TWI682431B - 半導體裝置的形成方法 - Google Patents
半導體裝置的形成方法 Download PDFInfo
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- TWI682431B TWI682431B TW106112738A TW106112738A TWI682431B TW I682431 B TWI682431 B TW I682431B TW 106112738 A TW106112738 A TW 106112738A TW 106112738 A TW106112738 A TW 106112738A TW I682431 B TWI682431 B TW I682431B
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- 238000000034 method Methods 0.000 title claims abstract description 180
- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 172
- 230000008569 process Effects 0.000 claims abstract description 106
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 97
- 238000002161 passivation Methods 0.000 claims abstract description 58
- 238000000059 patterning Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 51
- 239000003989 dielectric material Substances 0.000 claims description 39
- 238000004380 ashing Methods 0.000 claims description 32
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 29
- 239000001301 oxygen Substances 0.000 claims description 29
- 229910052760 oxygen Inorganic materials 0.000 claims description 29
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- 238000001312 dry etching Methods 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 9
- 229910052786 argon Inorganic materials 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- 238000001020 plasma etching Methods 0.000 claims description 6
- 239000000376 reactant Substances 0.000 claims description 3
- 238000013404 process transfer Methods 0.000 claims description 2
- 239000006227 byproduct Substances 0.000 abstract description 16
- 239000010410 layer Substances 0.000 description 224
- 239000000047 product Substances 0.000 description 53
- 239000000463 material Substances 0.000 description 44
- 239000012159 carrier gas Substances 0.000 description 30
- 239000011229 interlayer Substances 0.000 description 27
- 239000012535 impurity Substances 0.000 description 21
- 229910044991 metal oxide Inorganic materials 0.000 description 19
- 150000004706 metal oxides Chemical class 0.000 description 19
- 125000006850 spacer group Chemical group 0.000 description 19
- 238000002955 isolation Methods 0.000 description 18
- 239000007789 gas Substances 0.000 description 16
- 230000005669 field effect Effects 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 238000002513 implantation Methods 0.000 description 11
- 230000004888 barrier function Effects 0.000 description 10
- 238000001465 metallisation Methods 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 230000006641 stabilisation Effects 0.000 description 9
- 239000000126 substance Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000000203 mixture Substances 0.000 description 8
- 238000011105 stabilization Methods 0.000 description 8
- 239000004020 conductor Substances 0.000 description 7
- 239000011810 insulating material Substances 0.000 description 7
- 230000009969 flowable effect Effects 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 238000005498 polishing Methods 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000012546 transfer Methods 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000009616 inductively coupled plasma Methods 0.000 description 4
- 239000005368 silicate glass Substances 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 238000004528 spin coating Methods 0.000 description 4
- 238000005496 tempering Methods 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 239000003085 diluting agent Substances 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 230000000087 stabilizing effect Effects 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000000746 purification Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- BCMCBBGGLRIHSE-UHFFFAOYSA-N 1,3-benzoxazole Chemical compound C1=CC=C2OC=NC2=C1 BCMCBBGGLRIHSE-UHFFFAOYSA-N 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910017115 AlSb Inorganic materials 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 229910005898 GeSn Inorganic materials 0.000 description 1
- -1 InAlAs Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003028 elevating effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 150000001247 metal acetylides Chemical class 0.000 description 1
- 229910052914 metal silicate Inorganic materials 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31058—After-treatment of organic layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
半導體裝置與其形成方法中,可圖案化鈍化層。在實施例中,可採用與圖案化製程相同的蝕刻腔室,移除來自圖案化製程的副產物,同時移除圖案化製程中所用的光阻。上述製程可用於形成鰭狀場效電晶體裝置。
Description
本發明實施例關於半導體裝置的形成方法,更特別關於在蝕刻製程後移除光阻與副產物的方法。
由於積體電路的發明,多種電子構件如電晶體、二極體、電阻、電容、或類似物的積體密度持續改良,使半導體產業快速成長。大多積體密度改良來自於最小結構尺寸的持續縮小,可增加固定面積所能整合的構件數目。
然而縮小電晶體、二極體、電阻、電容、與類似物之最小結構尺寸,只是縮小半導體裝置的整體體積的方法之一。目前審查的其他方法,包含半導體裝置的其他方法。其他結構中的改良,可用以縮小結構尺寸。
本發明一實施例提供之半導體裝置的形成方法,包括:形成介電層於半導體基板上;圖案化介電層上的光阻;將半導體基板與光阻置入蝕刻腔室中;以蝕刻製程將光阻之圖案轉移至介電層;以及在自蝕刻腔室移開光阻前,先移除光阻。
本發明一實施例提供之半導體裝置的形成方法,包括:沉積光阻至基板上的介電材料上;圖案化光阻;經由光阻蝕刻介電材料,其中蝕刻介電材料之步驟採用來自於第一氧源的氧作為至少一反應物;以及在蝕刻介電材料後移除光阻,
其中移除光阻之步驟採用來自於第一氧源的氧。
本發明一實施例提供之半導體裝置的形成方法,包括:圖案化光阻以形成圖案化的光阻並露出介電材料;經由圖案化的光阻乾蝕刻介電材料;在乾蝕刻介電材料後,直接進行襯墊移除製程;以及在襯墊移除製程後,直接灰化光阻,其中乾蝕刻、襯墊移除製程、以及灰化均進行於單一蝕刻腔室中。
A-A、B/C-B/C‧‧‧剖線
D1‧‧‧第一距離
T1、T2‧‧‧厚度
W1‧‧‧第一寬度
W2‧‧‧第二寬度
W3‧‧‧第三寬度
30‧‧‧鰭狀場效電晶體
32、50、101‧‧‧基板
36、52、56‧‧‧鰭狀物
38、92、96‧‧‧閘極介電層
40、94、98‧‧‧閘極
42、44‧‧‧源極/汲極區
50B‧‧‧第一區
50C‧‧‧第二區
54‧‧‧隔離區
58‧‧‧虛置介電層
60‧‧‧虛置閘極層
62‧‧‧遮罩層
70、76‧‧‧虛置閘極
72、78‧‧‧遮罩
80‧‧‧閘極密封間隔物
82、84‧‧‧磊晶的源極/汲極區
86‧‧‧閘極間隔物
88、99、105‧‧‧層間介電層
90‧‧‧凹陷
100‧‧‧半導體裝置
102、104、106、108‧‧‧接點
103‧‧‧主動裝置
107‧‧‧金屬化層
109‧‧‧頂金屬層
111‧‧‧頂介電層
112‧‧‧第一蝕刻停止層
113‧‧‧第一鈍化層
115、302‧‧‧第一開口
116‧‧‧第一阻障層
117‧‧‧第一導電連接物
118‧‧‧蓋層
119‧‧‧第二鈍化層
120‧‧‧虛線
121‧‧‧底部
123‧‧‧頂部
125‧‧‧第一光阻
201‧‧‧蝕刻系統
202‧‧‧第一管線
203‧‧‧蝕刻品輸送系統
204‧‧‧蝕刻腔室
205‧‧‧歧管
206‧‧‧第二閥件
207‧‧‧承載氣體供應器
208‧‧‧第一閥件
210‧‧‧第二管線
211‧‧‧蝕刻品供應器
213‧‧‧蝕刻品控制器
215‧‧‧蝕刻腔室外殼
220‧‧‧第一電極
221‧‧‧上電極
222‧‧‧第一射頻產生器
223‧‧‧第二射頻產生器
225‧‧‧真空泵浦
227‧‧‧控制器
229‧‧‧淋浴頭
245‧‧‧安裝平台
301‧‧‧蝕刻製程
303‧‧‧副產物
305‧‧‧灰化製程
第1圖係一些實施例中,具有第一鈍化層與第二鈍化層的半導體裝置。
第2圖係一些實施例中,可用以圖案化第二鈍化層之蝕刻腔室。
第3A至3B圖係一些實施例中,自蝕刻製程移除副產物。
第4-9、10A-18A、10B-18B、10C-18C圖係一些實施例中,形成鰭狀場效電晶體的製程,其具有圖案化第二鈍化層之步驟。
下述內容提供的不同實施例或實例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說,形成第一構件於第二構件上的敘述包含兩者直接接觸,或兩者之間隔有其他額外構件而非直接接觸。此外,本發明之多種例子中可重複標號及/或符號,但這些重複僅用以簡化與清楚說明,不代表不同實施例及/或設置之間具有相同標號及/或符號的單元之間具有相同的對應關
係。
此外,空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件,而非侷限於圖示方向。元件亦可轉動90°或其他角度,因此方向性用語僅用以說明圖示中的方向。
如第1圖所示,半導體裝置100具有基板101、基板101上的主動裝置103、主動裝置103上的層間介電層105、以及層間介電層105上的金屬化層107。基板101可為實質上導體或電阻小於103Ω-公尺的半導體,且可包含摻雜或未摻雜的基體矽或絕緣層上半導體基板的主動層。一般而言,絕緣層上半導體基板包含半導體材料層如矽、鍺、矽鍺、絕緣層上矽、絕緣層上矽鍺、或上述之組合。其他可用基板包含多層基板、組成漸變基板、或混合取向基板。此外,此處所指的製程中基板101可為部份的半導體晶圓(完整晶圓並未圖示於第1圖中),其可切割於後續步驟中。
第1圖所示之主動裝置103為單一電晶體。然而本技術領域中具有通常知識者應理解,多種主動與被動裝置如電容、電阻、電感、與類似物亦可用於產生半導體裝置100所需的結構及功能。主動裝置103可由合適方法形成於基板101之中或之上。
層間介電層105可包含材料如摻雜硼的磷矽酸鹽玻璃,但亦可採用任何合適介電物。層間介電層105的形成製
程可為電漿增強化學氣相沉積,但亦可採用其他製程如低壓化學氣相沉積。層間介電層105之厚度可介於約100Å至約3000Å之間。
金屬化層107形成於基板101、主動裝置103、與層間介電層105上,其設計以連接多種主動裝置103以形成功能電路。在第1圖中的金屬化層107為雙層結構,其可由交錯的介電材料與導電材料所形成,且其形成方法可為任何合適製程如沉積、鑲嵌、雙鑲嵌、或類似方法。在一實施例中,金屬化層107為四層結構,且其與基板101之間隔有層間介電層105,但金屬化層107的實際層數取決於半導體裝置100的設計。
在金屬化層107之頂部,頂介電層111圍繞頂金屬層109。在一實施例中,頂金屬層109包含導電材料如銅或其他合適導體,而頂介電層111可為任何合適介電物如低介電常數介電材料。可先形成頂介電層111於其餘的金屬化層107上,接著可形成頂金屬層109於頂介電層111中,且上述形成方法可為鑲嵌製程或雙鑲嵌製程。在其他實施例中,亦可採用任何其他合適製程或材料以形成頂金屬層109與頂介電層111。
第一蝕刻停止層112用以保護下方的結構,並於蝕刻第一鈍化層113之後續製程中提供控制點。在一實施例中,第一蝕刻停止層112之組成可為電漿增強化學氣相沉積的氮化矽,但亦可為其他技術(如低壓化學氣相沉積、物理氣相沉積、或類似方法)形成之其他材料(如氮化物、碳化物、硼化物、上述之組合、或類似物)。第一蝕刻停止層112之厚度可介於約50Å至約2000Å之間,比如約200Å。
第一鈍化層113可形成於基板101上的第一蝕刻停止層112上。第一鈍化層113之組成可為一或多種合適的介電材料,如氧化矽、氮化矽、低介電常數介電物(如摻雜碳的氧化物)、極低介電常數介電物(如孔洞狀之摻雜碳的二氧化矽)、上述之組合、或類似物。第一鈍化層113之形成製程可為化學氣相沉積,但亦可採用其他合適製程。第一鈍化層113之厚度可介於約0.5微米至約5微米之間,比如約0.975微米。
在形成第一鈍化層113後,可形成第一開口115(如第1圖所示之一者)穿過第一鈍化層113。藉由移除部份的第一鈍化層113,可露出至少部份的頂金屬層109。第一開口115可用以形成頂金屬層109與第一導電連接物117之間的接點。第一開口115的形成方法可採用合適的光微影遮罩與蝕刻製程,但亦可採用任何合適的製程以露出部份的頂金屬層109,且第一開口115的第一寬度W1可介於約1微米至約10微米之間(如約2微米)。
當形成第一開口115後,可形成第一導電連接物117(如外部接點或再佈線層)。在一實施例中,在形成第一導電連接物117之前,可先形成第一阻障層116。在一實施例中,第一阻障層116可包含阻障材料如鈦、氮化鈦、上述之組合、或類似物,且其形成製程可為化學氣相沉積、物理氣相沉積、原子層沉積、或類似製程。第一阻障層116的厚度可介於約0.1微米至約20微米之間,比如約0.5微米。
第一導電連接物117可包含鋁/銅合金,但亦可採用其他材料如鋁或銅。第一導電連接物117的形成方法可採用沉
積製程如濺鍍以形成材料層(未圖示於第1圖中),並進行合適製程(如光微影遮罩及蝕刻)移除部份材料層,以形成第一導電連接物117。然而第一導電連接物117的形成方法可為任何其他合適製程。第一鈍化層113上的第一導電連接物117,其厚度T1可介於約2000Å至約20000Å之間,比如約8500Å。
在形成第一導電連接物117後,可將蓋層118置於第一導電連接物117上,以作為圖案化第一導電連接物117時的硬遮罩,以及作為後續曝光的蝕刻停止層。在一實施例中,蓋層118可包含一或多層的介電材料如氮氧化矽、氮化矽、碳氧化矽、碳化矽、上述之組合、或上述之多層結構,且其形成方法可為合適的沉積技術如濺鍍、化學氣相沉積、或類似方法。
在放置蓋層118後,可圖案化蓋層118作為硬遮罩層,以利圖案化第一導電連接物117。在一實施例中,蓋層118的圖案化方法可為放置、曝光、以及顯影光阻(未圖示於第1圖中),接著進行乾蝕刻如反應性離子蝕刻,以移除露出部份的蓋層118。在圖案化蓋層118後,可採用蓋層118作為硬遮罩以圖案化下方的第一導電連接物117與第一阻障層116。在一實施例中,第一導電連接物117與第一阻障層116的圖案化方法為乾蝕刻如反應性離子蝕刻,且圖案化的第一導電連接物117與第一阻障層116之第二寬度W2介於約1.5微米至20微米之間(比如約3微米)。
此外若情況需要,亦可蝕刻第一鈍化層113,以減少第一導電連接物117所露出之第一鈍化層113其厚度,且此蝕刻步驟可為前述蝕刻步驟、在前述蝕刻步驟之後接著進行、或
者與前述蝕刻步驟屬分開步驟。在一實施例中,第一鈍化層113其凹陷的第一距離D1可介於約200Å至約10000Å之間,比如約800Å。然而第一距離D1可為任何合適距離。
如第1圖所示,第二鈍化層119亦形成於第一鈍化層113及第一導電連接物117上,以提供第一導電連接物與其他下方結構所需之保護與隔離。在一實施例中,第二鈍化層119可為複合層,其具有虛線120分隔之底部121與頂部123。在一實施例中,第二鈍化層119之底部121可為介電聚合物材料如未摻雜的矽酸鹽玻璃,或任何合適材料如苯并噁唑或者聚醯亞胺或其衍生物。第二鈍化層119之底部121之形成方法可採用旋轉塗佈製程,其厚度T2可介於約2000至約20000之間(如4000)。然而在其他實施例中,第二鈍化層119之底部121可由任何合適方法形成,且可具有任何合適厚度。
第二鈍化層123的頂部123可位於第二鈍化層123的底部121上。在一實施例中,第二鈍化層123的頂部123可為介電材料如氮化矽或類似物,不過亦可採用任何其他合適材料。第二鈍化層119之頂部123的形成方法可為化學氣相沉積或物理氣相沉積,且其厚度可介於約2000至約20000之間(如6000)。然而在其他實施例中,第二鈍化層119之頂部123可由任何合適方法形成,且可具有任何合適厚度。
在形成第二鈍化層119後,形成第一光阻125於第二鈍化層119上,並圖案化第一光阻125以露出第二鈍化層119。在一實施例中,第一光阻125形成於第二鈍化層119上的方法可採用旋轉塗佈技術,且第一光阻125之厚度可介於約50
微米至約250微米之間(如約120微米)。在形成第一光阻125後,圖案化第一光阻125的方法可為以圖案化的能量源(如圖案化光源)照射第一光阻125以引發化學反應,進而引發圖案化光源照射之部份第一光阻125產生物理變化。接著施加顯影劑至曝光後的第一光阻125,藉由第一光阻的物理變化以選擇性地移除曝光部份(或非曝光部份)的第一光阻125,端視所需的圖案而定。在一實施例中,第一光阻125中的圖案其第三寬度W3介於約1微米至約10微米之間,比如約1.5微米。
第2圖為蝕刻系統201,其可採用第一光阻125作遮罩以圖案化第二鈍化層119與蓋層118。在一實施例中,蝕刻系統201可包含蝕刻品輸送系統203,其可輸送一或多種氣態蝕刻品至蝕刻腔室204中。蝕刻品輸送系統203可經由蝕刻品控制器213與歧管205提供多種所需的蝕刻品至蝕刻腔室204。蝕刻品輸送系統203可控制承載氣體的流速與壓力,以利蝕刻品輸送系統203控制進入蝕刻腔室204之蝕刻品的流速。
在一實施例中,蝕刻品輸送系統203可包含沿著承載氣體供應器207的多個蝕刻品供應器211。此外,雖然第2圖中僅有兩個蝕刻品供應器211,但此僅用於清楚說明。蝕刻品供應器211的個數可為任何合適數目,比如用於蝕刻系統201中的所需每一蝕刻品均可具有對應的蝕刻品供應器211。舉例來說,一實施例中需採用五種不同的蝕刻品,則可具有五個分開的蝕刻品供應器211。
每一個別的蝕刻品供應器211可為容器如氣體儲槽,其可位於蝕刻腔室204附近或遠離蝕刻腔室204。在其他實
施例中,蝕刻品供應器211可為單獨製備與輸送所需蝕刻品的裝置。蝕刻品供應器211可採用任何合適來源以提供所需的蝕刻品,且所有的這些來源完全屬於實施例所包含的範疇。
在一實施例中,個別的蝕刻品供應器211可經由具有第一閥件208之第一管線202,提供蝕刻品至蝕刻控制器213中。控制器227可控制第一閥件208,並控制與調整進入蝕刻腔室204之多種蝕刻品與承載氣體。
承載氣體供應器207可供應所需的承載氣體或稀釋氣體,其有助於推動或承載多種所需的蝕刻品至蝕刻腔室204。承載氣體可為鈍氣或其他氣體,其不與蝕刻氣體本身反應,亦不與蝕刻品反應後產生的副產物反應。舉例來說,承載氣體可為氮氣、氦氣、氬氣、上述之組合、或類似物,亦可採用其他合適的承載氣體。
承載氣體供應器207(或稀釋氣體供應器)可為容器如氣體儲槽,其可位於蝕刻腔室204附近或遠離蝕刻腔室204。在其他實施例中,承載氣體供應器207可為單獨製備與輸送所需承載氣體至蝕刻控制器213的裝置。承載氣體供應器207可採用任何合適來源以提供所需的承載氣體,且所有的這些來源完全屬於實施例所包含的範疇。承載氣體供應器207可經由具有第二閥件206之第二管線210,提供承載氣體至蝕刻控制器213中。上述第二管線210使承載氣體供應器207連接至第一管線202。控制器227亦可控制第二閥件206,並控制與調整進入蝕刻腔室204之多種蝕刻品與承載氣體。上述管線結合後導向蝕刻品控制器213,用以將控制後的氣體導入蝕刻腔室204中。
蝕刻腔室204可為任何所需的形狀,以適於分散蝕刻品使其接觸半導體裝置100。在第2圖所示之實施例中,蝕刻腔室204具有圓柱狀的側壁與底部。然而蝕刻腔室204並不限於圓柱狀,且可為任何其他合適形狀如中空立方體、八角形、或採用其他類似形狀。此外,蝕刻腔室外殼215可圍繞蝕刻腔室204,且蝕刻腔室外殼215之材料組成對多種製程材料來說屬惰性。如此一來,蝕刻腔室外殼215採用可抵抗蝕刻製程中的化學品與壓力之合適材料,比如鋼、不鏽鋼、鎳、鋁、上述之合金、上述之組合、或類似物。
此外,蝕刻腔室204與安裝平台245可為群集式工具系統(未圖示)的一部份。群集式工具系統可搭配自動處理系統,可在蝕刻製程前將半導體裝置100放置到蝕刻腔室204中;在蝕刻製程中支撐半導體裝置100;以及在蝕刻製程後自蝕刻腔室204移出半導體裝置100。
位於蝕刻腔室204中的安裝平台245可在蝕刻製程中,放置並控制半導體裝置100。安裝平台245可採用夾具、真空壓力、及或靜電力支撐半導體裝置100,亦可包含加熱與冷卻機制以控制製程中的半導體裝置100之溫度。在特定實施例中,安裝平台245可包含四個冷卻區如內部溫度區、中間溫度區、中間外部溫度區、與外部溫度區(未分別圖示),以在蝕刻製程中加熱與冷卻半導體裝置100。多種溫度區可採用氣態或液態熱傳材料,以準確地控制蝕刻製程中的半導體裝置100之溫度。在其他實施例中,可採用任何合適數目的加熱或冷卻區。
安裝平台245可額外包含第一電極220,其耦接至
第一射頻產生器222。在蝕刻製程中,第一射頻產生器222(受控於控制器227)可施加射頻電壓,使第一電極220具有電性偏壓。具有電性偏壓的第一電極220可提供偏壓至輸入的蝕刻品,有助於點火蝕刻品成電漿。此外,第一電極220亦維持偏壓以在蝕刻製程中維持電漿。
此外,第2圖所示之單一安裝平台245僅用以清楚說明而非侷限本發明。蝕刻腔室204中可包含任何數目的額外安裝平台245。如此一來,在單一蝕刻製程中可蝕刻多個半導體基板。
此外,蝕刻腔室204包含淋浴頭229。在一實施例中,淋浴頭229自歧管205接收多種蝕刻品,且有助於分散多種蝕刻品至蝕刻腔室204中。淋浴頭229可設計以均勻地分散蝕刻品,使不均勻擴散造成的製程問題最小化。在一實施例中,淋浴頭229可具有圓形設計,其開口可均勻分佈於淋浴頭上,使蝕刻品得以分散至蝕刻腔室204中。
蝕刻腔室204亦包含上電極221,其作為電漿產生器。在一實施例中,電漿產生器可為變壓器耦合電漿產生器與線圈。線圈可連接至第二射頻產生器223。第二射頻產生器223可用於提供功率至控制器227控制的上電極221,且在導入反應性蝕刻品時點燃電漿。
雖然上述之上電極221為變壓器耦合電漿產生器,但本發明實施例並不限於變壓器耦合電漿產生器。在其他實施例中,可採用產生電漿的任何合適方法如電感耦合電漿系統、磁增強反應性離子蝕刻、電子迴旋共振、遠端電漿產生器、
或類似方法。這些方法均屬實施例的範疇。
蝕刻腔室204可連接至真空泵浦225。在一實施例中,控制器227可控制真空泵浦225,以控制蝕刻腔室204中的壓力至所需值。此外,在完成蝕刻製程後,可採用真空泵浦抽出蝕刻腔室中的氣體,以準備移開半導體裝置100。
第3A圖係蝕刻製程301一開始的階段,其可形成第一開口302,並將第一光阻125之圖案轉移至第二鈍化層119及蓋層118。在一實施例中,蝕刻製程301之起始步驟為將所需蝕刻品置入蝕刻品供應器211中,並將所需的稀釋物置入承載氣體供應器207中。如此一來,蝕刻品與承載氣體至少部份取決於第二鈍化層119與蓋層118之材料。在一特定實施例中,第二鈍化層119為氮化矽與未摻雜的矽酸鹽玻璃之複合層,而蓋層118為氮氧化矽時,可將CF4、CHF3、氧、氮、氫、上述之組合、或類似物置入蝕刻品供應器211中,而承載氣體可為非反應性氣體如氬、氦、上述之組合、或類似物。然而其他實施例可採用任何合適的蝕刻品與稀釋物。
在特定實施例中,蝕刻製程301可包含多個個別步驟以轉移圖案。舉例來說,蝕刻製程301可包含吸盤固定步驟、主要蝕刻步驟、以及過蝕刻步驟。上述吸盤固定步驟可用以使蝕刻腔室準備好進行蝕刻製程,其初始程序可為吸盤固定穩定化程序,以調整蝕刻腔室204之壓力到介於約20mT至約800mT之間(如約300mT),且氣體比例可設定為介於5%至約95%(比如約50%)。吸盤固定穩定化程序亦可設定承載氣體(如氬)的流速介於約50sccm至約2000sccm之間,比如約1000sccm。B.P.壓力
可設定至低於約50Torr如約0Torr,溫度(T/B)可設定至(120/20),功率在60MHz與2MHz時可設定為0,且穩定化步驟可維持足夠的時間(如約15秒)以達穩定效果。
在吸盤固定穩定化程序已穩定蝕刻腔室204中的環境後,控制器227開始施加功率至一系列的步驟中。在一實施例中,控制器227可先施加60MHz之射頻功率(上電極221的源功率)到介於約20至約1000之間(如約200),並施加2MHz之射頻功率(第一電極220的偏功率)到介於約20至約1000之間(如約200)。且上述施加射頻功率的時間可介於約1秒至約100秒之間(比如1秒)。控制器227接著設定ESC HV為介於約500至約5000之間(比如600),其歷時約1秒至約100秒之間(如約1秒)。控制器227最後可設定B.P.為介於約5Torr至約100Torr之間(比如約10Torr),其歷時約1秒至約100秒之間(如約2秒)。
在吸盤固定步驟後,控制器227開始進行主要蝕刻製程。在一實施例中,控制器227開始蝕刻穩定化步驟,在點燃電漿前先降低壓力並穩定化所需蝕刻品的流速,其中上電極221與第一電極220的射頻功率均關閉以利穩定化步驟。在一實施例中,CF4、CHF3、與O2作為蝕刻品,蝕刻腔室204中的壓力降低到介於約20mT至約500mT(如約100mT),CF4之起始流速介於約20sccm至約800sccm之間(如約335sccm),CHF3之流速設定為介於約20sccm至約800sccm之間(如約165sccm),且氧氣之流速設定為介於約20sccm至約800sccm之間(如約100sccm)。承載氣體(如氬氣)之流速設定為介於約20sccm至約800sccm之間(如約250sccm)。此外,控制器227在此穩定化步驟中,可設定
B.P.為介於約5Torr至100Torr之間(如約30Torr),ESC HV為介於約500至約5000之間(如約850),並維持上述條件一段時間(比如介於約1秒至約100秒之間,如約20秒)直到蝕刻腔室穩定化。
在蝕刻穩定化步驟中的製程參數穩定後,控制器227進行點燃步驟以點燃蝕刻品成電漿,其設定60MHz的射頻功率到約100至約1000之間(如約200),並設定2MHz的射頻功率到約100至約100之間(如約200)。點燃步驟可維持到介於約1秒至約100秒之間(如約2秒),以確認電漿點燃。
在點燃產生後,第一蝕刻步驟可蝕刻第二鈍化層119與蓋層118。第一蝕刻步驟一開始可由控制器227設定60MHz的射頻功率為介於約200至約2000之間(如約1500),並設定2MHz的射頻功率為介於約200至約2000之間(如約1500)。第一蝕刻步驟蝕刻第一鈍化層119及/或蓋層118的時間可介於約5秒至約100秒之間(如約45秒)。
在第一蝕刻步驟後可進行第二蝕刻步驟。在一實施例中,第二蝕刻步驟中的控制器227使進入蝕刻腔室之CHF3的流速停止,並增加CF4之流速到介於約20sccm至約1000sccm之間(如500sccm)。此外,氧氣流速可設定為介於約20sccm至約1000sccm之間(如約75sccm),且2MHz的射頻功率可設定為介於約200至約2000之間(如約1800)。此外,控制器227可設定ESC HV為介於約950,且上述條件可維持到介於約5秒至約100秒之間(如約86秒)。
當主要蝕刻製程完成後,可進行過蝕刻製程以確認自第二鈍化層119移除所有的介電材料。在一實施例中,過
蝕刻製程一開始包括過蝕刻的漸變步驟,其中60MHz的射頻功率減少到介於約20至約1000(如約500),且2MHz的射頻功率減少到介於約200至約2000(如約500)。此外,承載氣體的流速降低到介於約20sccm至約800sccm之間(如約150sccm),B.P.可設定為約5Torr至約100Torr之間(如約20Torr),且ESC HV可設定為約500至約5000之間(如約700)。上述過蝕刻漸變步驟可維持到介於約1秒至約100秒之間(如約3秒)。
在完成過蝕刻漸變步驟後,可在相同條件下進行過蝕刻。過蝕刻的時間足以移除第二鈍化層119的材料。如此一來,過蝕刻的時間介於約1秒至約100秒之間(如約60秒)。
在主要蝕刻將第一光阻125的圖案轉移至第二鈍化層119後並露出蓋層118後,可進行襯墊移除步驟以移除蓋層118。在一實施例中,襯墊移除製程一開始包含襯墊移除漸變步驟,其中60MHz的射頻功率降低到介於約200至約2000之間(如約300),2MHz的射頻功率降低到介於約20至約1000之間(如約100),而氣體比例可設定為介於約5至約95之間(如約75)。此外,承載氣體之流速增加到介於約20sccm至約1000sccm之間(如約200sccm),CF4的流速降低到介於約20sccm至約1000sccm之間(如約200sccm),B.P.可設定為介於約5Torr至約100Torr之間(如約10torr),且ESC HV可設定為介於約500至約5000之間(如約2000)。襯墊移除製程可持續約1秒至約100秒(如約3秒)。
在襯墊移除步驟完成後,可改變襯墊移除步驟之壓力但維持其他參數後繼續進行。舉例來說,此步驟的壓力可增加至約20mTorr至約1000mTorr之間(如約150mTorr)。上述襯
墊移除步驟的時間足以移除蓋層118,以露出下方的第一導電連接物117。如此一來,襯墊移除步驟的時間可介於約1秒至約100秒之間(如約60秒)。
在襯墊移除後,進行卸除步驟以準備自半導體裝置100移除第一光阻125。在一實施例中,卸除步驟一開始可進行卸除漸變步驟,其蝕刻腔室中的壓力降低到介於約20mTorr至約1000mTorr之間(如75mTorr),ESC HV降低到介於約500至約5000之間(如3000),且氣體比例可設定為介於約5至約95之間(如約50)。此外,60MHz的射頻功率降低到介於約200至約2000之間(如約500),而2MHz的射頻功率降低至低於100(如0),且承載氣體的流速增加到介於約20sccm至約1000sccm之間(如約520sccm)。卸除漸變階段可持續約1秒至約100秒之間(如約2秒)。
當完成卸除漸變步驟後,第一卸除步驟降低ESC HV至約0。在一實施例中,第一卸除步驟可持續約1秒至約100秒,比如約20秒。接著可進行第二卸除步驟以降低射頻功率。在一實施例中,第二卸除步驟可降低60MHz的射頻功率至約0,其可持續約1秒至約100秒之間(比如約10秒)。
此外,蝕刻製程的特定實施例已搭配第2至3A圖說明如上,但這些內容僅用以說明而非侷限實施例。相反地,可採用蝕刻品、承載氣體、與製程條件的任何合適實施例。這些組合均屬實施例的範疇。
然而上述蝕刻製程301將上方之第一光阻125的圖案轉移至第二鈍化層119與蓋層118時,蝕刻反應的副產物303
(見第3A圖)會沿著第二鈍化層119與蓋層118之側壁累積。這些副產品可包含硬化的聚合物如C-F副產物,且未自第一開口302移除的副產物303將被視作缺陷且易降低可信度。然而一些移除製程如濕蝕刻,可能進一步損傷第二鈍化層119的材料。
為解決上述問題,第3B圖顯示半導體裝置100保留於相同的蝕刻腔室204中,可採用灰化製程305移除第一光阻215與副產物303。在一實施例中,灰化製程305之壓力可介於約2Torr至約500mTorr之間(如約25mTorr),源功率可介於約100W至約1500W(如約800W),偏功率可小於約500W,且氣體如氮氣、氧氣、與氬氣的流速可小於約1000sccm。在特定實施例中,可特別控制氧氣對氮氣與氬氣的比例,其中氧氣比例可介於0至100%之間。
在另一實施例中,灰化製程305一開始可先進行預熱灰化步驟,其中蝕刻腔室204中的壓力增加到介於約500mTorr至約10000mTorr之間(如約6000mTorr),且蝕刻腔室204中的加熱器可設定為介於約50℃至約250℃之間(如約200℃),且升降頂桿設定為下降。此外,功率仍設定為0,且控制器可充新導入蝕刻品如氧氣,其流速可介於約100sccm至約10000sccm(如約9000sccm),並可導入承載氣體如氮氣,其流速可介於約50sccm至約1500sccm(如約1000sccm)。預熱灰化製程可持續約1秒至約100秒,比如約25秒。
在預熱灰化製程時,可進行穩定化灰化步驟以穩定蝕刻腔室204,其可用於後續剝除步驟。在一實施例中,蝕刻腔室204的壓力可降低到介於約50mTorr至約1500mTorr之間
(如約900mTorr)。此外,蝕刻品(如氧)的流速可降低到介於約500sccm至約10000sccm之間(如約5400sccm),而承載氣體的流速可降低到介於約50sccm至約1000sccm之間(如約600sccm)。穩定化灰化步驟可持續至蝕刻腔室204穩定化,且持續時間可介於約1秒至約100秒之間(如約10秒)。
在進行穩定化灰化步驟以穩定蝕刻腔室204後,進行剝除步驟以移除第一光阻125。在一實施例中,剝除步驟一開始可由控制器施加功率,其介於約500至約5000之間(如約3500)。剝除步驟可持續至足以自開口302的側壁移除第一光阻125與副產品303,且持續時間可介於約1秒至約100秒之間(如約60秒)。
在又一實施例中,蝕刻製程可採用氧氣作為灰化製程的唯一蝕刻品。在此實施例中,氧氣灰化的穩定化步驟一開始將蝕刻腔室204的壓力設定為介於約50mTorr至約1000mTorr之間(如約300mTorr),T/B溫度設定為介於約100/10至約500/50之間(比如約120/20),且氣體比例設定為介於約5至約95(如約50)。此外,導入的蝕刻品(氧氣)流速可介於約500sccm至約5000sccm之間(如約1800sccm),而不需導入任何其他蝕刻品或承載氣體。氧氣灰化的穩定化步驟可持續至蝕刻腔室204穩定化,且持續時間可介於約約1秒至約100秒之間(如約10秒)。
在蝕刻腔室204穩定後,可進行轟擊步驟。在一實施例中,烘擊步驟一開始可由控制器提升60MHz的功率到介於約50至約1000之間(如約200),並維持關閉2MHz的功率。轟擊步驟可維持約1秒至約100秒之間,比如約5秒。
在轟擊步驟後,可採用主要灰化步驟以移除第一光阻125。在一實施例中,主要灰化步驟可採用先前設定的條件,除了控制器227將蝕刻腔室中的壓力降低到介於約20mTorr至約1000mTorr之間(如約100mTorr)。主要灰化步驟可持續到足以移除第一光阻125,且持續時間可介於約1秒至約100秒之間(如約15秒)。
在主要灰化步驟移除第一光阻125後,可進行淨化步驟。在一實施例中,可關閉60MHz的功率,並將蝕刻腔室204中的壓力降低到介於約20mTorr至約1000mTorr之間(如約50mTorr)。此外,關閉蝕刻品流(氧氣),並將承載氣體(如氬氣)的流速設定為介於約50sccm至約1500sccm之間(如約1000sccm)。上述淨化步驟可持續約1秒至約100秒,比如約10秒。
藉由自第二鈍化層119剝除第一光阻層125,同時自第一開口302之側壁移除副產物303,以及所有的蝕刻與灰化步驟均進行於單一蝕刻腔室204中,可將四種已知機器(如蝕刻、灰化、濕蝕刻、與襯墊移除步驟所用之個別機器)整合成單一的蝕刻機器,可讓物主的成本降低,且蝕刻步驟、襯墊移除步驟、與灰化步驟可達較快產能。上述實施例採用單一機器而非多重機器,可省略濕式清潔製程,進而省略乾蝕刻至灰化之間與灰化至濕蝕刻之間所需的等待時間控制。
此外,藉由上述之灰化製程305,可有效移除副產物303,有助於避免聚合物剝離問題,且不會負面地衝擊第二鈍化層119的性質。上述問題會導致裝置缺陷,並降低製程的整體良率。如此一來,降低缺陷與可能產生的剝離可得較佳的
KLA、WAT、與效能可信度,而不需調整第二鈍化層119的厚度或第一導電連接物117的組成。
在移除第一光阻125後,可進行額外製程以助完成半導體裝置100。在一實施例中,可形成凸塊下金屬化層(未圖示於第3圖中)與第一外部連接物如焊料球或銅柱(亦未圖示於第3圖中),以物理或電性連接至第一導電連接物117,進而提供外部接點至半導體裝置100。
第4圖係可用於一些實施例之鰭狀場效電晶體30的三維圖。鰭狀場效電晶體30包含鰭狀物36於基板32上。基板32包含隔離區34,而鰭狀物36凸起於相鄰的隔離區34之間。閘極介電層38沿著鰭狀物36之側壁且位於鰭狀物36的上表面上,而閘極40位於閘極介電層38上。源極/汲極區42與44位於鰭狀物36的相反兩側(對應閘極介電層38與閘極40)中。第4圖可搭配後述之剖視圖進一步說明。剖線A-A橫越鰭狀場效電晶體30之通道、閘極介電層38、與閘極40。剖線B/C-B/C垂直於剖線A-A,且沿著鰭狀物36的長度方向,比如源極/汲極區42與44之間的電流方向。後續圖式將對應上述剖線以清楚說明。
此處提及的一些實施例概念為採用閘極後製製程形成的鰭狀場效電晶體。在其他實施例中,可採用閘極先製製程。此外,一些實施例可用於平面的裝置如平面的場效電晶體。
第14至18C圖係採用第二鈍化層119形成鰭狀場效電晶體之方法的中間階段其剖視圖。除了多重鰭狀場效電晶體外,第14至18圖沿著第4圖中的A-A剖線。在第10A至18C圖中,圖式尾端為A者沿著類似的剖線A-A,圖式尾端為B者沿著類似
的剖線B/C-B/C且對應基板上的第一區,而圖式尾端為C者沿著類似的剖線B/C-B/C且對應基板上的第二區。
第5圖顯示基板50。基板50可為半導體基板如基體半導體、絕緣層上半導體基板、或類似物,且其可摻雜(p型摻質或n型摻質)或未摻雜。基板50可為晶圓如矽晶圓。一般而言,絕緣層上半導體基板包含半導體材料層形成於絕緣層上。舉例來說,絕緣層可為埋置氧化物層、氧化矽層、或類似物。絕緣層形成於基板上,一般為矽或玻璃基板。此外,亦可採用其他基板如多層或組成漸變的基板。在一些實施例中,基板50的半導體材料可包含矽或鍺;半導體化合物如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦;半導體合金如SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP;或上述之組合。
基板50具有第一區50B與第二區50C。第一區50B(對應後續圖式結尾為B者)可用於形成n型裝置,比如N型金氧半電晶體如n型鰭狀場效電晶體。第二區50C(對應後續圖式結尾為C者)可用於形成p型裝置,比如P型金氧半電晶體如p型鰭狀場效電晶體。
如第6與7圖所示,形成鰭狀物52,與相鄰鰭狀物52之間的隔離區54。在第6圖中,鰭狀物52形成於基板50中。在一些實施例中,鰭狀物52形成於基板50中的方法可為蝕刻溝槽於基板50中。上述蝕刻可為任何可行的蝕刻製程,比如反應性離子蝕刻、中子束蝕刻、類似方法、或上述之組合。上述蝕刻可為非等向蝕刻。
在第7圖中,形成絕緣材料於相鄰的鰭狀物52之間,以形成隔離區54。絕緣材料可為氧化物如氧化矽、氮化物、類似物、或上述之組合,且其形成方法可為高密度電漿化學氣相沉積、可流動化學氣相沉積(在遠端電漿系統中沉積化學氣相沉積為主的材料,其之後硬化以轉變為另一材料如氧化物)、類似方法、或上述之組合。此外亦可採用任何可行製程形成的其他絕緣材料。在形成絕緣材料後可進行回火。在此實施例中,絕緣材料為可流動化學氣相沉積製程形成的氧化矽。形成的絕緣材料可稱作隔離層54。此外在第7圖中,可進行平坦化製程(如化學機械研磨)以移除任何多餘的絕緣材料,使隔離區54之上表面與鰭狀物52的上表面共平面。
如第8圖所示,使隔離區54凹陷以形成淺溝槽的隔離區54。隔離區54凹陷後,第一區50B與第二區50C之鰭狀物56自相鄰的隔離區54之間凸起。此外,隔離區54的上表面可為平坦表面(如圖示),凸面、凹面(如碟狀)、或上述之組合。隔離區54的上表面形狀如平坦表面、凸面、及/或凹面,可由合適的蝕刻形成。隔離區54之凹陷方法可採用可行的蝕刻製程,端視隔離區54之材料選擇而定。舉例來說,化學的氧化物移除可採用CERTAS®蝕刻、應用材料之SICONI工具、或稀氫氟酸。
本技術領域中具有通常知識者應理解,上述第6至8圖的製程僅為形成鰭狀物56的一例。在其他實施例中,可形成介電層於基板50的上表面上;可形成溝槽蝕刻穿過介電層、磊晶成長同質磊晶結構於溝槽中、以及可使介電層凹陷,讓同質磊晶結構自介電層凸起以形成鰭狀物。在其他實施例中,異
質磊晶結構可作為鰭狀物。舉例來說,可讓第7圖中的鰭狀物52凹陷,且可磊晶成長不同於鰭狀物52的材料於凹陷處。在又一實施例中,可形成介電層於基板50的表面上、可形成溝槽蝕刻穿過介電層、可採用不同於基板50之材料磊晶成長於溝槽中、以及可使介電層凹陷,讓異質磊晶結構自介電層凸起以形成鰭狀物。在一些實施例中,磊晶成長同質磊晶結構或異質磊晶結構,且在成長時可臨場摻雜成長的材料,以省略之前後之後的佈植。不過其他實施例可採用臨場佈植搭配佈植摻雜。另一方面,磊晶成長於N型金氧半區中的材料不同於P型金氧半區中的材料具有優點。在多種實施例中,鰭狀物56可包含矽鍺(SixGe1-x,其中x介於約0至100),碳化矽、純或實質上純鍺、III-V族半導體化合物、II-VI族半導體化合物、或類似物。舉例來說,用以形成III-V族半導體化合物的可行材料包含但不限於InAs、AlAs、GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlP、GaP、或類似物。
在第8圖中,可形成適當的井區至鰭狀物56、鰭狀物52、及/或基板50中。舉例來說,p型井可形成於第一區50B中,而n型井可形成於第二區50C中。
可採用光阻或其他遮罩(未圖示),以達不同區域(如第一區50B與第二區50C)所用的不同佈植步驟。舉例來說,光阻形成於第一區50B之鰭狀物56與隔離區54上。圖案化光阻以露出基板50上的第二區50C(如P型金氧半區)。光阻的形成方法可為旋轉塗佈技術,且其圖案化方法可採用可行的光微影技術。在圖案化光阻後,可佈植n型雜質至第二區50C中,且光阻
可作為遮罩以實質上避免n型雜質佈植至第一區50B(如N型金氧半區)中。n型雜質可為磷、砷、或類似物,其佈植至第二區中的濃度小於或等於1018cm-3,比如介於約1017cm-3至約1018cm-3之間。在佈植後可移除光阻,其移除方法可為可行的灰化製程。
在佈植第二區50C後,形成光阻於第二區50C中的鰭狀物56與隔離區54上。圖案化光阻以露出基板50上的第一區50B(如N型金氧半區)。光阻的形成方法可為旋轉塗佈技術,且其圖案化方法可採用可行的光微影技術。在圖案化光阻後,可佈植p型雜質至第一區50B中,且光阻可作為遮罩以實質上避免p型雜質佈植至第二區50C(如P型金氧半區)中。p型雜質可為硼、BF2、或類似物,其佈植至第一區中的濃度小於或等於1018cm-3,比如介於約1017cm-3至約1018cm-3之間。在佈植後可移除光阻,其移除方法可為可行的灰化製程。
在佈植第一區50B與第二區50C後,可進行回火以活化佈植的p型雜質與n型雜質。佈植亦形成p型井於第一區50B(如N型金氧半區)中,並形成n型井於第二區50C(如P型金氧半區)中。在一些實施例中,可在成長步驟中臨場摻雜磊晶的鰭狀物之成長材料並省略佈植,不過亦可採用臨場摻雜搭配佈植摻雜。
在第9圖中,虛置介電層58形成於鰭狀物56上。舉例來說,虛置介電層58可為氧化矽、氮化矽、上述之組合、或類似物,其形成方法可依據可行技術沉積或熱成長。虛置閘極層60形成於虛置介電層58上,而遮罩層62形成於虛置閘極層60
上。在虛置閘極層60沉積於虛置介電層58上後,可接著進行平坦化製程如化學機械研磨。遮罩層62可沉積於虛置閘極層60上。舉例來說,虛置閘極層60之組成可為多晶矽,但亦可採用對隔離區54具有高蝕刻選擇性的其他材料。舉例來說,遮罩層62可包含氮化矽或類似物。在此例中,形成單一虛置閘極層60與單一遮罩層62於第一區50B及第二區50C上。在其他實施例中,可分別形成不同的虛置閘極層於第一區50B與第二區50C中,以及分別形成不同的遮罩層於第一區50B與第二區50C中。
在第10A、10B、與10C圖中,可採用可行的光微影與蝕刻技術圖案化遮罩層62,以形成遮罩72於第一區50B中(見第10B圖),並形成遮罩78於第二區50C中(見第10C圖)。接著可採用可行的蝕刻技術,將遮罩72與78的圖案轉移至虛置閘極層60與虛置介電層58,以形成虛置閘極70於第一區50B中,並形成虛置閘極76於第二區50C中。虛置閘極70與76覆蓋個別的鰭狀物56之通道區。虛置閘極70與76之長度方向實質上垂直於個別磊晶的鰭狀物之長度方向。
在第11A、11B、與11C圖中,閘極密封間隔物80可形成於個別的虛置閘極70與76及/或鰭狀物56其露出的表面上。進行熱氧化或沉積製程,再進行非等向蝕刻,可形成閘極密封間隔物80。
在形成閘極密封間隔物80後,可進行佈植以形成輕摻雜源極/汲極區。與前述之佈植類似,可形成遮罩如光阻於第一區50B(如N型金氧半區)上以露出第二區50C(如P型金氧半區),並將p型雜質佈植至第二區50C中露出的鰭狀物56
中。接著可移除遮罩,並形成遮罩如光阻於第二區50C上以露出第一區50B,並將n型雜質佈植至第一區50B中露出的鰭狀物56中。接著可移除遮罩。n型雜質可為前述之任何n型雜質,而p型雜質可為前述之任何p型雜質。輕源極/汲極區之雜質濃度可介於約1015cm-3至約1016cm-3之間。可進行回火以活化佈植的雜質。
在第11A、11B、與11C圖中,磊晶的源極/汲極區82與84形成於鰭狀物56中。在第一區50B中,磊晶的源極/汲極區82形成於鰭狀物56中,因此每一虛置閘極70位於每一對相鄰之磊晶的源極/汲極區82之間。在一些實施例中,磊晶的源極/汲極區82可延伸至鰭狀物52中。在第二區50C中,磊晶的源極/汲極區84形成於鰭狀物56中,因此每一虛置閘極76位於每一對相鄰之磊晶的源極/汲極區84之間。在一些實施例中,磊晶的源極/汲極區84可延伸至鰭狀物52中。
第一區50B(如N型金氧半區)中之磊晶的源極/汲極區82其形成方法,可為遮罩第二區50C(如P型金氧半區),並順應性地沉積虛置間隔物層於第一區50B中,再進行非等向蝕刻以形成沿著第一區50B中的虛置閘極70及/或閘極密封間隔物80之側壁的虛置閘極間隔物(未圖示)。接著蝕刻第一區50B中磊晶鰭狀物的源極/汲極區,以形成凹陷。磊晶的源極/汲極區82可包含任何可行材料,比如適用於n型鰭狀場效電晶體的材料。舉例來說,若鰭狀物56為矽,則磊晶的源極/汲極區82可包含矽、SiC、SiCP、SiP、或類似物。磊晶的源極/汲極區82可具有自鰭狀物56之個別表面隆起的表面,亦可具有多個晶
面。接著移除第一區50B中的虛置閘極間隔物,如同第二區50C上的遮罩,且其移除方法可為蝕刻。
第二區50C(如P型金氧半區)中的磊晶的源極/汲極區84其形成方法,可為遮罩第一區50B(如N型金氧半區),順應性地沉積虛置間隔物層於第二區50C中,再進行非等向蝕刻,以沿著第二區50C中的虛置閘極76及/或閘極密封間隔物80形成虛置閘極間隔物(未圖示)。接著蝕刻第二區50C中的磊晶鰭狀物之源極/汲極區,以形成凹陷。第二區50C中磊晶的源極/汲極區84可磊晶成長於凹陷中。磊晶的源極/汲極區84可包含任何可行材料,比如適用於p型鰭狀場效電晶體的材料。舉例來說,若鰭狀物56為矽,則磊晶的源極/汲極區84可包含SiGe、SiGeB、Ge、GeSn、或類似物。磊晶的源極/汲極區84可具有自鰭狀物56的個別表面隆起的表面,且可具有晶面。之後可移除第二區50C中的虛置閘極間隔物,如同第一區50B上的遮罩,且其移除方法可為蝕刻。
在第12A、12B、與12C圖中,閘極間隔物86形成於沿著虛置閘極70與76之側壁的閘極密封間隔物80上。閘極間隔物85的形成方法,可為順應性地沉積材料後接著非等向蝕刻材料。閘極間隔物86的材料可為氮化矽、SiCN、上述之組合、或類似物。
可將摻質佈植至磊晶的源極/汲極區82與84及/或磊晶鰭狀物,以形成源極/汲極區,如前述形成輕摻雜的源極/汲極區之製程。接著進行回火。源極/汲極區之雜質濃度可介於約1019cm-3至約1021cm-3之間。用於第一區50B(如N型金氧半
區)中的源極/汲極區之n型雜質,可為前述之任何n型雜質。用於第二區50C(如P型金氧半區)中的源極/汲極區之p型雜質,可為前述之任何p型雜質。在其他實施例中,磊晶的源極/汲極區82與84可在成長時臨場摻雜。
在第13A、13B、13C、與13D圖中,沉積層間介電層88於第12A、12B、與12C圖所示的結構上。在一實施例中,層間介電層88為可流動膜,其形成方法為可流動的化學氣相沉積。在一些實施例中,層間介電層88之組成為介電材料如磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃、或類似物,且其沉積方法可為適當方法如化學氣相沉積或電漿增強化學氣相沉積。
在第14A、14B、與14C圖中,可進行平坦化製程如化學機械研磨,使層間介電層88之上表面與虛置閘極70及76之上表面齊平。化學機械研磨亦可移除虛置閘極70與76上的遮罩72與78。綜上所述,可自層間介電層88露出虛置閘極70與76的上表面。
在第15A、15B、15C圖中,蝕刻移除虛置閘極70與76與直接位於虛置閘極70與76下的部份虛置介電層58,以形成凹陷90。每一凹陷90露出個別鰭狀物56之通道區。每一通道區位於相鄰之磊晶的源極/汲極區82與84之間。在上述蝕刻移除步驟中,蝕刻虛置閘極70與76時的虛置介電層58可作為蝕刻停止層。在移除虛置閘極70與76之後,可移除虛置介電層58與閘極密封間隔物80。
在第16A、16B、與16C圖中,形成閘極介電層92
與96以及閘極94與98,作為置換後的閘極結構。閘極介電層92與96順應性地沉積於凹陷90中,比如沉積於鰭狀物56之上表面與側壁上、閘極間隔物86之側壁上、以及層間介電層88的上表面上。在一些實施例中,閘極介電層92與96包含氧化矽、氮化矽、或上述之多層結構。在其他實施例中,閘極介電層92與96包含高介電常數介電材料,且這些實施例中的閘極介電層92與96其k值大於約7.0,其可包含Hf、Al、Zr、La、Mg、Ba、Ti、Pb、或上述之組合的金屬氧化物或矽酸鹽。閘極介電層92與96的形成方法可包含分子束磊晶、原子層沉積、電漿增強化學氣相沉積、或類似方法。
接著分別沉積閘極94與98於閘極介電層92與96上,其填入凹陷90之其餘部份。閘極94與98之組成可為含金屬材料如TiN、TaN、TaC、Co、Ru、Al、上述之組合、或上述之多層結構。在填入閘極94與98之後,步驟228進行平坦化製程如化學機械研磨以移除超出層間介電層88之上表面之多餘的部份閘極介電層92與96及閘極94與98。保留之部份閘極介電層94與98及閘極介電層92與96即鰭狀場效電晶體其置換後的閘極結構。
閘極介電層92與96可同時形成,因此兩者可由相同材料組成。閘極94與98可同時形成,因此兩者可由相同材料組成。然而其他實施例之閘極介電層92與96可由不同製程形成,因此兩者可由不同材料組成。閘極94與98可由不同製程形成,因此兩者可由不同材料組成。在使用不同製程時,可採用多種遮罩步驟以遮罩並露出適當區域。
在第17A、17B、與17C圖中,層間介電層99沉積於層間介電層88上。如第17A、17B、與17C圖所示,接點102與104穿過層間介電層99與層間介電層88,而接點106與108穿過層間介電層99。在一實施例中,層間介電層99為可流動化學氣相沉積法形成的可流動膜。在一些實施例中,層間介電層99之組成為介電材料如磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃、或類似物,且其沉積方法可為任何合適方法如化學氣相沉積或電漿增強化學氣相沉積。用於接點102與104之開口穿過層間介電層88與99。用於接點106與108之開口穿過層間介電層99。這些開口可同時形成於相同製程或分開的製程中。開口的形成方法可為可行的光微影與蝕刻技術。襯墊(如擴散阻障層、黏著層、或類似物)與導電材料可形成於開口中。襯墊可包含鈦、氮化鈦、鉭、氮化鉭、或類似物。導電材料可包含銅、銅合金、銀、金、鎢、鋁、鎳、或類似物。可進行平坦化製程如化學機械研磨,以自層間介電層99的表面移除多餘材料。保留的襯墊與導電材料即形成開口中的接點102與104。可進行回火製程以分別形成矽化物於磊晶的源極/汲極區82與84及接點102與104之間的界面。接點102物理與電性耦接至磊晶的源極/汲極區82,接點104物理與電性耦接至磊晶的源極/汲極區84,接點106物理與電性耦接至閘極94,而接點108物理與電性耦接至閘極98。
在第18A、18B、與18C圖中,第一鈍化層113與第二鈍化層119形成於層間介電層99上。在形成第一鈍化層113與第二鈍化層119後,可採用第1至3B圖之步驟圖案化第二鈍化層
119,有助於移除副產物303,並避免副產物303相關的缺陷存在於高效率製程中。
在一實施例中,半導體裝置的形成方法包括:形成介電層於半導體基板上;圖案化介電層上的光阻;將半導體基板與光阻置入蝕刻腔室中;以蝕刻製程將光阻之圖案轉移至介電層;以及在自蝕刻腔室移開光阻前,先移除光阻。
在另一實施例中,半導體裝置的形成方法包括:沉積光阻至基板上的介電材料上;圖案化光阻;經由光阻蝕刻介電材料,其中蝕刻介電材料之步驟採用來自於第一氧源的氧作為至少一反應物;以及在蝕刻介電材料後移除光阻,其中移除光阻之步驟採用來自於第一氧源的氧。
在又一實施例中,半導體裝置的形成方法包括:圖案化光阻以形成圖案化的光阻並露出介電材料;經由圖案化的光阻乾蝕刻介電材料;在乾蝕刻介電材料後,直接進行襯墊移除製程;以及在襯墊移除製程後,直接灰化光阻,其中乾蝕刻、襯墊移除製程、以及灰化均進行於單一蝕刻腔室中。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明作基礎,設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解,這些等效置換並未脫離本發明精神與範疇,並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
100‧‧‧半導體裝置
101‧‧‧基板
103‧‧‧主動裝置
105‧‧‧層間介電層
107‧‧‧金屬化層
109‧‧‧頂金屬層
111‧‧‧頂介電層
112‧‧‧第一蝕刻停止層
113‧‧‧第一鈍化層
115、302‧‧‧第一開口
116‧‧‧第一阻障層
117‧‧‧第一導電連接物
119‧‧‧第二鈍化層
120‧‧‧虛線
121‧‧‧底部
123‧‧‧頂部
125‧‧‧第一光阻
301‧‧‧蝕刻製程
303‧‧‧副產物
Claims (10)
- 一種半導體裝置的形成方法,包括:形成一介電層於一半導體基板上;圖案化該介電層上的一光阻;將該半導體基板與該光阻置入一蝕刻腔室中;以一反應性離子蝕刻製程將該光阻之圖案轉移至該介電層;以及在自該蝕刻腔室移開該光阻前,先自該介電層移除該光阻,移除該光阻之步驟更包括:一預熱灰化步驟,具有一第一組製程條件;以及一剝除步驟,具有與該第一組製程條件不同的一第二組製程條件。
- 如申請專利範圍第1項所述之半導體裝置的形成方法,其中該介電層更包括:一第一介電材料;以及一第二介電材料,位於該第一介電材料上,其中該第二介電材料不同於該第一介電材料。
- 如申請專利範圍第2項所述之半導體裝置的形成方法,其中該介電層位於一第一鈍化層上。
- 一種半導體裝置的形成方法,包括:沉積一光阻至一基板上的一介電材料上;圖案化該光阻;經由該光阻蝕刻該介電材料,其中蝕刻該介電材料之步驟採用一反應性離子蝕刻製程,以來自於一第一氧源的氧作 為至少一反應物;以及在蝕刻該介電材料後移除該光阻,其中移除該光阻之步驟採用來自於該第一氧源的氧,移除該光阻之步驟更包括:一預熱灰化步驟,具有一第一組製程條件;以及一剝除步驟,具有與該第一組製程條件不同的一第二組製程條件。
- 如申請專利範圍第4項所述之半導體裝置的形成方法,其中蝕刻該介電材料與移除該光阻的步驟進行於相同的蝕刻腔室中。
- 如申請專利範圍第4或5項所述之半導體裝置的形成方法,其中移除該光阻之步驟只採用氧移除該光阻。
- 一種半導體裝置的形成方法,包括:圖案化一光阻以形成一圖案化的光阻並露出於一頂金屬層之上的一介電材料;經由該圖案化的光阻乾蝕刻該介電材料,其中乾蝕刻該介電材料使用一電漿製程;在乾蝕刻該介電材料後,直接進行一襯墊移除製程;以及在該襯墊移除製程後,直接灰化該光阻,其中該乾蝕刻、該襯墊移除製程、以及該灰化均進行於單一蝕刻腔室中。
- 如申請專利範圍第7項所述之半導體裝置的形成方法,其中灰化該光阻之步驟包括將光阻暴露至不含其他蝕刻品的氧氣。
- 如申請專利範圍第7項所述之半導體裝置的形成方法,其中灰化該光阻之步驟包括將光阻暴露至氧氣與氮氣。
- 如申請專利範圍第9項所述之半導體裝置的形成方法,其中灰化該光阻之步驟更包括將光阻同時暴露至氧氣、氮氣、與氬氣。
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Also Published As
Publication number | Publication date |
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CN107452614B (zh) | 2021-07-06 |
US11217485B2 (en) | 2022-01-04 |
US20170316981A1 (en) | 2017-11-02 |
US11776853B2 (en) | 2023-10-03 |
US20220130729A1 (en) | 2022-04-28 |
US20200152516A1 (en) | 2020-05-14 |
TW201738931A (zh) | 2017-11-01 |
US10535566B2 (en) | 2020-01-14 |
CN107452614A (zh) | 2017-12-08 |
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