TW201919105A - 微元件的封裝方法 - Google Patents

微元件的封裝方法 Download PDF

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Publication number
TW201919105A
TW201919105A TW107137383A TW107137383A TW201919105A TW 201919105 A TW201919105 A TW 201919105A TW 107137383 A TW107137383 A TW 107137383A TW 107137383 A TW107137383 A TW 107137383A TW 201919105 A TW201919105 A TW 201919105A
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Taiwan
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micro
packaging
material layer
semi
cured
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TW107137383A
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English (en)
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TWI679681B (zh
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鐘志白
李佳恩
鄭錦堅
楊力勳
徐宸科
康俊勇
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大陸商廈門市三安光電科技有限公司
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Publication of TWI679681B publication Critical patent/TWI679681B/zh

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Abstract

一種微元件的封裝方法包括：步驟(1)在基板上形成封裝材料層，並對封裝材料層進行半固化處理形成表面具有黏性的半固化封裝材料層；步驟(2)將包含多個微元件的陣列抓取於半固化封裝材料層的表面；步驟(3)將陣列與共晶金屬層對準接合；步驟(4)使陣列與共晶金屬層進行共晶處理，並保持半固化封裝材料層的半固化狀態；步驟(5)將半固化封裝材料層與封裝基板進行壓合，使半固化封裝材料層包覆微元件，並對半固化封裝材料層進行完全固化；以及步驟(6)去除基板。利用半固化封裝材料層實現微元件的抓取並利用低溫高真空壓合實現微元件的轉移及密封，工藝簡單流暢，可實現微元件的無空隙封裝，提高封裝品質並有效降低封裝成本。

Description

微元件的封裝方法
本發明是有關於一種半導體製造領域，特別是指一種微微元件的封裝方法。
微元件技術是指在基板上形成包含高密度集成的微小尺寸的元件的陣列。目前，微發光二極體(Micro LED)技術逐漸成為研究熱門，且工業界期待有高品質的微元件產品進入市場。高品質微發光二極體產品會對市場上已有的諸如液晶顯示(LCD)或有機發光二極體(OLED)的傳統顯示產品產生深刻影響。
在製造微元件的過程中，首先在施體封裝基板上形成微元件，接著將微元件轉移到受體封裝基板上。該受體封裝基板例如是顯示螢幕。在製造微元件過程中的一個困難在於如何將微元件從該施體封裝基板上轉移到該受體封裝基板上。
傳統微元件的轉移方法為藉由封裝基板接合(Wafer Bonding)方式，將微元件自該施體封裝基板轉移至該受體封裝基板。該微元件的轉移方法的其中一種為直接轉移，也就是將包含多個微元件的陣列自該施體封裝基板直接接合至該受體封裝基板，之後通過剝離或者蝕刻方式，將該施體封裝基板移除。然而，該直接轉移方式常常需要犧牲掉多餘的外延層。該微元件的轉移方法的另一種為間接轉移。首先，利用轉移媒介提取包含多個微元件的陣列，接著該轉移媒介再將該陣列接合至該受體封裝基板，然後移除該轉移媒介。然而，該間接轉移方式的轉移媒介要求具有耐高溫的特性。
目前微元件的轉移的技術包括凡得瓦力、靜電吸附、相變化轉移和雷射束燒蝕四大技術。其中，凡得瓦力、靜電吸附及雷射束燒蝕方式是目前較多業者發展的方向。針對不同的應用，各種轉移方式各有優缺點。而微元件的封裝是在轉移後，需要整面進行封裝，主要就是利用常規的流體進行封裝及固化。
矽膠是微元件封裝常用的封裝材料。由於矽膠材料具有的抗大氣老化、抗紫外老化等優異性能，在高端的產品應用上已經廣泛使用矽膠進行封裝。矽膠在很短時間內也能承受瞬間高溫。微小元件的封裝由於尺寸小，當採單個進行封裝，封裝效率非常低，故常常採用整面封裝，然而，常規的整面流體覆蓋來進行封裝容易在微小元件間形成細小空隙，特別是元件的直角位置，從而影響可靠度。
基於以上所述，提供一種工藝流程簡單，可以有效減小封裝缺陷的微元件的封裝方法實屬必要。
因此，本發明的一目的，即在提供一種微元件的封裝方法，用於解決現有技術中封裝流程較為複雜，且容易產生封裝缺陷的問題。
於是，本發明微元件的封裝方法，包括步驟(1)至步驟(6) 。在該步驟(1)中，提供一基板，並在該基板上形成一層封裝材料層，且在第一溫度下對該封裝材料層進行半固化處理，形成半固化封裝材料層，其中，該第一溫度低於該封裝材料層的完全固化溫度，以保證該半固化封裝材料層具有黏性。在該步驟(2)中，提供包含多個間隔設置的微元件的陣列，基於該半固化封裝材料層的表面黏性，將該陣列的該等微元件黏著地設置在該半固化封裝材料層的表面。在該步驟(3)中，提供一個封裝單元，包括一個封裝基板及一層設置在該封裝基板的表面的共晶金屬層，該共晶金屬層包括多個間隔設置的共晶金屬，將該陣列與該共晶金屬層對準接合。在該步驟(4)中，在第二溫度下對該陣列與該共晶金屬層進行共晶處理，並保持該半固化封裝材料層的半固化狀態。在該步驟(5)中，將該半固化封裝材料層與該封裝單元的封裝基板進行壓合，使該半固化封裝材料層包覆該等微元件，並對該半固化封裝材料層進行完全固化，形成完全固化封裝材料層。以及在該步驟(6)中，去除該基板。
本發明的功效在於：本發明利用該半固化封裝材料層實現該等微元件的抓取，並將轉移媒介與封裝材料合而為一，從而使得工藝簡單並流暢，且利用低溫高真空壓合，實現該等微元件的轉移及密封，並在壓合過程中擠壓該半固化封裝材料層，從而可實現該等微元件的無空隙封裝，因而提高封裝品質，此外，相較於直接轉移的方式，本發明可充分使用外延層且步驟少，從而有效降低封裝成本。本發明利用該等共晶金屬在短時間內瞬間升溫共晶，或，採用共晶溫度低於該封裝材料層的完全固化溫度的該等共晶金屬，可保持該半固化封裝材料層的半固化狀態的穩定性。本發明可實現微元件的巨量轉移及整面完整無縫封裝，在半導體封裝領域具有廣泛的應用前景。
需要說明的是，本發明實施例中所提供的圖示僅以示意方式說明本發明的基本構想，遂圖示中僅顯示與本發明中有關的元件而非按照實際實施時的元件數目、形狀及尺寸繪製，且實際實施時各元件的型態、數量及比例可為一種隨意的改變，且元件佈局型態也可能更為複雜。
參閱圖1至圖8，本發明微元件的封裝方法的第一實施例包括步驟(1)至步驟(6)。
參閱圖1至圖3，在該步驟(1)S11中，提供一基板101，並在該基板101上形成一層封裝材料層102，且在第一溫度下對該封裝材料層102進行半固化處理，形成半固化封裝材料層108(參閱圖4)，其中，該第一溫度低於該封裝材料層102的完全固化溫度，以保證該半固化封裝材料層108具有黏性。
該基板101選用為與該封裝材料層102完全固化後可以較容易實現分離的基板，例如為不銹鋼基板。在該第一實施例中，該基板101為不銹鋼基板。
該封裝材料層102的厚度可以選自於15μm至100μm。在該第一實施例中，該封裝材料層102為矽膠層。該矽膠層的完全固化溫度通常為150℃至200℃，在此溫度下，該矽膠層需要約30分鐘至120分鐘才能實現完全固化。該矽膠層採用如旋轉塗佈工藝等形成於該基板101的表面，然後，在該第一溫度為60℃以上且小於150℃，如80℃、100℃或120℃，使該矽膠層進行熱處理。該熱處理的時間可以為10分鐘以上且小於30分鐘，使該矽膠層轉變成呈半固化狀態的矽膠層。該呈半固化狀態的矽膠層具有可塑性，且表面具有一定的黏性。
參閱圖1、圖4及圖5，在該步驟(2)S12中，提供包含一陣列11的懸浮式結構10，且該陣列11包括多個間隔設置的微元件103及多個對應該等微元件103設置的電極109，且基於該半固化封裝材料層108的表面黏性，將該陣列11的該等微元件103黏著地設置在該半固化封裝材料層108的表面。
在該第一實施例中，該等微元件103為發光二極體，且該等微元件103間以微間距間隔地設置。當然，其它的微元件103，如MOS元件、MEMS元件等也同樣可以採用該第一實施例的封裝方法進行封裝，且並不限於此處所列舉的示例。該等電極109例如金(Au)電極。在該第一實施例中，該等電極109為金電極。
在該第一實施例中，該懸浮式結構10能夠使該陣列11易被該半固化封裝材料層108的黏性表面抓取。具體地，該懸浮式結構10包含一層支撐層106、多個間隔地位於該支撐層106的表面的穩定柱107，以及該陣列11。該陣列11中的該等微元件103分別藉由該等穩定柱107支撐於該支撐層106上。需要說明的是，該等穩定柱107在保證該等微元件103可以被穩定地支撐的情況下，該等穩定柱107接觸該陣列11的面積被設計為盡可能小，且與該陣列11間的附著力低，以利於當該半固化封裝材料層108被施予一作用力時，該等穩定柱107能容易地與該陣列11脫離，從而使得該等微元件103容易被該半固化封裝材料層108抓取。
參閱圖1及圖6，在該步驟(3)S13中，提供一個封裝單元12。該封裝單元12包括一個封裝基板104，及一層設置在該封裝基板104的表面且位置對應該陣列11的共晶金屬層121。該共晶金屬層121包括多個對應該等微元件103的共晶金屬105。將該陣列11的該等電極109分別與該共晶金屬層121的該等共晶金屬105對準接合。該陣列11與該共晶金屬層121的厚度總和小於該封裝材料層102的厚度。
然後，在該步驟(4)S14中，在第二溫度下對該陣列11的該等電極109與該共晶金屬層121的該等共晶金屬105進行共晶處理，並保持該半固化封裝材料層108的半固化狀態。
作為示例，該共晶金屬層121的該等共晶金屬105包含銀錫銅(AgSnCu)合金及金錫(AuSn)合金所組成的群組中的一種。該第二溫度為不大於350℃，例如150℃至350℃。在該第一實施例中，該等共晶金屬105選用銀錫銅合金。
在較短的時間內，將該等共晶金屬105加熱至共晶溫度，通常為150℃至350℃，使該陣列11的該等電極109與該等共晶金屬105實現共晶互溶，整個處理時間為不大於1分鐘，且該半固化封裝材料層108在不大於350℃的溫度下，受熱時間不大於1分鐘的條件下，仍然會保持半固化狀態，以利於後續壓合工藝的進行。
參閱圖1及圖7，在該步驟(5)S15中，將該半固化封裝材料層108與該封裝單元12的封裝基板104進行壓合，使該半固化封裝材料層108包覆該等微元件103，並對該半固化封裝材料層108進行完全固化，形成完全固化封裝材料層13(參閱圖8)。
作為示例，採用真空壓合的方式，將該半固化封裝材料層108與該封裝基板104進行壓合，以保證該等微元件103的表面被該半固化封裝材料層108完全包覆，並使得該半固化封裝材料層108完全充滿該等微元件103之間的空隙。
作為示例，對該半固化封裝材料層108進行完全固化的固化溫度為150℃至200℃。
參閱圖1及圖8，最後，在該步驟(6)S16中，去除該基板101。
作為示例，直接將該基板101從該完全固化封裝材料層13上掀離。
在該第一實施例中，利用該半固化封裝材料層108實現該等微元件103的抓取，並利用低溫高真空壓合，實現該等微元件103的轉移及密封，工藝簡單流暢，可實現該等微元件103的無空隙封裝，提高封裝品質並有效降低封裝成本，並且，利用該等共晶金屬105在短時間內瞬間升溫共晶，可保持該半固化封裝材料層108的半固化狀態的穩定性。
參閱圖9至圖16，本發明微元件的封裝方法的第二實施例包括步驟(1)至步驟(6)。
參閱圖9至圖10，在該步驟(1)中，提供一基板201，且在該基板201上形成一個犧牲單元212，而該犧牲單元212包括依次在該基板201上形成一層剝離層208以及一層保護層209，然後，於該保護層209上形成一層封裝材料層202，並在第一溫度下對該封裝材料層202進行半固化處理，形成半固化封裝材料層210(參閱圖11)，其中，該第一溫度低於該封裝材料層202的完全固化溫度，以保證該半固化封裝材料層210具有黏性。該基板201包含藍寶石基板。該剝離層208包含鎵氮(GaN)層。該保護層209包含氧化銦錫(ITO)層。
作為示例，該基板201選用為藍寶石基板、該剝離層208選用為鎵氮層，而該保護層209選用為氧化銦錫層。該鎵氮層及該氧化銦錫層可以採用如化學氣相沉積工藝、濺射工藝等依次形成於該藍寶石基板的表面。
該封裝材料層202的厚度可以選自於15μm至100μm。在該第二實施例中，該封裝材料層202為矽膠層。該矽膠層的完全固化溫度通常為150℃至200℃，在此溫度下，該矽膠層需要約30分鐘至120分鐘才能實現完全固化。該矽膠層採用如旋轉塗佈工藝等形成於該基板201的表面，然後，在該第一溫度為60℃以上且小於150℃，如80℃、100℃或120℃，使該矽膠層進行熱處理。該熱處理的時間可以為10分鐘以上且小於30分鐘，使該矽膠層轉變成呈半固化狀態的矽膠層。該呈半固化狀態的矽膠層具有可塑性，且表面具有一定的黏性。
參閱圖11至圖12，在該步驟(2)中，提供包含一陣列21的懸浮式結構20，且該陣列21包括多個間隔設置的微元件203及多個對應該等微元件203設置的電極211，且基於該半固化封裝材料層210的表面黏性，將該陣列21的該等微元件203黏著地設置在該半固化封裝材料層210的表面。該等電極211例如金(Au)電極。在該第二實施例中，該等電極211為金電極。
在該第二實施例中，該等微元件203為發光二極體，且該等微元件203間以微間距間隔地設置。當然，其它的微元件203，如MOS元件、MEMS元件等也同樣可以採用該第二實施例的封裝方法進行封裝，且並不限於此處所列舉的示例。
在該第二實施例中，該懸浮式結構20能夠使該陣列21易被該半固化封裝材料層210的黏性表面抓取。具體地，該懸浮式結構20包括一層支撐層206、多個間隔地位於該支撐層206的表面的穩定柱207，以及該陣列21。該陣列21中的該等微元件203分別藉由該等穩定柱207支撐於該支撐層206上。需要說明的是，該等穩定柱207在保證該等微元件203可以被穩定地支撐的情況下，該等穩定柱207接觸該陣列21的面積被設計為盡可能小，且與該陣列21間的附著力低，以利於當該半固化封裝材料層210被施予一作用力時，該等穩定柱207能容易地與該陣列21脫離，從而使得該等微元件203容易被該半固化封裝材料層210抓取。
參閱圖13，在該步驟(3)中，提供一個封裝單元22。該封裝單元22包括一個封裝基板204，及一層設置在該封裝基板204的表面且位置對應該陣列21的共晶金屬層221。該共晶金屬層221包括多個對應該等微元件203的共晶金屬205。將該陣列21的該等電極211分別與該共晶金屬層221的該等共晶金屬205對準接合。該陣列21與該共晶金屬層221的厚度總和小於該封裝材料層202的厚度。
然後，在該步驟(4)S14中，在第二溫度下對該陣列21的該等電極211與該共晶金屬層221的該等共晶金屬205進行共晶處理，並保持該半固化封裝材料層210的半固化狀態。
作為示例，該共晶金屬層221的該等共晶金屬205包含銦(In)及鉍錫(BiSn)合金所組成的群組中的一種。該第二溫度為不大於該封裝材料層202的完全固化溫度，例如，該銦合金或該鉍錫合金與該等電極211的共晶溫度為不大於180℃，且可以在較短的時間內實現共晶互溶，例如1分鐘，因此，在該等共晶金屬205與該等電極211實現共晶時，該半固化封裝材料層210可以依然保持半固化狀態，以利於後續壓合工藝的進行。
參閱圖14，在該步驟(5)中，將該半固化封裝材料層210與該封裝單元22的封裝基板204進行壓合，使該半固化封裝材料層210包覆該等微元件203，並對該半固化封裝材料層210進行完全固化，形成完全固化封裝材料層23(參閱圖15)。
作為示例，採用真空壓合的方式，將該半固化封裝材料層210與該封裝基板204進行壓合，以保證該等微元件203的表面被該半固化封裝材料層210完全包覆，並使得該半固化封裝材料層210完全充滿該等微元件203之間的空隙。
作為示例，對該半固化封裝材料層210進行完全固化的固化溫度為150℃至200℃。
參閱圖15及圖16，最後，在該步驟(6)中，去除該基板201、該剝離層208，及該保護層209。
作為示例，基於該剝離層208，採用鐳射剝離的方式去除該基板201，該保護層209可以用來隔離該剝離層208及該完全固化封裝材料層23，以在鐳射剝離該剝離層208時對該完全固化封裝材料層23進行保護，然後採用濕式蝕刻的方式去除該保護層209及其它殘留物質。因該保護層209可為金屬氧化物層，在濕式刻蝕時採用的是酸性蝕刻液或鹼性蝕刻液，從而可以保證該完全固化封裝材料層23的完整性。
在該第二實施例中，利用該半固化封裝材料層210實現該等微元件203的抓取，並利用低溫高真空壓合實現該等微元件203的轉移及密封，工藝簡單流暢，可實現該等微元件203的無空隙封裝，提高封裝品質並有效降低封裝成本，並且，利用共晶溫度低於該封裝材料層202的完全固化溫度的共晶金屬205，可保持該半固化封裝材料層210的半固化狀態的穩定性。該第二實施例中利用無機材料作為犧牲單元212來實現該半固化封裝材料層210的壓合封裝，之後利用濕式刻蝕法去除該犧牲單元212，可完全保留完全固化封裝材料層23的完整性。
綜上所述，本發明微元件的封裝方法具有以下有益效果：本發明利用該半固化封裝材料層108,210實現該等微元件103,203的抓取，並利用低溫高真空壓合實現該等微元件103,203的轉移及密封，工藝簡單流暢，可實現該等微元件103,203的無空隙封裝，提高封裝品質並有效降低封裝成本。本發明利用該等共晶金屬105,205在短時間內瞬間升溫共晶，或，採用共晶溫度低於該封裝材料層102,202的完全固化溫度的該等共晶金屬105,205，可保持該半固化封裝材料層108,210的半固化狀態的穩定性。本發明利用無機材料作為犧牲單元212來實現該半固化封裝材料層210的壓合封裝，之後利用濕式刻蝕法去除該犧牲單元212，可完全保留完全固化封裝材料層23的完整性。本發明可實現微元件的巨量轉移及整面完整無縫封裝，在半導體封裝領域具有廣泛的應用前景。所以，本發明有效克服了現有技術中的種種缺點而具高度產業利用價值。
惟以上所述者，僅為本發明的實施例而已，當不能以此限定本發明實施的範圍，凡是依本發明申請專利範圍及專利說明書內容所作的簡單的等效變化與修飾，皆仍屬本發明專利涵蓋的範圍內。
S11‧‧‧步驟(1)
101‧‧‧基板
102‧‧‧封裝材料層
108‧‧‧半固化封裝材料層
201‧‧‧基板
212‧‧‧犧牲單元
208‧‧‧剝離層
209‧‧‧保護層
202‧‧‧封裝材料層
210‧‧‧半固化封裝材料層
S12‧‧‧步驟(2)
10‧‧‧懸浮式結構
11‧‧‧陣列
103‧‧‧微元件
109‧‧‧電極
106‧‧‧支撐層
107‧‧‧穩定柱
20‧‧‧懸浮式結構
21‧‧‧陣列
203‧‧‧微元件
211‧‧‧電極
206‧‧‧支撐層
207‧‧‧穩定柱
S13‧‧‧步驟(3)
12‧‧‧封裝單元
104‧‧‧封裝基板
121‧‧‧共晶金屬層
105‧‧‧共晶金屬
22‧‧‧封裝單元
204‧‧‧封裝基板
221‧‧‧共晶金屬層
205‧‧‧共晶金屬
S14‧‧‧步驟(4)
S15‧‧‧步驟(5)
13‧‧‧完全固化封裝材料層
23‧‧‧完全固化封裝材料層
S16‧‧‧步驟(6)
本發明的其他的特徵及功效，將於參照圖式的實施方式中清楚地呈現，其中： 圖1是本發明微元件的封裝方法的步驟流程示意圖； 圖2至圖8是本發明微元件的封裝方法的第一實施例的各步驟所呈現的結構示意圖；及 圖9至圖16是本發明微元件的封裝方法的第二實施例的各步驟所呈現的結構示意圖。

Claims (13)

  1. 一種微元件的封裝方法，包含： 步驟(1)，提供一基板，並在該基板上形成一層封裝材料層，且在第一溫度下對該封裝材料層進行半固化處理，形成半固化封裝材料層，其中，該第一溫度低於該封裝材料層的完全固化溫度，以保證該半固化封裝材料層具有黏性； 步驟(2)，提供包含多個間隔設置的微元件的陣列，基於該半固化封裝材料層的表面黏性，將該陣列的該等微元件黏著地設置在該半固化封裝材料層的表面； 步驟(3)，提供一個封裝單元，包括一個封裝基板，及一層設置在該封裝基板的表面的共晶金屬層，該共晶金屬層包括多個間隔設置的共晶金屬，將該陣列與該共晶金屬層對準接合； 步驟(4)，在第二溫度下對該陣列與該共晶金屬層進行共晶處理，並保持該半固化封裝材料層的半固化狀態； 步驟(5)，將該半固化封裝材料層與該封裝單元的封裝基板進行壓合，使該半固化封裝材料層包覆該等微元件，並對該半固化封裝材料層進行完全固化，形成完全固化封裝材料層；以及 步驟(6)，去除該基板。
  2. 如請求項1所述的微元件的封裝方法，其中，該封裝材料層包含矽膠，該第一溫度為60℃以上且小於150℃，該完全固化溫度為150℃至200℃。
  3. 如請求項1所述的微元件的封裝方法，其中，該等共晶金屬包含銀錫銅合金及金錫合金所組成的群組中的一種，該第二溫度為不大於350℃。
  4. 如請求項3所述的微元件的封裝方法，其中，該陣列與該共晶金屬層的共晶處理時間為不大於1分鐘，且該半固化封裝材料層在不大於350℃的溫度下且受熱時間不大於1分鐘的條件下保持半固化狀態。
  5. 如請求項1所述的微元件的封裝方法，其中，該等共晶金屬包含銦及鉍錫合金所組成的群組中的一種，該第二溫度為不大於該封裝材料層的完全固化溫度。
  6. 如請求項1所述的微元件的封裝方法，其中，該封裝材料層的厚度大於該陣列與該共晶金屬層的厚度總和。
  7. 如請求項1所述的微元件的封裝方法，其中，在該步驟(2)中，提供一個包含該陣列的懸浮式結構，以使該陣列易被該半固化封裝材料層的黏性表面抓取。
  8. 如請求項7所述的微元件的封裝方法，其中，該懸浮式結構還包含一層支撐層及多個間隔地位於該支撐層表面的穩定柱；該陣列中的該等微元件藉由對應的穩定柱支撐在該支撐層上。
  9. 如請求項1所述的微元件的封裝方法，其中，在該步驟(5)中，採用真空壓合的方式，將該半固化封裝材料層與該封裝基板進行壓合，以保證該等微元件的表面被該半固化封裝材料層完全包覆，並使得該半固化封裝材料層完全充滿該等微元件之間的空隙。
  10. 如請求項1所述的微元件的封裝方法，其中，該基板為不銹鋼基板，在該步驟(6)中，直接將該基板從該完全固化封裝材料層上掀離。
  11. 如請求項1所述的微元件的封裝方法，其中，該步驟(1)還包括在提供該基板後於該基板上形成一個犧牲單元，且該犧牲單元包括依次在該基板上形成一層剝離層以及一層保護層的步驟，然後，於該保護層上形成一層封裝材料層；在該步驟(6)中，基於該剝離層，採用鐳射剝離的方式去除該基板，然後採用濕式蝕刻的方式去除該保護層。
  12. 如請求項11所述的微元件的封裝方法，其中，該基板包含藍寶石基板，該剝離層包含鎵氮層，該保護層包含氧化銦錫層。
  13. 如請求項1所述的微元件的封裝方法，其中，該等微元件為微間距發光二極體。
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CN108039415B (zh) * 2017-11-02 2019-06-07 厦门市三安光电科技有限公司 微元件的封装方法
CN108682644B (zh) * 2018-06-15 2024-06-21 佛山宝芯智能科技有限公司 一种半导体无人工全自动流水线作业生产方法和系统
WO2020073306A1 (en) * 2018-10-12 2020-04-16 Boe Technology Group Co., Ltd. Micro light emitting diode apparatus and fabricating method thereof
US11018089B2 (en) * 2019-01-08 2021-05-25 Innolux Corporation Display devices and methods for manufacturing the same
CN109733493B (zh) * 2019-02-19 2021-09-10 上海交通大学 一种软体爬行吸附机器人
CN110707197A (zh) * 2019-09-11 2020-01-17 深圳市华星光电半导体显示技术有限公司 Led基板及led显示面板的制作方法
TWI720785B (zh) * 2020-01-15 2021-03-01 東貝光電科技股份有限公司 微型led發光裝置及其製造方法
TWI761895B (zh) 2020-07-24 2022-04-21 錼創顯示科技股份有限公司 微型電子元件轉移設備以及微型電子元件轉移方法
TWI757037B (zh) * 2021-01-06 2022-03-01 揚朋科技股份有限公司 顯示面板的修補方法
JP7368749B2 (ja) * 2021-07-26 2023-10-25 日亜化学工業株式会社 発光装置の製造方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002151551A (ja) 2000-11-10 2002-05-24 Hitachi Ltd フリップチップ実装構造、その実装構造を有する半導体装置及び実装方法
JP3665579B2 (ja) * 2001-02-26 2005-06-29 ソニーケミカル株式会社 電気装置製造方法
JP2003060241A (ja) 2001-08-10 2003-02-28 Sony Corp 回路素子の配列方法、及び表示装置の製造方法
JP2003347524A (ja) * 2002-05-28 2003-12-05 Sony Corp 素子の転写方法、素子の配列方法及び画像表示装置の製造方法
JP2007142232A (ja) * 2005-11-21 2007-06-07 Henkel Corp バンプ付電子部品の実装方法
JP4840371B2 (ja) * 2008-01-28 2011-12-21 ソニー株式会社 素子転写方法
JP2011517850A (ja) * 2008-03-21 2011-06-16 ライズ・テクノロジー・エッセ・アール・エル 多孔質シリコンを多孔質金属またはセラミックスに変換することによってマイクロ構造を作製するための方法
TWI399140B (zh) * 2009-06-12 2013-06-11 Unimicron Technology Corp 內埋式封裝結構的製作方法
US20110198762A1 (en) * 2010-02-16 2011-08-18 Deca Technologies Inc. Panelized packaging with transferred dielectric
TW201130104A (en) * 2010-02-22 2011-09-01 Chipmos Technologies Inc Semiconductor structure
JP5577859B2 (ja) * 2010-06-04 2014-08-27 株式会社デンソー 電子装置の製造方法
JP2012109396A (ja) * 2010-11-17 2012-06-07 Renesas Electronics Corp 半導体装置の製造方法
JP5892780B2 (ja) * 2011-12-19 2016-03-23 日東電工株式会社 半導体装置の製造方法
US8754435B1 (en) * 2013-02-19 2014-06-17 Cooledge Lighting Inc. Engineered-phosphor LED package and related methods
US9076882B2 (en) * 2013-06-03 2015-07-07 Intel Corporation Methods for high precision microelectronic die integration
US9035279B2 (en) * 2013-07-08 2015-05-19 LuxVue Technology Corporation Micro device with stabilization post
TWI597786B (zh) * 2013-12-19 2017-09-01 矽品精密工業股份有限公司 半導體封裝結構及其製法
JP2015216229A (ja) * 2014-05-09 2015-12-03 日東電工株式会社 半導体装置の製造方法及び熱硬化性樹脂シート
KR102334815B1 (ko) * 2014-02-19 2021-12-02 가부시키가이샤 한도오따이 에네루기 켄큐쇼 발광 장치 및 박리 방법
JP2015220400A (ja) 2014-05-20 2015-12-07 日東電工株式会社 電子デバイスパッケージの製造方法及び電子デバイスの封止方法
JP6165686B2 (ja) * 2014-07-31 2017-07-19 信越化学工業株式会社 支持基材付封止材、封止後半導体素子搭載基板、封止後半導体素子形成ウエハ、半導体装置、及び半導体装置の製造方法
JP5962834B1 (ja) 2015-06-04 2016-08-03 住友ベークライト株式会社 樹脂組成物、接着フィルムおよび回路部材の接続方法
CN105895539B (zh) * 2016-06-08 2018-08-10 华进半导体封装先导技术研发中心有限公司 芯片倒装封装中间结构和倒装封装结构及倒装封装方法
CN108039415B (zh) * 2017-11-02 2019-06-07 厦门市三安光电科技有限公司 微元件的封装方法

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