CN108039415A - 微元件的封装方法 - Google Patents
微元件的封装方法 Download PDFInfo
- Publication number
- CN108039415A CN108039415A CN201711065564.3A CN201711065564A CN108039415A CN 108039415 A CN108039415 A CN 108039415A CN 201711065564 A CN201711065564 A CN 201711065564A CN 108039415 A CN108039415 A CN 108039415A
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- Prior art keywords
- microcomponent
- encapsulating material
- material layer
- packing
- array
- Prior art date
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- 239000002184 metal Substances 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 35
- 239000000741 silica gel Substances 0.000 claims abstract description 35
- 229910002027 silica gel Inorganic materials 0.000 claims abstract description 35
- 239000007787 solid Substances 0.000 claims abstract description 24
- 238000002360 preparation method Methods 0.000 claims abstract description 22
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- 238000012545 processing Methods 0.000 claims abstract description 15
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- 229910045601 alloy Inorganic materials 0.000 claims description 10
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- 239000010935 stainless steel Substances 0.000 claims description 6
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- 238000001039 wet etching Methods 0.000 claims description 6
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- 238000005253 cladding Methods 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000012546 transfer Methods 0.000 abstract description 16
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Classifications
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Abstract
本发明提供一种微元件的封装方法,包括:1)于基底上形成封装材料层,并对封装材料层进行半固化处理;2)基于封装材料层的表面粘性,将微元件的阵列抓取于封装材料层表面;3)将微元件的阵列与封装基板上的共晶金属对准接合;4)对微元件的阵列与共晶金属下进行共晶处理,并保持封装材料的半固化状态;5)将半固化的封装材料层与封装基板进行压合,使封装材料层包覆微元件,并对封装材料进行完全固化;以及6)去除基底。本发明利用半固化的硅胶实现微元件的抓取,并利用低温高真空压合实现微元件的转移及密封,工艺简单流畅,可实现微元件的无空隙封装,提高封装质量并有效降低封装成本。
Description
技术领域
本发明属于半导体制造领域,特别是涉及一种微元件的封装方法。
背景技术
微元件技术是指在衬底上以高密度集成的微小尺寸的元件阵列。目前,微间距发光二极管(Micro LED)技术逐渐成为研究热门,工业界期待有高品质的微元件产品进入市场。高品质微间距发光二极管产品会对市场上已有的诸如LCD/OLED的传统显示产品产生深刻影响。
在制造微元件的过程中,首先在施体封装基板上形成微元件,接着将微元件转移到接收封装基板上。接收封装基板例如是显示屏。在制造微元件过程中的一个困难在于:如何将微元件从施体封装基板上转移到接收封装基板上。
传统转移微元件的方法为借由封装基板接合(Wafer Bonding)将微元件自转移封装基板转移至接收封装基板。转移方法的其中一种实施方法为直接转移,也就是直接将微元件阵列自转移封装基板接合至接收封装基板,之后通过剥离或者蚀刻将转移封装基板移除,制作转移常常需要牺牲掉多余的外延层。另一种实施方法为间接转移。-,首先,转移媒质提取微元件阵列,接着转移媒质再将微元件阵列接合至接收封装基板,然后移除转移媒质。转移媒质要求耐高温。
目前微元件的转移的技术包括范德华力、静电吸附、相变化转移和雷射激光烧蚀四大技术。其中范德华力、静电吸附及雷射激光烧蚀方式是目前较多厂商发展的方向。针对不同的应用,各种转移方式各有优缺点。而微元件的封装是在转移后,需要整面进行封装,主要就是常规的流体封装固化。
硅胶是微元件封装常用的封装材料。由于硅胶材料具有的抗大气老化、紫外老化等优异性能,在高端的产品应用上已经广泛使用硅胶进行封装;硅胶在很短时间内也能承受瞬间高温。微小元件的封装由于其单元小,不能采用单一的封装体进行组合,常常采用整面封装,常规的整面流体覆盖封装容易在微小元件间形成细小空隙,特别是元件的直角位置,从而影响可靠度。
基于以上所述,提供一种工艺流程简单,可以有效减小封装缺陷的微元件的封装方法实属必要。
发明内容
鉴于以上所述现有技术的缺点,本发明的目的在于提供一种微元件的封装方法,用于解决现有技术中封装流程较为复杂,且容易产生封装缺陷的问题。
为实现上述目的及其他相关目的,本发明提供一种微元件的封装方法,所述封装方法包括步骤:1)提供一基底,于所述基底上形成封装材料层,并对所述封装材料层在第一温度下进行半固化处理,其中,所述第一温度低于所述封装材料层的完全固化温度,以保证所述封装材料层具有粘性;2)提供微元件的阵列,基于所述封装材料层的表面粘性,将所述微元件的阵列抓取于所述封装材料层表面;3)提供一封装基板,所述封装基板表面具有与所述微元件的阵列对应的共晶金属,将所述微元件的阵列与所述共晶金属对准接合;4)对所述微元件的阵列与所述共晶金属在第二温度下进行共晶处理,并保持所述封装材料的半固化状态;5)将半固化的所述封装材料层与所述封装基板进行压合,使所述封装材料层包覆所述微元件,并对所述封装材料进行完全固化;以及6)去除所述基底。
优选地,所述封装材料层包含硅胶,所述半固化处理采用的所述第一温度选自于60℃~150℃,所述完全固化温度为150℃~200℃。
优选地,所述共晶金属包含AgSnCu合金及AuSn合金所组成的群组中的一种,所述第二温度为不高于350℃。
进一步地,所述微元件的阵列与所述共晶金属的共晶处理时间为不大于1min,且所述封装材料在不高于350℃的温度下,受热时间不大于1min的条件下保持半固化状态。
优选地,所述共晶金属包含In及BiSn合金所组成的群组中的一种,所述第二温度为不高于所述封装材料的完全固化温度。
优选地,所述封装材料层的厚度大于所述微元件与所述共晶金属的总厚度。
优选地,步骤2)中,所述微元件的阵列采用悬浮式结构,以使其易被所述封装材料层的粘性表面抓取。
进一步地,所述悬浮式结构包括:一支撑层;多个稳定柱,位于所述支撑层表面;以及微元件的阵列,该阵列中的每个微元件藉由若干个所述稳定柱支撑。
优选地,步骤5)中,采用真空压合的方式将半固化的所述封装材料层与所述封装基板进行压合,以保证所述微元件的表面被所述封装材料层完全包覆,并使得所述封装材料层完全充满所述微元件之间的空隙。
优选地,所述基底为不锈钢基底,步骤6)直接将所述不锈钢基底从所述封装材料上掀离。
优选地,步骤1)提供一基底后,还包括于所述基底上依次形成剥离层以及保护层的步骤,然后于所述保护层上形成封装材料层;步骤6)先基于所述剥离层,采用激光剥离的方式去除所述基底,然后采用湿法蚀刻的方式去除所述保护层。
优选地,所述基底包含蓝宝石基底,所述剥离层包含GaN层,所述保护层包含ITO层。
优选地,所述微元件的阵列包含微间距发光二极管阵列。
如上所述,本发明的微元件的封装方法,具有以下有益效果:
本发明利用半固化的硅胶实现微元件的抓取,并利用低温高真空压合实现微元件的转移及密封,工艺简单流畅,可实现微元件的无空隙封装,提高封装质量并有效降低封装成本。
本发明利用共晶金属在短时间内瞬间升温共晶,或采用共晶温度低于硅胶的完全固化温度的共晶金属,可保持硅胶半固化状态的稳定性。
本发明利用无机牺牲层实现硅胶的压合封装,之后利用湿法刻蚀去除无机牺牲层,可完全保留硅胶的完整性。
本发明可实现微元件的巨量转移及整面完整无缝封装,在半导体封装领域具有广泛的应用前景。
附图说明
图1显示为本发明的微元件的封装方法的步骤流程示意图。
图2~图8显示为本发明实施例1的微元件的封装方法各步骤所呈现的结构示意图。
图9~图16显示为本发明实施例2的微元件的封装方法各步骤所呈现的结构示意图。
元件标号说明
101、201 基底
102、202 封装材料层
103、203 微元件
104、204 封装基板
105、205 共晶金属
106、206 支撑层
107、207 稳定柱
208 剥离层
209 保护层
S11~S16 步骤
具体实施方式
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1~图16。需要说明的是,本实施例中所提供的图示仅以示意方式说明本发明的基本构想,遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制,其实际实施时各组件的型态、数量及比例可为一种随意的改变,且其组件布局型态也可能更为复杂。
实施例1
如图1~图8所示,本实施例提供一种微元件103的封装方法,所述封装方法包括步骤:
如图1~图3所示,首先进行步骤1)S11,提供一基底101,于所述基底101上形成封装材料层102,并对所述封装材料层102在第一温度下进行半固化处理,其中,所述第一温度低于所述封装材料层102的完全固化温度,以保证所述封装材料层102具有粘性。
所述基底101选用为与完全固化后的封装材料可以较容易实现分离的材料制成,例如为不锈钢基底101。
所述封装材料层102的厚度大于所述微元件103与所述共晶金属105的总厚度,例如,所述封装材料层102的厚度可以选自于15~100μm。
在本实施例中,所述封装材料层102为硅胶,所述硅胶的完全固化温度通常为150℃~200℃,在此温度下,所述硅胶需要约30min~120min才能实现完全固化。
所述硅胶采用如旋涂工艺等形成于所述基底101表面,然后在60℃~150℃的第一温度,如80℃、100℃或120℃等温度下进行热处理,热处理时间可以为10min~30min,使所述硅胶呈半固化状态,半固化状态下的硅胶具有可塑性,且其表面具有一定的粘性。
如图1及图4~图5所示,然后进行步骤2)S12,提供微元件103的阵列,基于所述封装材料层102的表面粘性,将所述微元件103的阵列抓取于所述封装材料层102表面。
在本实施例中,所述微元件103的阵列为微间距发光二极管阵列。当然,其它的微元件103,如MOS器件、MEMS器件等也同样可以采用本实施例的封装方法进行封装,且并不限于此处所列举的示例。
在本实施例中,所述微元件103的阵列采用悬浮式结构,以使其易被所述封装材料层102的粘性表面抓取。具体地,所述悬浮式结构包括:一支撑层106;多个稳定柱107,位于所述支撑层106表面;以及微元件103的阵列,该阵列中的每个微元件103藉由若干个所述稳定柱107支撑。需要说明的是,所述稳定柱107在保证所述微元件103可以被稳定支撑的情况下,所述稳定柱107的面积设计为尽可能小,以利于微元件103容易被所述封装材料抓取。
如图1及图6所示,接着进行步骤3)S13,提供一封装基板104,所述封装基板104表面具有与所述微元件103的阵列对应的共晶金属105,将所述微元件103的阵列上的电极与所述共晶金属105对准接合。
如图1所示,然后进行步骤4)S14,对所述微元件103的阵列与所述共晶金属105在第二温度下进行共晶处理,并保持所述封装材料的半固化状态。
作为示例,所述共晶金属105包含AgSnCu合金及AuSn合金所组成的群组中的一种,所述第二温度为不高于350℃。在本实施例中,所述共晶金属105选用为AgSnCu合金。
在较短的时间内将所述共晶金属105加热至共晶温度,通常为150℃~350℃,使所述微元件103的阵列上的电极,如Au电极,与所述共晶金属105实现共晶互溶,整个处理时间为不大于1min,所述封装材料在不高于350℃的温度下,如150℃~350℃,受热时间不大于1min的条件下,会仍然保持半固化状态,以利于后续压合工艺的进行。
如图1及图7所示,然后进行步骤5)S15,将半固化的所述封装材料层102与所述封装基板104进行压合,使所述封装材料层102包覆所述微元件103,并对所述封装材料进行完全固化。
作为示例,采用真空压合的方式将半固化的所述封装材料层102与所述封装基板104进行压合,以保证所述微元件103的表面被所述封装材料层102完全包覆,并使得所述封装材料层102完全充满所述微元件103之间的空隙。
作为示例,对所述封装材料进行完全固化的固化温度为150℃~200℃。
如图1及图8所示,最后进行步骤6)S16,去除所述基底101。
作为示例,直接将所述不锈钢基底101从所述封装材料上掀离。
本实施例利用半固化的硅胶实现微元件103的抓取,并利用低温高真空压合实现微元件103的转移及密封,工艺简单流畅,可实现微元件103的无空隙封装,提高封装质量并有效降低封装成本,并且,本实施例利用共晶金属105在短时间内瞬间升温共晶,可保持硅胶半固化状态的稳定性。
实施例2
如图9~图16所示,本实施例提供一种微元件203的封装方法,所述封装方法包括步骤:
如图9~图10所示,首先进行步骤1),提供一基底201,所述基底201上依次形成剥离层208以及保护层209,然后于所述保护层209上形成封装材料层202,并对所述封装材料层202在第一温度下进行半固化处理,其中,所述第一温度低于所述封装材料层202的完全固化温度,以保证所述封装材料层202具有粘性。
作为示例所述基底201选用为蓝宝石基底201,所述剥离层208选用为GaN层,所述保护层209选用为ITO层。所述GaN层及ITO层可以采用如化学气相沉积工艺、溅射工艺等依次形成于所述蓝宝石基底201表面。
所述封装材料层202的厚度大于所述微元件203与所述共晶金属205的总厚度,例如,所述封装材料层202的厚度可以选自于15~100μm。
在本实施例中,所述封装材料层202为硅胶,所述硅胶的完全固化温度通常为150℃~200℃,在此温度下,所述硅胶需要约30min~120min才能实现完全固化。
所述硅胶采用如旋涂工艺等形成于所述基底201表面,然后在60℃~150℃的第一温度,如80℃、100℃或120℃等温度下进行热处理,热处理时间可以为10min~30min,使所述硅胶呈半固化状态,半固化状态下的硅胶具有可塑性,且其表面具有一定的粘性。
如图11~图12所示,然后进行步骤2),提供微元件203的阵列,基于所述封装材料层202的表面粘性,将所述微元件203的阵列抓取于所述封装材料层202表面。
在本实施例中,所述微元件203的阵列为微间距发光二极管阵列。当然,其它的微元件203,如MOS器件、MEMS器件等也同样可以采用本实施例的封装方法进行封装,且并不限于此处所列举的示例。
在本实施例中,所述微元件203的阵列采用悬浮式结构,以使其易被所述封装材料层202的粘性表面抓取。具体地,所述悬浮式结构包括:一支撑层206;多个稳定柱207,位于所述支撑层206表面;以及微元件203的阵列,该阵列中的每个微元件203藉由若干个所述稳定柱207支撑。需要说明的是,所述稳定柱207在保证所述微元件203可以被稳定支撑的情况下,所述稳定柱207的面积设计为尽可能小,以利于微元件203容易被所述封装材料抓取。
如图13所示,接着进行步骤3),提供一封装基板204,所述封装基板204表面具有与所述微元件203的阵列对应的共晶金属205,将所述微元件203的阵列与所述共晶金属205对准接合。
然后进行步骤4),对所述微元件203的阵列与所述共晶金属205在第二温度下进行共晶处理,并保持所述封装材料的半固化状态;
作为示例,所述共晶金属205包含In及BiSn合金所组成的群组中的一种,所述第二温度为不高于所述封装材料的完全固化温度,例如,所述In或BiSn合金与微元件203上的Au电极的共晶温度为不高于180℃,且可以在较短的时间内实现共晶互溶,如1min,因此,在所述共晶金属205与微元件203的Au电极实现共晶时,所述封装材料可以依然保持半固化状态,以利于后续压合工艺的进行。
如图14所示,然后进行步骤5),将半固化的所述封装材料层202与所述封装基板204进行压合,使所述封装材料层202包覆所述微元件203,并对所述封装材料进行完全固化。
作为示例,采用真空压合的方式将半固化的所述封装材料层202与所述封装基板204进行压合,以保证所述微元件203的表面被所述封装材料层202完全包覆,并使得所述封装材料层202完全充满所述微元件203之间的空隙。
作为示例,对所述封装材料进行完全固化的固化温度为150℃~200℃。
如图15~图16所示,最后进行步骤6),去除所述基底201以及位于所述基底201上的剥离层208以及保护层209。
作为示例,先基于所述剥离层208,采用激光剥离的方式去除所述基底201,所述保护层209可以用于隔离所述剥离层208及所述封装材料层202,以在激光剥离时对所述封装材料层202进行保护,然后采用湿法蚀刻的方式去除所述保护层209及其它残留物质,所述保护层209在湿法刻蚀时可以保证所述封装材料层202的完整性。
本实施例利用半固化的硅胶实现微元件203的抓取,并利用低温高真空压合实现微元件203的转移及密封,工艺简单流畅,可实现微元件203的无空隙封装,提高封装质量并有效降低封装成本。本实施例利用共晶温度低于硅胶的完全固化温度的共晶金属205,可保持硅胶半固化状态的稳定性。本实施例利用无机牺牲层实现硅胶的压合封装,之后利用湿法刻蚀去除无机牺牲层,可完全保留硅胶的完整性。
如上所述,本发明的微元件的封装方法,具有以下有益效果:
本发明利用半固化的硅胶实现微元件的抓取,并利用低温高真空压合实现微元件的转移及密封,工艺简单流畅,可实现微元件的无空隙封装,提高封装质量并有效降低封装成本。
本发明利用共晶金属在短时间内瞬间升温共晶,或采用共晶温度低于硅胶的完全固化温度的共晶金属,可保持硅胶半固化状态的稳定性。
本发明利用无机牺牲层实现硅胶的压合封装,之后利用湿法刻蚀去除无机牺牲层,可完全保留硅胶的完整性。
本发明可实现微元件的巨量转移及整面完整无缝封装,在半导体封装领域具有广泛的应用前景。
所以,本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。
Claims (13)
1.一种微元件的封装方法,其特征在于,所述封装方法包括步骤:
1)提供一基底,于所述基底上形成封装材料层,并对所述封装材料层在第一温度下进行半固化处理,其中,所述第一温度低于所述封装材料层的完全固化温度,以保证所述封装材料层具有粘性;
2)提供微元件的阵列,基于所述封装材料层的表面粘性,将所述微元件的阵列抓取于所述封装材料层表面;
3)提供一封装基板,所述封装基板表面具有与所述微元件的阵列对应的共晶金属,将所述微元件的阵列与所述共晶金属对准接合;
4)对所述微元件的阵列与所述共晶金属在第二温度下进行共晶处理,并保持所述封装材料的半固化状态;
5)将半固化的所述封装材料层与所述封装基板进行压合,使所述封装材料层包覆所述微元件,并对所述封装材料进行完全固化;以及
6)去除所述基底。
2.根据权利要求1所述的微元件的封装方法,其特征在于:所述封装材料层包含硅胶,所述半固化处理采用的所述第一温度选自于60℃~150℃,所述完全固化温度为150℃~200℃。
3.根据权利要求1所述的微元件的封装方法,其特征在于:所述共晶金属包含AgSnCu合金及AuSn合金所组成的群组中的一种,所述第二温度为不高于350℃。
4.根据权利要求3所述的微元件的封装方法,其特征在于:所述微元件的阵列与所述共晶金属的共晶处理时间为不大于1min,且所述封装材料在不高于350℃的温度下,受热时间不大于1min的条件下保持半固化状态。
5.根据权利要求1所述的微元件的封装方法,其特征在于:所述共晶金属包含In及BiSn合金所组成的群组中的一种,所述第二温度为不高于所述封装材料的完全固化温度。
6.根据权利要求1所述的微元件的封装方法,其特征在于:所述封装材料层的厚度大于所述微元件与所述共晶金属的总厚度。
7.根据权利要求1所述的微元件的封装方法,其特征在于:步骤2)中,所述微元件的阵列采用悬浮式结构,以使其易被所述封装材料层的粘性表面抓取。
8.根据权利要求7所述的微元件的封装方法,其特征在于:所述悬浮式结构包括:
支撑层;
多个稳定柱,位于所述支撑层表面;以及
微元件的阵列,该阵列中的每个微元件藉由若干个所述稳定柱支撑。
9.根据权利要求1所述的微元件的封装方法,其特征在于:步骤5)中,采用真空压合的方式将半固化的所述封装材料层与所述封装基板进行压合,以保证所述微元件的表面被所述封装材料层完全包覆,并使得所述封装材料层完全充满所述微元件之间的空隙。
10.根据权利要求1所述的微元件的封装方法,其特征在于:所述基底为不锈钢基底,步骤6)直接将所述不锈钢基底从所述封装材料上掀离。
11.根据权利要求1所述的微元件的封装方法,其特征在于:步骤1)提供一基底后,还包括于所述基底上依次形成剥离层以及保护层的步骤,然后于所述保护层上形成封装材料层;步骤6)先基于所述剥离层,采用激光剥离的方式去除所述基底,然后采用湿法蚀刻的方式去除所述保护层。
12.根据权利要求11所述的微元件的封装方法,其特征在于:所述基底包含蓝宝石基底,所述剥离层包含GaN层,所述保护层包含ITO层。
13.根据权利要求1所述的微元件的封装方法,其特征在于:所述微元件的阵列包含微间距发光二极管阵列。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2019085444A1 (zh) * | 2017-11-02 | 2019-05-09 | 厦门市三安光电科技有限公司 | 微元件的封装方法 |
CN109733493A (zh) * | 2019-02-19 | 2019-05-10 | 上海交通大学 | 一种软体爬行吸附机器人 |
CN111415955A (zh) * | 2019-01-08 | 2020-07-14 | 群创光电股份有限公司 | 显示装置及其制造方法 |
WO2021047008A1 (zh) * | 2019-09-11 | 2021-03-18 | 深圳市华星光电半导体显示技术有限公司 | Led基板及led显示面板的制作方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020073306A1 (en) * | 2018-10-12 | 2020-04-16 | Boe Technology Group Co., Ltd. | Micro light emitting diode apparatus and fabricating method thereof |
TWI720785B (zh) * | 2020-01-15 | 2021-03-01 | 東貝光電科技股份有限公司 | 微型led發光裝置及其製造方法 |
TWI761895B (zh) | 2020-07-24 | 2022-04-21 | 錼創顯示科技股份有限公司 | 微型電子元件轉移設備以及微型電子元件轉移方法 |
TWI757037B (zh) * | 2021-01-06 | 2022-03-01 | 揚朋科技股份有限公司 | 顯示面板的修補方法 |
JP7368749B2 (ja) * | 2021-07-26 | 2023-10-25 | 日亜化学工業株式会社 | 発光装置の製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102037560A (zh) * | 2008-03-21 | 2011-04-27 | Rise技术有限责任公司 | 通过将多孔硅转变成多孔金属或陶瓷来制作微结构的方法 |
US20110198762A1 (en) * | 2010-02-16 | 2011-08-18 | Deca Technologies Inc. | Panelized packaging with transferred dielectric |
JP2012109396A (ja) * | 2010-11-17 | 2012-06-07 | Renesas Electronics Corp | 半導体装置の製造方法 |
CN105895539A (zh) * | 2016-06-08 | 2016-08-24 | 华进半导体封装先导技术研发中心有限公司 | 芯片倒装封装中间结构和倒装封装结构及倒装封装方法 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002151551A (ja) | 2000-11-10 | 2002-05-24 | Hitachi Ltd | フリップチップ実装構造、その実装構造を有する半導体装置及び実装方法 |
JP3665579B2 (ja) * | 2001-02-26 | 2005-06-29 | ソニーケミカル株式会社 | 電気装置製造方法 |
JP2003060241A (ja) | 2001-08-10 | 2003-02-28 | Sony Corp | 回路素子の配列方法、及び表示装置の製造方法 |
JP2003347524A (ja) * | 2002-05-28 | 2003-12-05 | Sony Corp | 素子の転写方法、素子の配列方法及び画像表示装置の製造方法 |
JP2007142232A (ja) * | 2005-11-21 | 2007-06-07 | Henkel Corp | バンプ付電子部品の実装方法 |
JP4840371B2 (ja) * | 2008-01-28 | 2011-12-21 | ソニー株式会社 | 素子転写方法 |
TWI399140B (zh) * | 2009-06-12 | 2013-06-11 | Unimicron Technology Corp | 內埋式封裝結構的製作方法 |
TW201130104A (en) * | 2010-02-22 | 2011-09-01 | Chipmos Technologies Inc | Semiconductor structure |
JP5577859B2 (ja) * | 2010-06-04 | 2014-08-27 | 株式会社デンソー | 電子装置の製造方法 |
JP5892780B2 (ja) * | 2011-12-19 | 2016-03-23 | 日東電工株式会社 | 半導体装置の製造方法 |
US8754435B1 (en) * | 2013-02-19 | 2014-06-17 | Cooledge Lighting Inc. | Engineered-phosphor LED package and related methods |
US9076882B2 (en) * | 2013-06-03 | 2015-07-07 | Intel Corporation | Methods for high precision microelectronic die integration |
US9035279B2 (en) * | 2013-07-08 | 2015-05-19 | LuxVue Technology Corporation | Micro device with stabilization post |
TWI597786B (zh) * | 2013-12-19 | 2017-09-01 | 矽品精密工業股份有限公司 | 半導體封裝結構及其製法 |
JP2015216229A (ja) * | 2014-05-09 | 2015-12-03 | 日東電工株式会社 | 半導体装置の製造方法及び熱硬化性樹脂シート |
DE112015000866T5 (de) * | 2014-02-19 | 2016-11-17 | Semiconductor Energy Laboratory Co., Ltd. | Lichtemittierende Vorrichtung und Ablöseverfahren |
JP2015220400A (ja) | 2014-05-20 | 2015-12-07 | 日東電工株式会社 | 電子デバイスパッケージの製造方法及び電子デバイスの封止方法 |
JP6165686B2 (ja) * | 2014-07-31 | 2017-07-19 | 信越化学工業株式会社 | 支持基材付封止材、封止後半導体素子搭載基板、封止後半導体素子形成ウエハ、半導体装置、及び半導体装置の製造方法 |
JP5962834B1 (ja) | 2015-06-04 | 2016-08-03 | 住友ベークライト株式会社 | 樹脂組成物、接着フィルムおよび回路部材の接続方法 |
CN108039415B (zh) * | 2017-11-02 | 2019-06-07 | 厦门市三安光电科技有限公司 | 微元件的封装方法 |
-
2017
- 2017-11-02 CN CN201711065564.3A patent/CN108039415B/zh active Active
-
2018
- 2018-05-22 WO PCT/CN2018/087800 patent/WO2019085444A1/zh active Application Filing
- 2018-05-22 KR KR1020207014916A patent/KR102438404B1/ko active IP Right Grant
- 2018-05-22 JP JP2020524355A patent/JP7082264B2/ja active Active
- 2018-10-23 TW TW107137383A patent/TWI679681B/zh active
-
2020
- 2020-05-01 US US16/865,186 patent/US11101239B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102037560A (zh) * | 2008-03-21 | 2011-04-27 | Rise技术有限责任公司 | 通过将多孔硅转变成多孔金属或陶瓷来制作微结构的方法 |
US20110198762A1 (en) * | 2010-02-16 | 2011-08-18 | Deca Technologies Inc. | Panelized packaging with transferred dielectric |
JP2012109396A (ja) * | 2010-11-17 | 2012-06-07 | Renesas Electronics Corp | 半導体装置の製造方法 |
CN105895539A (zh) * | 2016-06-08 | 2016-08-24 | 华进半导体封装先导技术研发中心有限公司 | 芯片倒装封装中间结构和倒装封装结构及倒装封装方法 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2019085444A1 (zh) * | 2017-11-02 | 2019-05-09 | 厦门市三安光电科技有限公司 | 微元件的封装方法 |
US11101239B2 (en) | 2017-11-02 | 2021-08-24 | Xiamen Sanan Optoelectronics Technology Co., Ltd. | Process for packaging component |
CN111415955A (zh) * | 2019-01-08 | 2020-07-14 | 群创光电股份有限公司 | 显示装置及其制造方法 |
CN109733493A (zh) * | 2019-02-19 | 2019-05-10 | 上海交通大学 | 一种软体爬行吸附机器人 |
CN109733493B (zh) * | 2019-02-19 | 2021-09-10 | 上海交通大学 | 一种软体爬行吸附机器人 |
WO2021047008A1 (zh) * | 2019-09-11 | 2021-03-18 | 深圳市华星光电半导体显示技术有限公司 | Led基板及led显示面板的制作方法 |
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US11101239B2 (en) | 2021-08-24 |
JP7082264B2 (ja) | 2022-06-08 |
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