TW201917893A - 埋藏式電力軌 - Google Patents

埋藏式電力軌 Download PDF

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Publication number
TW201917893A
TW201917893A TW107121263A TW107121263A TW201917893A TW 201917893 A TW201917893 A TW 201917893A TW 107121263 A TW107121263 A TW 107121263A TW 107121263 A TW107121263 A TW 107121263A TW 201917893 A TW201917893 A TW 201917893A
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Taiwan
Prior art keywords
power rail
semiconductor device
isolation trench
dielectric cover
trench
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TW107121263A
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English (en)
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TWI734919B (zh
Inventor
傑佛瑞 史密斯
安東 Ｊ 德維利耶
坎達巴拉 泰伯利
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日商東京威力科創股份有限公司
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    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract

本發明之態樣提供用於製造半導體裝置的半導體裝置及方法。該半導體裝置包含形成於一隔離渠溝中的一電力軌。該電力軌係由一介電質蓋部所覆蓋，該介電質蓋部將該電力軌與在該介電質蓋部上的導電性圖案結構隔離。再者，一開口部係選擇性地形成於該介電質蓋部中、且係以導電性材料填充，俾選擇性地將導電性圖案結構與該電力軌連接。

Description

埋藏式電力軌
本發明描述大體上關於半導體裝置與製造程序的實施例。 [相關申請案的交互參照]
本發明主張2017年6月22日提交的案名為「Method to Self-align Buried Power Rails and Below-device Wiring for Random and Non-random Logic Applications and Designs」的美國臨時專利申請案第62/523,704號的權益，在此藉由參照全文引入。
本發明係關於製造半導體裝置(例如積體電路、及用於積體電路的電晶體及電晶體元件)的方法。在半導體裝置之製造中(特別係微觀尺度)，重複執行各種加工處理(例如薄膜形成之沉積、蝕刻遮罩之產生、圖案化、材料蝕刻與移除、以及摻雜處理)以在基板上形成期望的半導體裝置元件。從歷史上來看，透過微加工，已在一平面中產生電晶體，透過在上方形成的接線/金屬化，已使電晶體具有二維(2D)電路或2D加工的特性。在尺度上的努力已使2D電路中每單位面積的電晶體數目大幅增加，然而隨著尺度進入個位數奈米之半導體裝置加工節點，尺度上的努力正面臨更大的挑戰。
此發明係關於包含鰭式場效電晶體(FINFET)、奈米線、奈米片、或互補式堆疊奈米線及/或奈米片的隨機與非隨機邏輯兩者之裝置加工。在標準邏輯單元內，透過後段製程(BEOL)金屬層中的電力軌將裝置(例如，電晶體)的電源供應至源極/汲極接觸窗。電力軌通常在一般稱為東西向之方向上穿過鄰近的單元。由於電力軌需將電源供應至一些單元，故電力軌經常以相比於用於單元內之標準佈線軌道/信號線大許多的尺寸(例如，較大的寬度)實行。電力軌相比於正常佈線的尺寸差異通常可為3至4倍般大，因此電力軌利用了單元設計內的大量區域。需要較大臨界尺寸的電力軌以維持整個軌道中的適當電阻，俾維持適當的配電目標，其包括裝置內需供應至電力軌之IR壓降及頻率。
已設計一種方法以減小電力軌的橫向(寬度)尺寸，其係透過促使其在尺寸上較深(例如，高深寬比)，俾容許較小的由上而下之截面(例如，較小寬度的金屬線)、並同時有效地使電力軌中的總金屬體積維持相同或增加。深寬比之增加提供橫跨電力軌的較低電阻，其提供以下能力：維持需供應至電力軌之經改善的IR壓降及頻率。僅增加BEOL中之電力軌的深寬比經常係困難的，因為其會使較大深寬比之介層窗將信號線連接至裝置(例如，較高的介層窗電阻)、或者會需要信號線亦具有相似的深寬比，其會導致BEOL中之軌道間增加的電容。一種方法包含將電力軌「埋藏」或安置於實體裝置(例如電晶體)下方，其中電力軌的深寬比可獨立於BEOL中之信號線而增加，此提供以下手段：使通過電力軌的電阻顯著降低，而不會對BEOL中的介層窗電阻或電容造成任何負面影響。在此方法中，透過由下而上的方式將電源供應至金屬接觸窗，而非透過習知的下拉方式。
在實體裝置下方埋藏電力軌容許單元長度(footage)減小。例如，在標準單元佈局庫中，單元一般係實施為固定高度、可變寬度的單元。固定高度使單元能被成列放置、且使自動佈局設計的程序簡化。列方向係被稱為東-西方向的方向，而垂直於東-西方向的方向係被稱為南-北方向。根據此命名慣例，M0通常會含有在東-西方向上行進的線，而M1會具有在南-北方向上行進的線。後續的金屬層會垂直於先前的金屬層而施行。
在實體裝置下方埋藏電力軌容許單獨由佈線軌道或信號線的數目界定標準單元之單元高度，而非由電力軌及佈線軌道之組合界定。此提供以下能力：藉由結合此概念，簡單地從6.0至6.5佈線軌道(6.5T)之單元高度(假設每一電力軌寬度等於每一佈線軌道線的2或3倍之寬度)縮小至5.0佈線軌道之單元高度，即使實際的佈線軌道數目係相同的。
可沿著共通的電力軌而完成從鄰近單元至Vss或Vdd的連接(在南-北向上)。在一範例中，電力軌(例如，Vdd)係位在標準單元的上列與標準單元的下列之間的下方。電力軌在東-西方向上行進。例如，上列中的單元朝北，而下列中的單元朝南，且可共同使用電力軌以作為Vdd電源供應。電力軌可由上列中的朝北之單元分接、而同樣地可由下列中相鄰的朝南之單元分接。對於大的非埋藏式軌道之情況，可將其容納，因為軌道上存在足夠的空間以進行以上兩連接，且該等連接係以由上而下整合方法完成，在該方法中介層窗被轉移通過軌道至下方的金屬汲極(例如金屬化之通道或隧道)。因此，微影或圖案化中所完成的任何對準將由蝕刻處理直接轉移。然而，對於埋藏式軌道之實施例，電力軌可被封裝於淺渠溝隔離(STI)內、或同時於本體矽與STI之內，其取決於需要多大的深寬比以符合電阻規格。以下可能難以執行：形成向下通過置換金屬汲極之氧化物填充、並落在金屬軌道而非實體鄰接於軌道的STI上的連接。由於該處理的後續步驟為在形成與埋藏式軌道的連接之後使金屬汲極金屬化，故任何設置誤差會造成軌道之額外金屬填充。相反地，對電力軌形成不足連接的任何設置誤差造成重大的電阻問題，特別係在軌道與金屬汲極間的連接尺寸小於12nm之設計中。
對於來自南-北方向上之兩相鄰單元的兩源極/汲極接觸窗從共同電力軌下拉的情況，兩標準單元之間的源極/汲極接觸窗或電極可係實際上共享的，其使介層窗連接之設置能(a) 於直徑上增加以改善介層窗電阻、以及(b) 設置於電力軌寬度內之任何位置，因此提供一些邊緣設置誤差(EPE)之緩解。
在主動裝置下方埋藏電力軌之整合操作會帶來若干額外的挑戰。該等問題亦受若干因素所影響，其包括欲使用之軌道的尺寸、埋藏式軌道在整合處理序列中所欲實施之位置、靠近矽或SiGe鰭式結構(或用於奈米片環繞式閘極(GAA)處理中的Si / SiGe鰭式超晶格)的埋藏式電力軌設置、該等軌道所分接的密度與位置(兩者皆在單一標準單元內、以及在南-北方向上之兩相鄰單元間)、與軌道金屬化所需之任何相關襯層一同用於埋藏式軌道的金屬及其與金屬汲極之後續連接、以及對於在整合操作中建立埋藏式電力軌之方式及位置的熱限制。
本文之範例實施例主要著重於說明埋藏式電力軌之應用。然而此應用並非限制性的。可將本文之實施例延伸以包含任何背側接線(例如存在於實體裝置下方的佈線、或局部互連線、或單元與單元之互連線)、以及直接從晶圓背部供應電力軌的埋藏式電力分配網路。
目前不存在使實體裝置之底端上所完成的任何接線自對準的方法。此與接線是否包含埋藏式電力軌、記憶體之埋藏式字元線、埋藏式互連線、埋藏式佈線、邏輯之埋藏式單元間接線等等無關。
達成本文所揭示的自對準之多種方法提供以下能力：將用於邏輯設計的單元高度從目前的6.5T縮小至5T、或甚至更小，若與其他尺度概念(例如互補式FET堆疊奈米片架構)一同實施，其中4T或甚至3T之單元高度對於埋藏式電力軌係可行的。其最終亦提供可將單元本身彼此堆疊的機構。在一些範例中，揭示互補式堆疊奈米片(PMOS在NMOS上方)。如此堆疊裝置可與埋藏式背側接線的本文實施例一同使用，以延伸至複數單元堆疊，其中可在實體裝置下方、複數實體裝置之間、以及實體裝置上方完成佈置或線、及/或其他接線，其目前為用於金屬化之方法。
當然，本文所述之不同步驟的討論順序已為了清楚解釋而呈現。一般而言，可以任何適當順序執行該等步驟。此外，雖然本文之每個不同特徵、技術、構造等可於本揭示內容的不同地方討論，擬使每個概念可各自單獨或互相組合而執行。因此，可以許多不同方式實施及分析本發明。
本發明之態樣提供一種半導體裝置。該半導體裝置包含一電力軌，其係形成於一隔離渠溝中、並可選地往下延伸進入本體矽。電力軌係由一介電質蓋部或STI氧化物之第二沉積所覆蓋，以將該電力軌與HKMG(高k(介電係數)金屬閘)、閘電極、甚至源極/汲極電極隔離。再者，一開口部可係形成於該介電質蓋部中、且係以導電性材料填充，俾選擇性地將源極/汲極電極與該電力軌連接。
本發明之態樣提供一種用於製造半導體裝置的方法。該方法包含形成一電力軌於一隔離渠溝中、並可選地往下延伸進入本體矽。再者，該方法包含以一介電質蓋部覆蓋該電力軌的頂部，以將該電力軌與在該介電質蓋部上的導電性圖案結構隔離。接著，該方法包含在該介電質蓋部中選擇性地形成一開口部、並以導電性材料填充該開口部，俾透過經填充之該開口部而選擇性地將導電性圖案結構與該電力軌連接。介電質蓋部的材料可不同於周圍的STI氧化物，以在形成介層窗結構時透過選擇性地蝕刻而提供一些自對準手段，該介層窗結構會將電力軌連接至源極/汲極電極。可透過下列方式以完成此頂蓋材料之沉積：(a) 習知的填充、CMP、及凹入處理，或者較佳係透過(b) 選擇性沉積處理，其中將該蓋部材料選擇性地沉積於埋藏式金屬軌的上表面上。
以下揭示內容提供用以施行本文標的之不同特徵的許多不同的實施例或範例。以下說明元件與配置的特定實例以簡化本發明。當然，其僅為範例且意不在限制本發明。例如，在說明中在第二特徵部上方或上形成第一特徵部可能包含第一與第二特徵部以直接接觸方式形成的實施例及亦可包含在第一與第二特徵部之間形成有額外特徵部以致於第一與第二特徵部不直接接觸的實施例。此外，本發明在各種實例中可重覆參考標號及/或字母。此重覆係基於簡化與清晰的目的，其本身並不代表各種實施例及/或配置討論之間的關係。
再者，在文中可為了說明便利性而使用空間相關的詞如「在…之下」、「在…下方」、「較低」、「在…上方」、「較高」等說明圖中所示之一元件或特徵部與另一元件或特徵部之間的關係。空間相關的詞彙意在包含除了圖中所示的位向外，裝置於使用中或操作時的不同位向。設備可具有其他位向(旋轉90度或其他位向)，因此文中所用的空間相關詞彙可以類似方式解釋。
本揭示內容提供用於隨機與非隨機邏輯單元兩者的自對準埋藏式電力軌之方法。埋藏式電力軌可於下列複數位置插入已知邏輯整合流程之間：(a) 對於標準鰭式場效電晶體(FINFET)處理，直接在本體矽上；(b) 對於SiGe P型金屬氧化物半導體(PMOS)通道處理，直接在本體矽上方之SiGe磊晶膜上；(c) 對於奈米線及/或奈米片處理，直接在Si/SiGe多層堆疊體上；或(d) 在已將FINFET或Si/SiGe FIN堆疊體圖案化、並以STI氧化物填充之後。
大體上，在佈局中加入虛擬FIN圖案以使圖案密度均勻，俾形成均勻的處理環境。在處理期間，例如，在某時間將虛擬FIN圖案移除，俾為空間建立空位或界定空間，隔離區域最終將形成於該處以使個別的FinFET裝置彼此分隔。虛擬FIN圖案移除被稱為FIN切割(cut)。虛擬FIN圖案移除可發生於FIN蝕刻處理之前，例如藉由移除用於遮蔽FIN蝕刻之硬遮罩層中的虛擬圖案，其被稱為CUT-最先途徑。虛擬FIN圖案移除可發生於FIN蝕刻處理的過程中，其被稱為CUT-中間途徑。虛擬FIN圖案移除可發生於FIN形成之後，其被稱為CUT-最後途徑。CUT-最後途徑可改善製程均勻性。
對於應用(a)、(b)、及(c)之形成埋藏式電力軌的情況，可在Si、SiGe、或堆疊的Si/SiGe FINs之任何圖案化之前，將軌道圖案化及蝕刻為固定距離。因此，將會在FIN蝕刻處理期間轉移完全的軌道深度，例如以相似於用於後段製程(BEOL)之雙重鑲嵌方法的方式。此方法可使FIN蝕刻處理以CUT-中間途徑或CUT-最先途徑完成，而非以目前先進技術之半導體製造商所青睞的CUT-最後途徑完成。
FIN CUT-最後途徑可能使埋藏式電力軌的深度及外形畸變。同樣地，對於形成深而窄的軌道之情況(其對於維持電阻控制係重要的)，此可能為鄰接於圖案化之鰭的深渠溝之間留下非常受限的空間，其可能造成實體電力軌尺寸及/或外形的一些畸變，而其可能具有同樣令人關注之針對電性參數之問題。此外，針對FINFET應用之情況，本體矽在電力軌及相鄰FINs形成之後可能受制於一些植入步驟，且以下係困難的：控制在與本體矽內所蝕刻之軌道毗鄰的區域中之植入物特性。如此的整合方法係可能的、且已經加以說明，但在實行上會有一些限制。對於在FIN蝕刻及STI填充/CMP之後圖案化埋藏式軌道的選擇(d)，此為包含埋藏式電力軌之較佳實施例。
在此實施例中，埋藏式軌道被圖案化於STI氧化物上方、並轉移通過STI氧化物，無論在STI氧化物之深度內良好地停止、或完全地通過STI氧化物之深度、並延伸進入本體矽。電力軌進入本體矽的最終深度會取決於埋藏式軌道的期望深寬比、且通常係由埋藏式電力軌的所用金屬之選擇及所需電阻所界定，俾符合電源分配網路規格(例如軌道之接點及供應電源的IR壓降、頻率)、及軌道之供應電源之頻率的設計法則符合性、及基於此頻率而佈置上金屬層的影響與從佈線觀點來看其對於面積尺度之影響。對於寬電力軌(相比於佈線之1.5T至4T寬軌道)之情況，此渠溝之深寬比係大約2.5至5.0。深而窄之軌道(其可具有額外優點)會具有高達3倍之深寬比、或7.5至15.0。此蝕刻處理會產生非常薄(＜ 12nm)的STI氧化物，其可與STI內的埋藏式電力軌之預期深度一樣深。將FINs之間的氧化物填充內的該等窄渠溝轉移的挑戰包括埋藏式電力軌之間的空間之傾覆邊緣與畸變，其對於寄生現象係關鍵的。
在一些實施例中，可透過自對準處理而形成窄的埋藏式軌道。例如，1.5T至4T電力軌尺寸的初始渠溝被蝕刻通過STI。一旦到達埋藏式電力軌之預期深度，可將蝕刻選擇性薄膜保形地沉積於渠溝內，以在渠溝的兩側上形成「間隔件」。此蝕刻選擇性材料可接著經歷正規的「間隔件開孔」蝕刻以移除渠溝底部處的保形沉積，僅留下沿著寬渠溝之側壁的蝕刻選擇性材料。可接著選擇氧化物或其他介電質襯層及/或填充材料以填充於渠溝的剩餘部分中、並將其平坦化(例如，透過CMP)或被乾或-濕蝕刻下凹以暴露「A/B」矩陣，其中A為STI氧化物或填充氧化物、且B為渠溝內的蝕刻選擇性材料。非侵略性蝕刻處理可接著用以挖掘蝕刻選擇性材料「B」，其使得兩相同渠溝形成。由於兩渠溝原本皆係透過單一保形沉積處理而形成，故其會係相同的。存在多種低侵略性蝕刻處理，其會防止兩相鄰窄渠溝之間的氧化物崩塌。一種此類處理為可達成高達一百比一之選擇性的化學氧化物移除(COR)氣相蝕刻，以及其他準原子層蝕刻(ALE)與濕及/或乾蝕刻。
一旦形成自對準渠溝以產生相鄰的埋藏式軌道，則可接著將電力軌金屬化。
埋藏式電力軌之金屬化的選擇影響軌道在整合流程中的何處形成並金屬化。對於執行S/D磊晶上的尖峰退火之前使埋藏式軌道形成且金屬化的情況，金屬在氧化物上必須具有非常良好的熱特性。例如，在尖峰退火溫度(其可介於700ºC至1100ºC之範圍內)、及用於金屬閘中的薄膜之任何沉積溫度下金屬應能為穩定的。對於在金屬閘沉積及S/D尖峰退火之前佈置埋藏式軌道的實施例，此將排除諸如銅(＜ 450ºC之熱穩定性)、鈷、或鋁之金屬的使用。在一些實施例中，鑒於釕在氧化物上具有優異的熱穩定性，其在整合過程中的此時可被選用以金屬化埋藏式電力軌，且亦可利用由下而上沉積處理以將釕沉積於深渠溝中。
依據本揭示內容的一種態樣，本文之技術包含電力軌對金屬汲極之由下而上自對準，其係透過在凹陷的釕(或任何其他金屬)上使用蝕刻選擇性蓋部。在一些實施例中，利用選擇性沉積處理以在金屬上沉積介電質(DoM)而形成蓋部。針對釕之情況，蓋部可為(a) 介電質且具有足夠尺寸以作為電力軌與位在軌道之上的金屬汲極之間的真介電質、或(b) 相對於邊界STI氧化物或介電質襯層而具蝕刻選擇性的、(c) 電力軌與任何突懸的閘電極之間的介電質、並且(d) 介電質蓋部的高度實際界定HKMG與閘電極相對於埋藏式電力軌頂部的最終配置，且可控制此沉積量以控制電力軌與閘電極之間的電容。由於埋藏式電力軌與任何矽或Si / SiGe鰭式結構之間的實體分隔亦必須被良好地控制，蓋部之蝕刻選擇性特性的考量確保在將金屬汲極開孔時可實行自對準蝕刻處理，在該自對準蝕刻處理中可沿埋藏式軌道之軸將蓋部開孔而不對STI氧化物進行進一步開孔。此亦使整個金屬汲極能將蓋部開孔至埋藏式電力軌、並將分接頭控制為初始埋藏式軌道渠溝之相同尺寸，其亦與埋藏式電力軌本身減去渠溝內所進一步沉積之襯層的尺寸相同。此容許欲使用的金屬汲極之尺寸的完全自由度，其對於接腳進入受限制之面積尺度裝置係有利的。
對於本文的一些實施例之詳細說明，金屬填充係考量於FIN蝕刻之後、並在最終STI填充之後執行，且向下研磨至鰭式結構的頂部。雖然範例實施例著重於埋藏式電力軌，但可將本文之技術延伸以包含任何背側接線，例如存在於實體裝置下方的佈線、或局部互連線、或單元與單元之互連線。
以下的範例實施例說明互補式堆疊奈米片裝置(CFET)的處理流程。應注意， FINFET、橫向堆疊奈米線及/或奈米片、及SiGe通道FINFET 裝置之加工所使用的整合處理流程係相似的。
透過使用凹陷之釕上方的蝕刻選擇性蓋部，使用電力軌對金屬汲極之由下而上自對準的半導體製程係參照圖1至圖14而說明。
依據一些實施例，圖1顯示半導體製造程序期間之半導體裝置100之一部分的示意圖。在圖1之範例中，已完成Si/SiGe FIN蝕刻，且襯墊氧化物/ SiN蓋部係餘留於FIN之頂部。在此特定情況下，在FIN蝕刻處理之前已完成(虛擬)FIN切割。此意指STI之下的矽在FINs間之區域被視為「平坦的」。對於FINCUT-最後途徑，在FINs之間的矽內提供深凹部的此步驟之前蝕刻虛擬FINs，其使得形成埋藏式電力軌更為困難。因此，對於FIN圖案之界定，較佳係使用FINCUT-最先或FINCUT-中間途徑，以將埋藏式電力軌包含於此範例整合過程中。以下圖式顯示範例結果。
圖2顯示淺渠溝隔離(STI)完成之後的半導體裝置100之示意圖，淺渠溝隔離(STI)係透過氧化物沉積、並經CMP回到Si/SiGe FIN結構之頂部而完成。
圖3顯示在光阻層中產生軌道渠溝的圖案之後的半導體裝置100之示意圖。在圖3之範例中，多層微影堆疊體係用於圖案轉移。多層微影堆疊體包含旋塗碳(SOC)之底層、含矽抗反射塗層(SiARC)之中間層、及頂層光阻。在一範例中，光阻中的圖案首先被轉移至中間層SiARC及底層SOC。接著，中間層SiARC及底層SOC中的圖案被往下轉移至STI氧化物(例如，經由軌道渠溝蝕刻)。
圖4顯示埋藏式軌道渠溝蝕刻之後的半導體裝置100之示意圖。應注意，埋藏式軌道渠溝係在STI氧化物上方圖案化、並例如藉由蝕刻而轉移通過STI氧化物。在一範例中，圖案轉移在STI氧化物之深度內良好地停止。在另一範例中，圖案轉移完全地蝕刻通過STI氧化物之深度、並延伸進入本體矽。對於寬電力軌(相比於佈線之1.5T至4T寬軌道)之情況，此渠溝之深寬比係大約2.5至5.0。深而窄之軌道可具有高達3倍之深寬比、或7.5至15.0。此蝕刻處理會產生非常薄(＜ 12nm)的STI氧化物，其係與STI內的埋藏式電力軌之預期深度一樣深。將FINs之間的氧化物填充內的該等窄渠溝轉移的挑戰包括埋藏式電力軌之間的空間之傾覆邊緣與畸變。以下圖式顯示範例結果。
在FINFET應用中，本體矽可為高摻雜的，且將軌道完全保持於STI內係較佳的。保持STI內的深軌道，但使FIN的初始高度比傳統上所加工的高出許多。對於FINFET，鰭的尺寸通常在大約75A，因此在此範例實施例中，可使FIN之深寬比良好地擴展至超過15-1、甚至達到20-1。由於此為極具侵略性的、且易於造成鰭外形之畸變，故對於一些實施例而言，促使埋藏式軌道進入矽中可能係較佳的。在一實施例中，可透過自對準處理而形成窄的埋藏式軌道，其中初始渠溝在其被蝕刻通過STI時為較傳統的1.5T至4T電力軌之尺寸。
在埋藏式軌道渠溝被往下延伸至本體矽的實施例中，圖案轉移進入本體矽之後，藉由渠溝中的保形介電質沉積，使埋藏式軌道受益於與本體矽實體隔離。
圖5顯示沉積襯層(例如原子層沉積(ALD) SiO襯層)之後的半導體裝置100之示意圖。
一旦到達埋藏式電力軌之預期深度，可將蝕刻選擇性薄膜保形地沉積於渠溝內，以在渠溝的兩側上形成「間隔件」。此蝕刻選擇性材料可接著經歷正規的「間隔件開孔」蝕刻以移除渠溝底部處的保形沉積，僅留下沿著寬渠溝之側壁的蝕刻選擇性材料。
在本文的一實施例中，亦可透過自對準處理而形成窄的埋藏式軌道，其中初始渠溝在其被蝕刻通過STI時為較傳統的1.5T至4T電力軌之尺寸。一旦到達埋藏式電力軌之預期深度，可將蝕刻選擇性薄膜保形地沉積於渠溝內，以在渠溝的兩側上形成「間隔件」。
圖6顯示沉積蝕刻選擇性薄膜(例如，ALD犧牲薄膜)之後的半導體裝置100之示意圖。
此蝕刻選擇性材料可接著經歷正規的「間隔件開孔」蝕刻以移除渠溝底部處的保形沉積，僅留下沿著寬渠溝之側壁的蝕刻選擇性材料。氧化物或其他介電質襯層及/或填充材料接著用以填充於渠溝的剩餘部分中、並被平坦化(例如，CMP)或被乾或濕蝕刻下凹以暴露「A/B」矩陣，其中A為STI氧化物或填充之氧化物、且B為渠溝內的蝕刻選擇性材料。
圖7顯示氧化物填充之後的半導體裝置100之示意圖。
再者，非侵略性蝕刻處理可接著用以挖掘蝕刻選擇性材料「B」，其結果為形成兩相同渠溝。
圖8顯示形成兩相同渠溝之後的半導體裝置100之示意圖。
在一實施例中，由於兩渠溝原本皆係透過單一保形沉積處理而形成，故其可為相同的。存在多種低侵略性蝕刻處理，其防止兩相鄰窄渠溝之間的氧化物崩塌。一種此類處理為可達成高達一百比一之選擇性的化學氧化物移除(COR)氣相蝕刻，以及其他準原子層蝕刻(ALE)與濕及/或乾蝕刻。以下圖式顯示範例結果。
接著，在一範例中，渠溝的底部係以欲用作埋藏式電力軌之金屬及/或襯層填充。埋藏式電力軌之金屬化的選擇係基於軌道在整合流程中的何處形成並金屬化。對於在S/D磊晶上的尖峰退火完成之前使埋藏式軌道形成且金屬化的情況，金屬在氧化物上必須具有非常良好的熱特性 – 特別係在尖峰退火溫度(其在700至1100ºC之範圍內)、及用於金屬閘中的薄膜之沉積溫度下能夠係穩定的。對於在金屬閘沉積及S/D尖峰退火之前佈置埋藏式軌道的實施例，將排除諸如銅(＜ 450ºC之熱穩定性)、鈷、或鋁之金屬的使用。然而，鑒於釕在氧化物上具有優異的熱穩定性，其在整合過程中的此時可被選用以金屬化埋藏式電力軌，且亦可利用由下而上沉積處理以將釕沉積於深渠溝中。然而若欲使用諸如釕之金屬；此會因釕的電阻率及其後續的電阻而使埋藏式電力軌成為窄軌道而非1.5T至4T尺寸的軌道。由於由下而上連接至窄電力軌係更加困難的，因此在一些實施例中，與金屬汲極之連接可為自對準的。以下圖式顯示範例結果。
圖9顯示以釕填充渠溝底部之後的半導體裝置100之示意圖。在一範例中，將釕填充於渠溝及表面上、並回蝕(凹入)至渠溝底部。
本文之技術包含電力軌對金屬汲極之由下而上自對準，其係藉由在凹陷的釕(或任何其他金屬)上使用蝕刻選擇性蓋部。應注意，當電力軌係透過置換方法而產生時，可在S/D尖峰退火之後或實際的金屬汲極金屬化期間執行金屬化。針對釕之情況，蓋部可為(a) 介電質且具有足夠尺寸以作為電力軌與位在軌道之上的金屬汲極之間的真介電質、或(b) 相對於邊界STI氧化物或介電質襯層而具蝕刻選擇性的。
圖10顯示在凹陷的釕上形成蝕刻選擇性蓋部之後的半導體裝置100之示意圖。
接著以STI氧化物或其他介電質填充埋藏式軌道渠溝之剩餘部分，並接著往下研磨至FIN結構之頂部。
圖11顯示填充STI氧化物並往下研磨之後的半導體裝置100之示意圖。
接著，可執行STI凹部蝕刻處理以使STI下降至主動FIN之底部、或者對於此範例，下降至SiGe以用於互補式堆疊奈米片。STI蝕刻可止於埋藏式電力軌上方之蝕刻選擇性介電質蓋部的頂部。
圖12顯示STI凹部蝕刻處理之後的半導體裝置100之示意圖。
應注意，可使用其他可選的實施例以使埋藏式電力軌金屬化，俾促成釕以外或其他可選擇性沉積金屬的金屬選擇。能使其他金屬被用於埋藏式電力軌的另一選擇為實行完全置換金屬軌道，其中在埋藏式軌道渠溝界定處理期間，渠溝係完全以介電質填充並接著往下凹入至金屬化埋藏式軌道之預期高度，以取代使用金屬填充軌道及使用蝕刻選擇性介電質加蓋。在後續與金屬汲極之連接期間，可將整體置換軌道等向地移除、並接著以金屬再填充。對於埋藏式電力軌，不受干擾地穿過已知單元至鄰接的已知單元係有利的。有如此的連續電力軌金屬可為具挑戰性的。在此類實施例中，將整體置換軌道從作用接點至金屬汲極以及至無需連接之點移除。當填充金屬時，在此情況下的此類填充係作為「地道」填充(而非簡單的由上而下或由下而上之填充)，其中金屬沿著在金屬汲極下方通過的埋藏式軌道之長度而延伸，而沒有與軌道連接之需求。
繼續本文的整合實施例，其中軌道已被金屬化、並以蝕刻選擇性介電質蓋部加蓋，處理流程繼續進行到形成S/D之後、並經過尖峰退火、隨後經過置換金屬閘之金屬化。在整合流程中的此時，在預期的金屬汲極與電力軌之接點的所選點之間完成接觸窗。
示例性實施例使用互補式FET堆疊奈米片以作為範例，說明主要著重於由金屬汲極至Vss的分接頭，Vss連接至最底下的兩堆疊電極(下方為NMOS，而上方為PMOS)
此時，在金屬閘之金屬化期間金屬汲極尚未金屬化、而係利用氧化物填充。此時，將金屬汲極內的氧化物向下凹入至埋藏式電力軌上方之蝕刻選擇性介電質蓋部的頂部(或者，若STI與金屬汲極填充氧化物之間存在蝕刻停止層，則可完全移除氧化物)。蓋部之蝕刻選擇性特性的考量確保在將金屬汲極開孔時可採用自對準蝕刻處理，在該自對準蝕刻處理中可沿埋藏式軌道之軸將蓋部開孔而不對STI氧化物進行進一步開孔。此亦使完全的金屬汲極能將蓋部開孔至埋藏式電力軌、並始終將分接頭控制為初始埋藏式軌道渠溝之相同尺寸，其亦與埋藏式電力軌本身減去渠溝內所進一步沉積之襯層的尺寸相同。此容許欲使用的金屬汲極之尺寸的完全自由度，其對於接腳進入受嚴格限制之面積尺度裝置係有利的。
圖13顯示將金屬汲極內之氧化物向下凹入至蝕刻選擇性介電質蓋部的頂部之後的半導體裝置100之示意圖。
可藉由氧化物(若氧化物與STI之間存在停止層)或藉由一些通常稱為置換接觸窗所用的其他材料來填充金屬汲極。置換接觸窗一般對於下列多種薄膜具有非常良好的選擇性：(a) STI中的氧化物、(b) 保護埋藏式軌道的介電質蓋部、(c) 保護金屬閘的蓋部，其通常為氮化物的一些型態、以及(d) 低k(介電係數)閘極間隔件。以下圖式顯示範例結果。
圖14顯示以置換接觸窗填充之後的半導體裝置100之示意圖。
將連至電力軌的電力分接頭成像(圖案化)、並往下轉移通過置換接觸窗。由於埋藏式電力軌會使BEOL金屬線成為一系列密集佈線，南-北方向上之單元間的空間將僅為½關鍵金屬節距，或者考量晶圓加工之N5技術，約為12nm。關於兩相鄰單元到沿電力軌緯度軸之相同位置所構成的電力分接頭，此意指即使使用EUV多重圖案化仍難以將個別介層窗成像。因此，為了確保此情況不會造成相鄰單元間的短路，自對準係有利的。以下事實為使用自對準的原因：初始寬渠溝係自對準圖案化以形成兩相同窄軌道。因此每一「對」軌道會對應於Vdd或Vss，由於南-北方向上之單元共享Vdd或Vss軌道，故此自對準方法不僅提供電阻改善、同時亦確保兩相鄰單元不會短路。
圖15顯示使電力分接頭成像於SiARC與SOC層中(例如，從光阻層)之後的半導體裝置100之示意圖。
對於需要如此與電力軌分接的金屬汲極接觸窗，可將電力軌上方的蝕刻選擇性蓋部移除。
圖16顯示移除蝕刻選擇性蓋部之後的半導體裝置100之示意圖。
可接著移除金屬汲極中的置換接觸窗材料。
圖17顯示移除置換接觸窗之後的半導體裝置100之示意圖。
可接著將金屬汲極金屬化，其中同等地填充與預期軌道之連接，而不樂見的連接仍被蝕刻選擇性蓋部所阻隔，該等蝕刻選擇性蓋部在分接頭轉移通過金屬汲極期間未被開孔。
圖18顯示下電極之汲極金屬化之後的半導體裝置100之示意圖。
對於互補式堆疊奈米片FET的情況，下電極(NMOS)需與上電極(PMOS)各別地金屬化。同樣地，兩組電極皆存在連接至Vss與Vdd軌道的電力分接頭。在本文之實施例中，可使用複數金屬化及蝕刻步驟、或透過選擇性沉積而執行各別的金屬化。
圖19顯示使下電極之金屬化圖案形成、且沉積氧化物層之後的半導體裝置100之示意圖。
圖20顯示上電極之汲極金屬化、及氧化物層沉積之後的半導體裝置100之示意圖。
應注意，半導體裝置100中，各電力軌包含兩軌道線，該等軌道線係利用開孔間隔件技術而形成。可修改製程以形成寬電力軌，例如圖21至30所示。
依據一些實施例，圖21顯示半導體製造程序期間的半導體裝置200之一部分的示意圖。圖21相似於圖1。在圖21之範例中，已完成Si/SiGe FIN蝕刻，且襯墊氧化物/SiN蓋部係餘留於FIN之頂部。
圖22顯示淺渠溝隔離(STI)完成之後的半導體裝置200之示意圖，淺渠溝隔離(STI)係透過氧化物沉積、並經CMP回到Si/SiGe FIN結構之頂部而完成。圖22相似於圖2。
圖23顯示在光阻層中產生軌道渠溝的圖案之後的半導體裝置200之示意圖。圖23相似於圖3。
圖24顯示當圖案被轉移通過STI氧化物(例如，藉由蝕刻)時的半導體裝置200之示意圖。
圖25顯示當圖案被進一步轉移進入本體矽時的半導體裝置200之示意圖。在一範例中，在圖案轉移進入矽之前沉積間隔件層，以協助將圖案轉移進入矽。
圖26顯示沉積蝕刻選擇性薄膜(例如SiO/TaN襯層)之後的半導體裝置200之示意圖。
圖27顯示釕底部填充之後的半導體裝置200之示意圖。
圖28顯示將釕回蝕之後的半導體裝置200之示意圖。將釕蝕刻凹入特定深度的軌道渠溝中。此外，將襯層中的TaN移除。
圖29顯示在凹陷的釕上形成蝕刻選擇性蓋部之後的半導體裝置200之示意圖。
圖30顯示填充STI氧化物並往下研磨之後的半導體裝置200之示意圖。
再者，參照圖12至20而描述的相似處理可用以接續半導體裝置200上的製造程序。
應注意，半導體裝置100與200為帶有堆疊裝置的3D裝置。可將用於製造埋藏式電力軌的操作整合於無堆疊的正規FINFET。依據本揭示內容的一些實施例，圖31至39顯示形成FINFET裝置的埋藏式電力軌之中間階段的各種示意圖。
依據一些實施例，圖31顯示半導體製造程序期間的半導體裝置300之一部分的示意圖。在圖31之範例中，已完成Si FIN蝕刻，且襯墊氧化物/SiN蓋部係餘留於FIN之頂部。
圖32顯示淺渠溝隔離(STI)完成之後的半導體裝置300之示意圖，淺渠溝隔離(STI)係透過氧化物沉積、並經CMP回到Si/SiGe FIN結構之頂部而完成。
圖33顯示當圖案被轉移通過STI氧化物(例如，藉由蝕刻)時的半導體裝置300之示意圖。
圖34顯示沉積間隔件層之後的半導體裝置300之示意圖。間隔件層可透過下列方式而協助將圖案轉移進入矽：(a) 確保任何經開孔之矽或SiGe鰭式結構在埋藏式軌道渠溝圖案轉移進入本體矽期間不會受到蝕刻、以及(b) 確保(透過原子層沉積)最終的埋藏式電力軌與矽、SiGe、或矽/SiGe的鰭式結構之間存在固定且可控制的距離。
圖35顯示當圖案被進一步轉移進入本體矽時的半導體裝置300之示意圖。
圖36顯示沉積蝕刻選擇性薄膜(例如SiO/TaN襯層)、並接著從渠溝底部填充釕時的半導體裝置300之示意圖。
圖37顯示將釕回蝕之後的半導體裝置300之示意圖。將釕蝕刻凹入特定深度的軌道渠溝中。此外，將襯層中的TaN移除。
圖38顯示在凹陷的釕上形成蝕刻選擇性蓋部之後的半導體裝置300之示意圖。
圖39顯示在晶圓製造程序之後的半導體裝置300之示意圖。
如上所述，本文之範例實施例著重於埋藏式電力軌之應用。此僅為一範例實施例，可將本文之技術延伸以包含任何背側接線，例如存在於實體裝置或電晶體下方的佈線、或局部互連線、或單元與單元之互連線。
在前述中，已提出特定細節，例如處理系統之特定幾何以及其中所使用之各種元件及處理之敘述。然而，吾人應了解，本文之技術可實行於不同於這些特定細節之其他實施例，且此等細節係用於解釋之目的而非用以設限制。本文揭露之實施例已參照附圖敘述。同樣地，為了作解釋，已提到特定數目、材料、及配置以供徹底理解。然而，在無這些特定細節的情況下，亦可能實行實施例。實質上具有相同功能性結構之元件係由類似的參考符號表示，因此可能省略所有多餘的敘述。
已將各種技術描述為多重的分散操作以協助理解各實施例。不應將描述之順序解釋為隱含有這些操作必須係順序相依之意。這些操作確實並不需依描述之順序執行。所述之操作可依不同於所述之實施例的順序執行。在額外之實施例中，可執行各種額外之操作及/或可省略所述之操作。
本文所提及之「基板」或「目標基板」基本上指涉依據本發明受處理之物體。該基板可包含任何材料部分或元件之結構，特別係半導體或其他電子元件，以及可係例如一基底基板結構，如半導體晶圓、標線片，或是在基底基板結構之上方或覆蓋其上之膜層例如一薄膜。因此，基板並不限於任何特定基底結構、基底層或覆蓋層、經圖案化或未經圖案化，而係考量包含任何此類膜層或基底結構，以及任何膜層及/或基底結構之組合。該敘述可參考基板之特定類型，但僅為了說明之目的。
熟悉本技藝者亦將理解，可對前述之該技術之操作做出許多變化，而依然能達到本發明之相同目的。本發明之範圍擬包含此類變化。因此，不擬將本發明之實施例之以上敘述視為限制性者。而擬將對於本發明之實施例的任何限制於以下申請專利範圍說明。
100‧‧‧半導體裝置
200‧‧‧半導體裝置
300‧‧‧半導體裝置
由以下的實施方式並配合附圖加以閱讀可最適當地理解本發明之態樣。應理解，依據產業中的標準實施方式，許多特徵並非依比例繪製。事實上，為了清楚地討論，可將許多特徵的尺寸任意增加或減少。
依據本發明的一些實施例，圖1至20顯示半導體製造程序期間的中間階段之各種示意圖；
依據本發明的一些實施例，圖21至30顯示用於形成埋藏式電力軌的中間階段之各種示意圖；以及
依據本發明的一些實施例，圖31至39顯示用於形成埋藏式電力軌的中間階段之各種示意圖。

Claims (22)

  1. 一種半導體裝置，其包含： 一電力軌，其係形成於一隔離渠溝中； 在該電力軌上的一介電質蓋部，該介電質蓋部將該電力軌與在該介電質蓋部上的導電性圖案結構隔離；以及 一開口部，其係選擇性地形成於該介電質蓋部中，該開口部係以導電性材料填充，俾選擇性地將導電性圖案結構與該電力軌連接。
  2. 如申請專利範圍第1項之半導體裝置，其中該電力軌係形成於該隔離渠溝內。
  3. 如申請專利範圍第1項之半導體裝置，其中該電力軌形成通過該隔離渠溝並進入本體矽基板。
  4. 如申請專利範圍第1項之半導體裝置，其中該介電質蓋部係相對於形成該隔離渠溝之材料而具蝕刻選擇性，俾使在該介電質蓋部中產生該開口部之自對準能夠達成。
  5. 如申請專利範圍第4項之半導體裝置，其中該介電質蓋部係相對於SiO襯層而具蝕刻選擇性的材料，該SiO襯層係在該電力軌與該隔離渠溝、與該隔離渠溝中的氧化物之間。
  6. 如申請專利範圍第4項之半導體裝置，其中該介電質蓋部被選擇性地沉積於該電力軌上。
  7. 如申請專利範圍第1項之半導體裝置，其中該電力軌係由具有超過700之熱穩定性的金屬材料所形成。
  8. 如申請專利範圍第7項之半導體裝置，其中該金屬材料為一折射金屬。
  9. 如申請專利範圍第7項之半導體裝置，其中該金屬材料包含釕。
  10. 如申請專利範圍第1項之半導體裝置，其中預定該電力軌的深寬比以符合該電力軌的電阻率需求。
  11. 如申請專利範圍第10項之半導體裝置，其中該電力軌的臨界尺寸寬度係與該深寬比一同預定。
  12. 如申請專利範圍第8項之半導體裝置，其中藉由以該折射金屬填充軌道開口部、並將該折射金屬回蝕至一特定深度而形成該電力軌。
  13. 一種用於製造半導體裝置的方法，其包含： 在一隔離渠溝中形成一電力軌； 以一介電質蓋部覆蓋該電力軌的頂部，該介電質蓋部將該電力軌與在該介電質蓋部上的導電性圖案結構隔離；以及 在該介電質蓋部中選擇性地形成一開口部； 以導電性材料填充該開口部，俾透過經填充之該開口部而選擇性地將導電性圖案結構與該電力軌連接。
  14. 如申請專利範圍第13項之用於製造半導體裝置的方法，其中，在該隔離渠溝中形成該電力軌更包含： 在該隔離渠溝內蝕刻一電力軌渠溝；以及 在該隔離渠溝內形成該電力軌。
  15. 如申請專利範圍第13項之用於製造半導體裝置的方法，其中，在該隔離渠溝中形成該電力軌更包含： 蝕刻一電力軌渠溝通過該隔離渠溝並進入本體矽基板；以及 在該隔離渠溝及該本體矽基板中形成該電力軌。
  16. 如申請專利範圍第13項之用於製造半導體裝置的方法，其中，以該介電質蓋部覆蓋該電力軌的頂部俾將該電力軌與在該介電質蓋部上的該導電性圖案結構隔離更包含： 以相對於形成該隔離渠溝之材料而具蝕刻選擇性的該介電質蓋部覆蓋該電力軌的頂部，使在該介電質蓋部中產生該開口部之自對準能夠達成。
  17. 如申請專利範圍第16項之用於製造半導體裝置的方法，其中，以相對於形成該隔離渠溝之材料而具蝕刻選擇性的該介電質蓋部覆蓋該電力軌的頂部更包含： 選擇性地沉積介電質材料作為該介電質蓋部，該介電質材料係相對於SiO襯層而具蝕刻選擇性，該SiO襯層係在該電力軌與該隔離渠溝之間。
  18. 如申請專利範圍第13項之用於製造半導體裝置的方法，其中，在該隔離渠溝中形成該電力軌更包含： 使用具有超過700之熱穩定性的金屬材料以形成該電力軌。
  19. 如申請專利範圍第18項之用於製造半導體裝置的方法，其中，使用具有超過700之熱穩定性的金屬材料以形成該電力軌更包含： 使用釕以形成該電力軌。
  20. 如申請專利範圍第19項之用於製造半導體裝置的方法，其中，使用釕以形成該電力軌更包含： 以釕填充該隔離渠溝中的軌道開口部；以及 將釕回蝕至一特定深度。
  21. 如申請專利範圍第13項之用於製造半導體裝置的方法，其中，在該隔離渠溝中形成該電力軌更包含： 形成包含兩軌道線的該電力軌。
  22. 如申請專利範圍第21項之用於製造半導體裝置的方法，其中，形成包含該兩軌道線的該電力軌更包含： 將間隔件層保形地沉積於該隔離渠溝中的軌道開口部之側壁及底部上； 以一介電質材料填充該軌道開口部； 將形成於該軌道開口部之側壁上的該間隔件層移除，俾形成兩間隔件渠溝； 以釕填充該兩間隔件渠溝；以及 將釕回蝕至一特定深度。
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JP2020524907A (ja) 2020-08-20
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