JP7486058B2 - 後面電力供給における交換用埋設電力レール - Google Patents
後面電力供給における交換用埋設電力レール Download PDFInfo
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
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- H01L23/495—Lead-frames or other flat leads
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
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Description
本出願は、2019年2月19日に出願された米国仮特許出願第62/807,451号、「Replacement Buried Power-Rail in Backside Power Delivery」に対する優先権の利益を主張するものであり、その全体が参照により本明細書に組み込まれる。
Claims (14)
- 半導体デバイスを製造するための方法であって、
基板の第2の側面とは反対側にある前記基板の第1の側面からアクセスすることによって、前記基板上にダミー電力レールを形成することと、
前記基板の前記第1の側面にアクセスすることによって、前記基板上にトランジスタデバイス及び第1の配線層を形成することであって、前記ダミー電力レールが、前記基板の前記第1の側面の前記トランジスタデバイスのレベルの下に配置される、形成することと、
前記基板の前記第1の側面とは反対側にある前記基板の前記第2の側面からアクセスすることによって、前記ダミー電力レールを導電性電力レールと交換することと、
を含む、方法。 - 前記基板の前記第2の側面からアクセスすることによって、前記ダミー電力レールを前記導電性電力レールと交換することが、
前記第2の側面から前記基板を薄化することと、
前記第2の側面から前記ダミー電力レールを露出させることと、
前記第2の側面から前記ダミー電力レールを前記導電性電力レールと交換することと、
を含む、請求項1に記載の方法。 - 前記第2の側面から前記基板を薄化することが、
前記基板の前記第2の側面で、エッチングプロセス、研削プロセス、及び化学機械研磨(CMP)プロセスのうちの少なくとも1つを使用して前記基板を薄化すること、
を含む、請求項2に記載の方法。 - いったん前記ダミー電力レールが露出したら、前記薄化を停止すること、
を更に含む、請求項2に記載の方法。 - いったん前記ダミー電力レールの一部である停止層が検出されたら、前記薄化を停止すること、
を更に含む、請求項2に記載の方法。 - 前記ダミー電力レールの深さが、500ナノメートルよりも大きい、請求項4に記載の方法。
- 前記ダミー電力レールが露出されるまで、前記基板が薄化されると、前記薄化を停止すること、
を更に含む、請求項3に記載の方法。 - 前記ダミー電力レールとアラインするエッチングマスクパターンを形成することと、
前記エッチングマスクパターンに従って前記基板材料をエッチングして、前記ダミー電力レールを露出させることと、
を更に含む、請求項7に記載の方法。 - 前記ダミー電力レールの一部であるエッチング停止層が露出するまで、前記エッチングマスクパターンに従って前記基板材料をエッチングすること、
を更に含む、請求項8に記載の方法。 - 前記基板の前記第2の側面からアクセスすることによって、前記ダミー電力レールを導電性電力レールと交換することが、
前記ダミー電力レールの材料を前記基板の前記第2の側面から選択的に除去して、前記基板の前記第2の側面へのレール開口部を形成することと、
前記レール開口部を導電性スタックで充填して、前記導電性電力レールを形成することと、
を更に含む、請求項1に記載の方法。 - 前記レール開口部を、前記トランジスタデバイス及び前記第1の配線層の前記形成用のための処理温度よりも低い熱安定性の閾値温度を有する前記導電性スタックで充填すること、
を更に含む、請求項10に記載の方法。 - 前記レール開口部を、前記導電性電力レールを形成するバリア層及び銅層で充填すること、
を更に含む、請求項11に記載の方法。 - 前記レール開口部、及び前記基板の前記第2の側面の表面を前記導電性スタックで過剰に充填することと、
化学機械研磨(CMP)プロセスを実行して、前記基板の前記第2の側面の前記表面の前記導電性スタックを除去することと、
を更に含む、請求項11に記載の方法。 - 前記基板の前記第2の側面に第2の配線層を形成することであって、前記第2の配線層が前記導電性電力レールに電力を供給するように構成されている、形成すること、を更に含む、請求項1に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201962807451P | 2019-02-19 | 2019-02-19 | |
US62/807,451 | 2019-02-19 | ||
PCT/US2020/017427 WO2020171992A1 (en) | 2019-02-19 | 2020-02-10 | Replacement buried power rail in backside power delivery |
Publications (2)
Publication Number | Publication Date |
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JP2022521207A JP2022521207A (ja) | 2022-04-06 |
JP7486058B2 true JP7486058B2 (ja) | 2024-05-17 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2021548212A Active JP7486058B2 (ja) | 2019-02-19 | 2020-02-10 | 後面電力供給における交換用埋設電力レール |
Country Status (7)
Country | Link |
---|---|
US (1) | US20200266169A1 (ja) |
EP (1) | EP3928350A4 (ja) |
JP (1) | JP7486058B2 (ja) |
KR (1) | KR20210118136A (ja) |
CN (1) | CN113424307A (ja) |
TW (1) | TW202042319A (ja) |
WO (1) | WO2020171992A1 (ja) |
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US11271567B1 (en) * | 2020-09-04 | 2022-03-08 | Arm Limited | Buried metal technique for critical signal nets |
US11444073B2 (en) | 2020-10-27 | 2022-09-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Power distribution network |
US11521927B2 (en) | 2020-11-10 | 2022-12-06 | International Business Machines Corporation | Buried power rail for scaled vertical transport field effect transistor |
US11961802B2 (en) * | 2020-12-04 | 2024-04-16 | Tokyo Electron Limited | Power-tap pass-through to connect a buried power rail to front-side power distribution network |
US20220254769A1 (en) * | 2021-02-09 | 2022-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit and manufacturing method of the same |
US20220262791A1 (en) * | 2021-02-16 | 2022-08-18 | Intel Corporation | Integrated circuit structure with front side signal lines and backside power delivery |
US11791326B2 (en) | 2021-05-10 | 2023-10-17 | International Business Machines Corporation | Memory and logic chip stack with a translator chip |
US11881455B2 (en) | 2021-05-20 | 2024-01-23 | Samsung Electronics Co., Ltd. | Through silicon buried power rail implemented backside power distribution network semiconductor architecture and method of manufacturing the same |
US11915966B2 (en) | 2021-06-09 | 2024-02-27 | International Business Machines Corporation | Backside power rail integration |
US11984401B2 (en) | 2021-06-22 | 2024-05-14 | International Business Machines Corporation | Stacked FET integration with BSPDN |
US11804436B2 (en) | 2021-09-03 | 2023-10-31 | International Business Machines Corporation | Self-aligned buried power rail cap for semiconductor devices |
US11990412B2 (en) * | 2021-09-29 | 2024-05-21 | International Business Machines Corporation | Buried power rails located in a base layer including first, second, and third etch stop layers |
US11817394B2 (en) * | 2021-10-11 | 2023-11-14 | International Business Machines Corporation | Semiconductor circuit power delivery |
US11894436B2 (en) | 2021-12-06 | 2024-02-06 | International Business Machines Corporation | Gate-all-around monolithic stacked field effect transistors having multiple threshold voltages |
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- 2020-02-10 EP EP20760073.5A patent/EP3928350A4/en active Pending
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JP2008085226A (ja) | 2006-09-28 | 2008-04-10 | Renesas Technology Corp | 半導体ウェハおよびその製造方法、ならびに半導体装置の製造方法 |
US20150187642A1 (en) | 2013-12-30 | 2015-07-02 | International Business Machines Corporation | Double-sided segmented line architecture in 3d integration |
US20180145030A1 (en) | 2016-11-21 | 2018-05-24 | Imec Vzw | Integrated circuit chip with power delivery network on the backside of the chip |
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KR20210118136A (ko) | 2021-09-29 |
EP3928350A4 (en) | 2022-11-23 |
TW202042319A (zh) | 2020-11-16 |
CN113424307A (zh) | 2021-09-21 |
EP3928350A1 (en) | 2021-12-29 |
JP2022521207A (ja) | 2022-04-06 |
WO2020171992A1 (en) | 2020-08-27 |
US20200266169A1 (en) | 2020-08-20 |
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