TW201916131A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW201916131A
TW201916131A TW106146405A TW106146405A TW201916131A TW 201916131 A TW201916131 A TW 201916131A TW 106146405 A TW106146405 A TW 106146405A TW 106146405 A TW106146405 A TW 106146405A TW 201916131 A TW201916131 A TW 201916131A
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semiconductor substrate
semiconductor
modified layer
modified
layer
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TW106146405A
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TWI675412B (zh
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藤田努
友野章
大野天頌
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日商東芝記憶體股份有限公司
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
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Abstract

本發明之實施形態提供一種既抑制半導體晶片之不良且提高與封裝樹脂之密接性及雜質吸除效果之半導體裝置。本實施形態之半導體裝置具備半導體基板。半導體元件設置於半導體基板之第1面上。能量吸收膜設置於第1面上，吸收光能而發熱。第1絕緣膜設置於半導體元件及能量吸收膜上。第2絕緣膜設置於位在第1面相反側之半導體基板之第2面上。第1改質層設置於位在第1面之外緣與第2面之外緣之間之半導體基板之側面。第2改質層設置於能量吸收膜與第1改質層之間之側面。解理面設置於第1改質層與第2改質層之間之側面。

Description

半導體裝置及其製造方法
本發明之實施形態係關於一種半導體裝置及其製造方法。
已開發出一種藉由對半導體晶圓之切晶區照射雷射光而將半導體晶圓單片化成半導體晶片之切晶技術。於該切晶技術中，雷射光會將半導體晶圓內部之晶體改質，藉由自該經改質部位將半導體晶圓劈開，半導體晶圓會被單片化成半導體晶片。於以如上方式製造出之半導體晶片之側面，經雷射光改質所得之改質層會使與封裝樹脂之密接性提高，並使雜質吸除(gettering)效果提高。另一方面，此種改質層會使半導體晶片本身之強度降低，從而有導致形成於半導體晶片之元件發生不良之虞。
本發明之實施形態提供一種既抑制了半導體晶片之不良又提高了與封裝樹脂之密接性及雜質吸除效果之半導體裝置。本實施形態之半導體裝置具備半導體基板。半導體元件設置於半導體基板之第1面上。能量吸收膜設置於第1面上，吸收光能而發熱。第1絕緣膜設置於半導體元件及能量吸收膜上。第2絕緣膜設置於位在第1面相反側之半導體基板之第2面上。第1改質層設置於位在第1面之外緣與第2面之外緣之間之半導體基板之側面。第2改質層設置於能量吸收膜與第1改質層之間之側面。解理面設置於第1改質層與第2改質層之間之側面。
以下，參照圖式對本發明之實施形態進行說明。本實施形態並不限定本發明。於以下之實施形態中，關於半導體基板之上下方向，有以設置半導體元件之第1面為上之情形、及以無半導體元件之第2面為上之情形，且有與依照重力加速度而規定之上下方向不同之情形。又，圖式係模式性或概念性之圖，各部分之比例等未必與實物相同。於說明書及圖式中，對與已結合既給圖式加以敍述之要素相同之要素，標註相同之符號並適當省略詳細之說明。圖1係表示本實施形態之半導體晶片1之構成例之剖視圖。本實施形態之半導體晶片1例如例如為NAND(Not And，與非)型EEPROM(Electrically Erasable and Programmable Read-Only-Memory，電子可擦可程式化唯讀記憶體)等半導體記憶體。圖1中表示出了半導體晶片1之TSV(Through-Silicon Via，矽通孔)及其周邊部。半導體晶片1具備半導體基板10、半導體元件15、STI(Shallow Trench Isolation，淺槽隔離)20、焊墊(凸塊)30、配線層35、第1絕緣膜37、38、TSV40、第2絕緣膜50、及凸塊60。半導體基板10例如為矽基板，且已被薄膜化至例如約30 μm以下。半導體基板10具有第1面F1、及位於第1面F1相反側之第2面F2。於半導體基板10之第1面F1，具有形成半導體元件之工作區、及將工作區之間電性分離之STI(Shallow Trench Isolation)20。於工作區形成有記憶單元陣列、電晶體、電阻元件、電容器元件等半導體元件15。對於STI20，例如使用氧化矽膜等絕緣膜。於STI上20，未設置半導體元件，但設置有將半導體元件電性連接於TSV40之焊墊30及配線層35。半導體元件15設置於半導體基板10之第1面F1上。於半導體基板10之第2面F2，未設置半導體元件及配線，但設置有電性連接於TSV40之凸塊60等。焊墊30及配線層35設置於半導體基板10之第1面F1上，且電性連接於半導體元件(例如，電晶體等)。對於焊墊30及配線層35，例如使用銅、鋁、鎢或鈦等低電阻金屬。配線層35作為吸收切晶雷射之光能而發熱之能量吸收膜發揮功能。焊墊30亦可作為能量吸收膜之一部分發揮功能。TSV40及障壁金屬BM設置於半導體基板10之第1面F1與第2面F2之間，且貫通半導體基板10。進而，TSV40及障壁金屬BM貫通STI20，且電性連接於導電體30、35。藉此，TSV40及障壁金屬BM將與位於第1面F1側之配線層35之電性連接引延至第2面F2側為止。對於TSV40，例如使用鎳等低電阻金屬。障壁金屬BM設置於第5絕緣膜50(以下，亦稱之為間隔膜)50之側面。對於障壁金屬BM，例如使用Ti、Ta、Ru或其等之積層膜。以下，亦會將TSV40及障壁金屬BM統稱為金屬電極40、BM。再者，只要能將TSV40良好地嵌入至接觸孔CH內，便未必需要設置障壁金屬BM。第1絕緣膜37、38設置於位在半導體基板10之第1面F1上之半導體元件15及配線層35上。對於絕緣膜37，例如使用氧化矽膜、氮化矽膜等。對於絕緣膜38，例如使用聚醯亞胺等有機膜。作為第2絕緣膜之間隔膜50設置於位在第1面F1相反側之半導體基板10之第2面F2上。又，間隔膜50設置於金屬電極40、BM與半導體基板10之間，將金屬電極40、BM與半導體基板10電性分離。對於間隔膜50，例如使用氧化矽膜、氮化矽膜等絕緣膜。凸塊60在半導體基板10之第2面F2側設置於TSV40上。對於凸塊60，例如使用錫、銅等金屬。圖2係表示半導體晶片1之側面狀態之概念性立體圖。半導體基板10具有將第1面F1之外緣與第2面F2之外緣之間相連之側面FS。於側面FS設置有第1改質層LM1、第2改質層LM2、及解理面LC1、LC2。第1改質層LM1以與第1及第2面F1、F2大致平行地延伸之方式呈帶狀設置於側面FS，且位於第1面F1與第2面F2之中間位置。第1改質層LM1係使半導體基板10改質後之晶體缺陷層，藉由切晶雷射而形成於半導體基板10之側面FS之表層。如下所述，切晶雷射間斷地照射於半導體晶圓之切晶區域，於焦點位置利用熱將半導體晶圓之晶體(晶體矽)改質(例如非晶化或多晶化)。因此，第1改質層LM1之晶體缺陷部分間斷地設置於半導體基板10之側面FS。第1改質層LM1之D1方向之厚度(寬度)W1例如為10 μm以下。D1方向為半導體基板10之厚度方向(自第1面F1向第2面F2之方向或其相反方向)。再者，第1改質層LM1之晶體缺陷之大小大於第2改質層LM2之晶體缺陷之大小。第2改質層LM2與第1改質層LM1同樣地，以與第1及第2面F1、F2大致平行地延伸之方式呈帶狀設置於側面FS，但第2改質層LM2設置得較第1改質層LM1更靠第1面F1側。即，第2改質層LM2設置於配線層35與第1改質層LM1之間之側面FS，且設置於第1面F1之表層。第2改質層LM2亦為藉由切晶雷射使半導體基板10改質後之晶體缺陷層，且亦形成於半導體基板10之側面FS之表層。第2改質層LM2之晶體缺陷部分亦與第1改質層LM1之晶體缺陷部分同樣地，間斷地設置於半導體基板10之側面FS。第2改質層LM2之D1方向之厚度(寬度)W2例如為10 μm以下。解理面LC1設置於第1改質層LM1與第2改質層LM2之間之側面FS。解理面LC2設置於第1改質層LM1與第2面F2之間之側面FS。解理面LC1、LC2係半導體基板10(例如矽基板)之解理面，且係單晶矽之晶面。因此，解理面LC1、LC2係晶體缺陷較第1及第2改質層LM1、LM2為少且幾乎無凹凸之鏡面狀態之面。即，解理面LC1、LC2係幾乎無經切晶雷射改質之改質面之光滑面。解理面LC1、LC2各自之D1方向之厚度(寬度)W3、W4例如為10 μm以上。例如，於雷射切晶中，雷射一面使半導體晶圓改質一面將其切斷。因此，改質後之半導體晶片之側面部分具有改質層(改質面)。改質層(改質面)例如由非晶矽或多晶矽等使單晶矽改質後之材料構成，且含有許多晶體缺陷。如上所述，本實施形態之半導體基板10之側面FS具有經切晶雷射改質之第1及第2改質層LM1、LM2、以及晶體缺陷較少之解理面LC1、LC2，而成為四層結構。於側面FS，第1及第2改質層LM1、LM2以外之區域成為解理面LC1、LC2。藉此，可維持半導體晶片1本身之機械強度。例如，於側面FS整面經改質之情形時，改質層之晶體缺陷較多，凹凸亦相對較大。於此種情形時，半導體晶片1之機械強度變弱，半導體晶片1變得容易破損或開裂。相對於此，本實施形態之半導體晶片1具有解理面LC1、LC2，而能夠某種程度地維持機械強度。另一方面，於側面FS整面成為解理面之情形時，金屬離子等雜質容易自側面FS侵入，而有可能對半導體元件15造成不良影響。又，由於解理面係光滑面，所以封裝樹脂與側面FS之密接性較差，封裝樹脂容易自側面FS剝離。針對此問題，本實施形態之半導體晶片1於側面FS設置了第1及第2改質層LM1、LM2。第1及第2改質層LM1、LM2具有相對較多之晶體缺陷，所以具有金屬離子等雜質之吸除效果。因此，藉由使第1改質層LM1位於第1面F1與第2面F2之間之側面FS，能於某種程度上抑制雜質自側面FS侵入。又，第2改質層LM2設置於半導體元件15之某第1面F1側(配線層35正下方)之側面FS。亦即，第2改質層LM2設置於半導體基板10之第1面F1表層側之側面FS。藉此，能於某種程度上抑制雜質自半導體基板10之第1面F1附近之側面FS(半導體元件15附近之側面FS)侵入。進而，藉由於側面FS設置有第1及第2改質層LM1、LM2，封裝樹脂與側面FS之密接性得以提高，從而封裝樹脂變得難以自側面FS剝離。為了設置第2改質層LM2，而於第1面F1上設置有作為能量吸收膜之配線層35。配線層35如下所述吸收雷射光而使半導體基板10之第1面F1側之表面層改質。藉此，第2改質層LM2設置於配線層35正下方之半導體基板10。為了將第2改質層LM2設置於半導體基板10之側面FS，而將配線層35設置至半導體晶片1之第1面F1之外緣上方為止。即，於半導體晶圓中，切晶線上亦設置有配線層35。藉此，於切晶線上之配線層35正下方之半導體基板10，形成第2改質層LM2。如上所述，於半導體晶片1中，能使半導體基板10之側面FS成為改質層LM1、LM2及解理面LC1、LC2之四層結構。改質層LM1、LM2能抑制雜質自側面FS之中間區域或半導體元件15附近之側面FS侵入。並且，能提高封裝樹脂與半導體晶片1之密接性。又，解理面LC1、LC2能維持半導體晶片1之機械強度。進而，第1絕緣膜37、38能抑制雜質自第1面F1侵入，作為第2絕緣膜之間隔膜50能抑制雜質自第2面F2侵入。即，第1絕緣膜37、38、50係為了提高吸除效果而設置。如此，根據本實施形態，不僅能抑制雜質自第1及第2面F1、F2侵入，藉由第1及第2改質層LM1、LM2，還能抑制雜質自側面FS侵入。其次，對本實施形態之半導體裝置之製造方法進行說明。圖3(A)～圖3(C)係表示本實施形態之半導體晶片1之製造方法之一例的立體圖或剖視圖。首先，於半導體晶圓100之第1面F1上形成圖1之半導體元件15。於半導體元件上形成配線層35，於半導體元件及配線層35上以及其等之周圍形成絕緣膜37、38。然後，於半導體晶圓100之第1面F1上貼附支持基板，利用CMP(Chemical Mechanical Polishing，化學機械拋光)法研磨(pre-grind，預磨)半導體晶圓100之第2面F2。研磨半導體晶圓100後，於半導體晶圓100之第2面F2上形成第2絕緣膜50。藉由預磨，半導體晶圓100之厚度會變成30 μm以下。然後，以將半導體晶圓100之第1面F1與第2面F2之間貫通之方式利用已知方法形成TSV40(via-last process，後通孔工序)。進而，於半導體晶片1之表面形成電極墊(未圖示)。亦可於電極墊上設置金屬凸塊(未圖示)。圖3(A)表示形成半導體元件及TSV後之半導體晶圓100。複數個半導體晶片1之間存在切晶線DL，如下所述，藉由沿該切晶線DL進行切斷，而將半導體晶片1單片化。將第1面F1上之支持基板卸除後，如圖3(B)所示，在張設於晶圓環130內之可撓性樹脂帶131上貼附半導體晶圓100之第1面F2。其次，使用雷射振盪器105，沿著該切晶線對半導體晶圓100之第2面F2之與切晶線DL對應之部分照射雷射光。藉此，於半導體晶圓100之內部(矽基板之內部)形成第1及第2改質層(非晶層或多晶矽層)LM1、LM2。圖4係沿著圖3(B)之切晶線DL之局部剖視圖。雷射振盪器105使雷射光自半導體基板10之第2面F2入射，並且於半導體基板10之任意深度位置聚焦。於本實施形態中，雷射光係以於第1面F1與第2面F2之中間區域聚焦之方式照射。雷射光較佳為具有800 nm以上且3000 nm以下之波長，以能夠將單晶矽改質。若波長低於800 nm，雷射光於矽內部吸收之概率增加而難以形成改質層。若波長超過3000 nm，則雷射光穿過矽之概率增加而難以形成改質層。例如，雷射光亦可為所謂之隱形雷射(stealth laser)。藉由將此種雷射照射至半導體基板10，能於雷射光之聚焦位置，例如將單晶矽加熱而改質為非晶矽或多晶矽。藉此，於雷射光之照射下，於位在第1面F1與第2面F2之中間區域之半導體基板10形成第1改質層LM1。又，雷射光自聚焦位置朝向第1面F1透過半導體基板10，而被作為能量吸收膜之配線層35吸收。此時，配線層35發熱，藉由該熱，配線層35附近之半導體基板10之表層區域被改質為非晶矽或多晶矽。藉此，於第1面F1附近之半導體基板10之區域形成第2改質層。再者，雷射光之強度設定為配線層35不會熔解之程度之強度。其原因在於，若雷射光之強度高達配線層35會熔解之程度，則半導體元件15有可能因該熱而遭到破壞。雷射光係按某間距P1之間隔進行照射。藉此，於改質層LM1中，改質部分121、122以某間距P1之間隔形成。若間距P1較窄，改質部分121相連，而成為層狀(帶狀)改質層LM1，改質部分122相連，而成為層狀(帶狀)改質層LM2。第1改質層LM1與第2改質層LM2之間之半導體基板10未被改質，而作為晶體矽殘留。第1改質層LM1與第1面F1之間之半導體基板10亦未被改質，而作為晶體矽殘留。若如下述般將半導體晶圓100單片化，則切晶線之未改質部分成為側面FS中之解理面LC1、LC2。另，於此階段，半導體晶圓100尚未被單片化成半導體晶片1。其次，如圖3(C)所示，自下方利用頂推構件132頂推樹脂帶131，藉此拉伸樹脂帶131(使之延展)。藉此，將樹脂帶131及半導體晶圓100一併向外方向拉伸。此時，半導體晶圓100沿著第1及第2改質層LM1、LM2(即，沿著切晶線)劈開，而被單片化成複數個半導體晶片1。藉此，半導體晶片1完成。此時，圖4之未改質部分於側面FS成為解理面LC1、LC2。然後，半導體晶片1被分別拾取，安裝於安裝基板上，並利用封裝樹脂加以密封。至此，半導體封裝完成。如上所述，藉由於第1面F1上設置配線層35，而形成第2改質層LM2。藉此，能使半導體基板10之側面FS成為改質層LM1、LM2及解理面LC1、LC2之四層結構。改質層LM1、LM2能抑制雜質自側面FS之中間區域或半導體元件15附近之側面FS侵入。並且，能提高封裝樹脂與半導體晶片1之密接性。又，藉由解理面LC1、LC2，能維持半導體晶片1之機械強度。對本發明之若干實施形態進行了說明，但該等實施形態僅作為示例而提出，並非意欲限定發明之範圍。該等實施形態能以其他各種形態加以實施，於不脫離發明主旨之範圍內，能進行各種省略、替換、變更。該等實施形態及其變化包含於發明之範圍及主旨中，同樣包含於申請專利範圍所記載之發明及其等同之範圍內。[相關申請]本申請享有以日本專利申請2017-180403號(申請日：2017年9月20日)為基礎申請之優先權。本申請藉由參照該基礎申請而包含基礎申請之全部內容。
1‧‧‧半導體晶片
10‧‧‧半導體基板
15‧‧‧半導體元件
20‧‧‧ST
I30‧‧‧焊墊
35‧‧‧配線層
37‧‧‧第1絕緣膜
38‧‧‧第1絕緣膜
40‧‧‧TSV
50‧‧‧第2絕緣膜
60‧‧‧凸塊
100‧‧‧半導體晶圓
105‧‧‧雷射振盪器
121‧‧‧改質部分
122‧‧‧改質部分
130‧‧‧晶圓環
131‧‧‧可撓性樹脂帶
132‧‧‧頂推構件
BM‧‧‧障壁金屬
D1‧‧‧方向
DL‧‧‧切晶線
F1‧‧‧第1面
F2‧‧‧第2面
FS‧‧‧側面
LM1‧‧‧第1改質層
LM2‧‧‧第2改質層
LC1‧‧‧解理面
LC2‧‧‧解理面
P1‧‧‧間距
W1‧‧‧厚度(寬度)
W2‧‧‧厚度(寬度)
W3‧‧‧厚度(寬度)
W4‧‧‧厚度(寬度)
圖1係表示本實施形態之半導體晶片1之構成例之剖視圖。圖2係表示半導體晶片1之側面狀態之概念性立體圖。圖3(A)～(C)係表示本實施形態之半導體晶片1之製造方法之一例的立體圖或剖視圖。圖4係沿著圖3(B)之切晶線DL剖開之局部剖視圖。

Claims (9)

  1. 一種半導體裝置，其具備：半導體基板；半導體元件，其設置於上述半導體基板之第1面上；能量吸收膜，其設置於上述第1面上，吸收光能而發熱；第1絕緣膜，其設置於上述半導體元件及上述能量吸收膜上；第2絕緣膜，其設置於位在上述第1面相反側之上述半導體基板之第2面上；第1改質層，其設置於位在上述第1面外緣與上述第2面外緣之間之上述半導體基板之側面，且含有晶體缺陷；第2改質層，其設置於上述能量吸收膜與上述第1改質層之間之上述側面，且含有晶體缺陷；及解理面，其設置於上述第1改質層與上述第2改質層之間之上述側面。
  2. 如請求項1之半導體裝置，其中上述第2改質層設置於上述能量吸收膜正下方之上述側面。
  3. 如請求項1或2之半導體裝置，其中上述能量吸收膜為金屬膜。
  4. 如請求項1或2之半導體裝置，其中上述能量吸收膜於上述第1絕緣膜上設置至上述第1面之外緣上方為止。
  5. 如請求項1或2之半導體裝置，其中上述第2改質層設置於上述半導體元件正下方之上述半導體基板。
  6. 如請求項1或2之半導體裝置，其中上述第1改質層之晶體缺陷之大小大於上述第2改質層之晶體缺陷之大小。
  7. 一種半導體裝置之製造方法，其係製造具備設置於第1面上之半導體元件、設置於上述半導體元件上之第1絕緣膜、設置於上述第1絕緣膜上之能量吸收膜、及設置於位在上述第1面相反側之第2面上之第2絕緣膜之半導體基板者，且具備：將上述半導體基板貼附於帶上；自上述第2面沿著上述半導體基板之切晶線，以在位於上述第1面與上述第2面之中間區域之上述半導體基板上聚焦之方式照射雷射光；及拉伸上述帶，藉此將上述半導體基板沿上述切晶線切斷而單片化為上述半導體晶片。
  8. 如請求項7之半導體裝置之製造方法，其中於上述雷射光之照射下，將位於上述第1面與上述第2面之中間區域之上述半導體基板改質為第1改質層，並且將上述能量吸收膜附近之上述半導體基板改質為第2改質層。
  9. 如請求項8之半導體裝置之製造方法，其中於上述雷射光之照射下，上述第1改質層與上述第2改質層之間之上述半導體基板不被改質。
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EP2908335B1 (en) * 2014-02-14 2020-04-15 ams AG Dicing method
JP5863891B2 (ja) * 2014-07-01 2016-02-17 浜松ホトニクス株式会社 レーザ加工装置、レーザ加工装置の制御方法、レーザ装置の制御方法、及び、レーザ装置の調整方法
JP2016129203A (ja) * 2015-01-09 2016-07-14 株式会社ディスコ ウエーハの加工方法
JP6576212B2 (ja) * 2015-11-05 2019-09-18 株式会社ディスコ ウエーハの加工方法
JP6576211B2 (ja) * 2015-11-05 2019-09-18 株式会社ディスコ ウエーハの加工方法

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