TW201836022A - 半導體裝置之製造方法及半導體裝置 - Google Patents

半導體裝置之製造方法及半導體裝置 Download PDF

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TW201836022A
TW201836022A TW106122791A TW106122791A TW201836022A TW 201836022 A TW201836022 A TW 201836022A TW 106122791 A TW106122791 A TW 106122791A TW 106122791 A TW106122791 A TW 106122791A TW 201836022 A TW201836022 A TW 201836022A
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substrate
semiconductor substrate
semiconductor
substrates
groove
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TW106122791A
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TWI635544B (zh
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志摩真也
高野英治
久米一平
野田有輝
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東芝記憶體股份有限公司
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Abstract

本發明之實施形態提供一種能夠一面抑制半導體晶圓損傷、一面在將複數個半導體晶圓積層後一起進行單片化之半導體裝置之製造方法及半導體裝置。 本實施形態之半導體裝置之製造方法係將第1半導體基板與第2半導體基板積層，該第1半導體基板具有包含半導體元件之第1面及位於該第1面之相反側之第2面，該第2半導體基板具有包含半導體元件之第3面及位於該第3面之相反側之第4面。自第1半導體基板之第2面進行蝕刻，形成自該第2面到達至第1面之第1接觸孔，並且於第1半導體基板之第2面中之第1區域形成第1槽。形成被覆第1槽之第1遮罩材。將第1遮罩材用作遮罩而於第1接觸孔內形成第1金屬電極。去除第1遮罩材之後，將第1半導體基板之第1區域切斷。

Description

半導體裝置之製造方法及半導體裝置
本發明之實施形態係關於一種半導體裝置之製造方法及半導體裝置。
開發有藉由將複數個半導體晶片積層而減少半導體裝置整體之佔有面積之技術。被積層之半導體晶片彼此係藉由被稱為TSV(Through-Silicon Via，矽穿孔)之貫通金屬而電性連接。 此種半導體裝置先前係藉由在利用切割而由半導體晶圓單片化為半導體晶片之後，將複數個半導體晶片積層而製造。另一方面，考慮有在將複數個半導體晶圓積層之後一起進行切割。但是，若將所積層之複數個半導體晶圓一次切割，則存在積層內部之電路等易因碎片或龜裂等而受到損傷之問題。
本發明之實施形態提供一種能夠一面抑制半導體晶圓之損傷，一面在將複數個半導體晶圓積層之後一起進行單片化之半導體裝置之製造方法及半導體裝置。 本實施形態之半導體裝置之製造方法係將第1半導體基板與第2半導體基板積層，該第1半導體基板具有包含半導體元件之第1面及位於該第1面之相反側之第2面，該第2半導體基板具有包含半導體元件之第3面及位於該第3面之相反側之第4面。自第1半導體基板之第2面進行蝕刻而形成自該第2面到達至第1面之第1接觸孔，並且於第1半導體基板之第2面中之第1區域形成第1槽。形成被覆第1槽之第1遮罩材。將第1遮罩材用作遮罩而於第1接觸孔內形成第1金屬電極。去除第1遮罩材之後，將第1半導體基板之第1區域切斷。
以下，參照圖式，對本發明之實施形態進行說明。本實施形態並不限定本發明。於以下之實施形態中，半導體基板之上下方向表示以供設置半導體元件之正面或其相反側之背面為上之情形時之相對方向，有時與按照重力加速度之上下方向不同。(第1實施形態)圖1(A)～圖8係表示第1實施形態之半導體裝置之製造方法之一例的剖視圖。於圖1(A)～圖8中，表示基板10a及10b之部分剖面。於第1實施形態中，在半導體基板10a及10b之兩者形成作為金屬電極之TSV，並且於半導體基板10a上積層半導體基板10b。半導體基板10a及10b例如可為具備NAND(Not-And，反及)型EEPROM(Electrically Erasable and Programmable Read-Only Memory，電可擦除唯讀記憶體)等之半導體基板。半導體基板10a及10b為切割前之晶圓狀態，尚未被單片化為半導體晶片。首先，於作為第2半導體基板之半導體基板10a之第3面F1a上，形成未圖示之STI(Shallow Trench Isolation，淺溝槽隔離)，而規定為有效區(active area)。半導體基板10a例如為矽基板。STI例如為矽氧化膜。繼而，於有效區形成半導體元件(未圖示)。半導體元件例如可為記憶胞陣列、電晶體、電阻元件、電容器元件等。於形成半導體元件時，在有效區或STI上，介隔層間絕緣膜而形成例如配線構造20a。半導體元件及配線構造20a由絕緣膜25a被覆。繼而，以連接於配線構造20a之方式形成焊墊30a。因此，於有效區或STI上形成作為導電體之配線構造20a及焊墊30a。配線構造20a及焊墊30a使用鎢或鈦等低電阻金屬。以下，亦將配線構造20a及焊墊30a統稱為導電體20a、30a。於在半導體基板10a之第3面F1a形成半導體元件等之後，半導體基板10a自與第3面F1a為相反側之第4面F2a被研磨，例如被薄膜化成約30 μm以下。藉此，可獲得圖1(A)所示之構造。再者，於圖1(A)中，表示為第3面F1a朝下。如圖1(B)所示，使用微影技術於第4面F2a上形成抗蝕劑膜PR。抗蝕劑膜PR被覆第4面F2a中除了被用於TSV之接觸孔之形成區域以外之區域。繼而，如圖2(A)所示，將抗蝕劑膜PR用作遮罩，利用RIE(Reactive Ion Etching，反應性離子蝕刻)法自第4面F2a對基板10a進行蝕刻。藉此，形成自第4面F2a到達至第3面F1a之接觸孔(第2接觸孔)CHa。為了將TSV連接於導電體20a、30a，接觸孔CHa形成於存在導電體20a、30a之區域。藉此，於接觸孔CHa之底部，導電體20a露出。於去除抗蝕劑膜PR之後，如圖2(B)所示般，使用CVD(Chemical Vapor Deposition，化學氣相沈積)法或ALD(Atomic Layer Deposition，原子層沈積)法，於接觸孔CHa之內側面、底面及半導體基板10a之第4面F2a上形成間隔膜40a。間隔膜40a例如使用矽氧化膜等絕緣膜。繼而，如圖3(A)所示，藉由利用RIE法對間隔膜40a進行回蝕，而對接觸孔CHa之底部之間隔膜40a進行蝕刻。由於接觸孔CHa之縱橫比較大，故間隔膜40a於第4面F2a上相對較厚地形成，於接觸孔CHa之底部基本不形成。因此，藉由對間隔膜40a進行回蝕，而接觸孔CHa貫通間隔膜40a到達至導電體20a、30a。即，接觸孔CHa延長至導電體20a、30a。繼而，如圖3(B)所示，於接觸孔CHa內形成障壁金屬50a。障壁金屬50a例如使用Ti或Cu等。繼而，如圖4(A)所示，於接觸孔CHa內沈積作為金屬電極之TSV60a之金屬材料。TSV60a例如使用Cu等金屬材料。藉此，可使TSV60a及障壁金屬50a連接於導電體20a、30a。繼而，如圖4(A)所示，使用CMP(Chemical Mechanical Polishing，化學機械拋光)法，將TSV60a平坦化，於保留接觸孔CHa內之TSV60a及障壁金屬50a之狀態下將位於第4面F2a上之TSV60a及障壁金屬50a去除。藉此，TSV60a及障壁金屬50a於相鄰之接觸孔CHa間被電性絕緣。繼而，如圖4(B)所示，將半導體基板10b積層於半導體基板10a之第4面F2a上。作為第1半導體基板之半導體基板10b具有與圖1(A)之半導體基板10a大致相同之構成。因此，於半導體基板10b之第1面F1b上，形成未圖示之STI，於有效區形成半導體元件等(未圖示)。於有效區或STI上，介隔層間絕緣膜而形成例如配線構造20b。半導體元件及配線構造20b由絕緣膜25b被覆。焊墊30b係以連接於配線構造20b之方式形成。因此，於有效區或STI上，形成作為導電體之配線構造20b及焊墊30b。以下，亦將配線構造20b及焊墊30b統稱為導電體20b、30b。於在半導體基板10b之第1面F1b形成半導體元件等之後，半導體基板10b自與第1面F1b為相反側之第2面F2b被研磨，例如被薄膜化成約30 μm以下。藉此，形成具有與半導體基板10a相同構成之半導體基板10b。半導體基板10b係使第1面F1b朝向半導體基板10a之第4面F2a而積層於半導體基板10a上。積層後，半導體基板10a及10b藉由熱壓接而接著。此時，半導體基板10b之焊墊30b與半導體基板10a之TSV60a接觸，而半導體基板10a與10b電性連接。繼而，如圖5(A)所示，使用微影技術於第2面F2b上形成抗蝕劑膜PR。抗蝕劑膜PR被覆除接觸孔之形成區域Rch及切割區域Rdc以外之區域。接觸孔之形成區域Rch係半導體基板10b之第2面F2b中形成被用於TSV之接觸孔之區域。切割區域Rdc係使所積層之半導體基板10a及10b成為個別之半導體晶片時被切斷之區域。繼而，如圖5(B)所示，將抗蝕劑膜PR用作遮罩，利用RIE法自第2面F2b對半導體基板10b進行蝕刻。藉此，形成接觸孔CHb作為自第2面F2b到達至第1面F1b之第1接觸孔。為了將TSV連接於導電體20b、30b，接觸孔CHb形成於存在導電體20b、30b之區域。藉此，於接觸孔CHb之底部，導電體20b露出。又，於第2面F2b中作為第1區域之切割區域Rdc，形成第1槽TRb。由於第1槽TRb之開口部之面積較接觸孔CHb之開口部之面積寬，故形成為較接觸孔CHb深。由於切割區域Rdc係藉由切割而被切斷之區域，故第1槽TRb亦可形成為較接觸孔CHb深。更確切地，由於在後續之切割步驟中，切割機DC容易將半導體基板10a及10b切斷，故第1槽TRb較佳為較深地形成。另一方面，由於半導體基板10a及10b非常薄，故若第1槽TRb過深，則有在切割步驟之前意外地產生龜裂等之虞。因此，第1槽TRb可某種程度上形成為較淺、或者亦可形成於切割區域Rdc之一部分而非整體。關於第1槽TRb之平面佈局，於下文中參照圖9(A)～圖9(D)進行說明。於去除抗蝕劑膜PR之後，如參照圖2(B)～圖3(B)所說明般，形成間隔膜40b(第1絕緣膜)及障壁金屬50b。藉此，如圖6(B)所示，於接觸孔CHb之內側面、第1槽TRb之內側面及底面、以及半導體基板10b之第2面F2b上形成間隔膜40b及障壁金屬50b。間隔膜40b及障壁金屬50b之材料可分別與間隔膜40a及障壁金屬50a之材料相同。由於將位於接觸孔CHb及第1槽TRb之底面之間隔膜40b利用RIE法回蝕，故於接觸孔CHb之底面無間隔膜40b。作為第1絕緣膜之間隔膜40b位於接觸孔CHb及第1槽TRb之各內側面。另一方面，障壁金屬50b設置於接觸孔CHb及第1槽TR之底面。藉此，於接觸孔CHb內，障壁金屬50b保持與基板10b電性絕緣之狀態而電性連接於導電體20b、30b。繼而，如圖6(B)所示，使用微影技術，利用作為第1遮罩材之抗蝕劑膜PR被覆接觸孔CHb及其周邊以外之區域。此時，抗蝕劑膜PR亦形成於第1槽TRb上，被覆第1槽TRb。繼而，將抗蝕劑膜PR用作遮罩，於接觸孔CHb內沈積作為第1金屬電極之TSV60b。TSV60b之材料可與TSV60a之材料相同。藉此，可使TSV60b電性連接於導電體20b、30b。繼而，將圖6(B)之抗蝕劑膜PR直接用作遮罩，以鍍覆法於TSV60b上形成凸塊70b。凸塊70b例如可使用錫或銅等可鍍覆之金屬材料。去除抗蝕劑膜PR之後，可獲得圖7(A)所示之構造。繼而，如圖7(B)所示，將凸塊70b及TSV60b用作遮罩，以濕式蝕刻對障壁金屬50b進行蝕刻。藉此，將第2面F2b上之障壁金屬50b及第1槽TRb之內表面之障壁金屬50b去除。因此，相鄰之TSV60b及凸塊70b相互電分離。另一方面，由於位於凸塊70b及TSV60b之正下方之障壁金屬50b被保留，故各TSV60b及凸塊70b維持電性連接於位於其下之導電體20b、30b之狀態。其後，如圖8所示，基板10a及10b於積層之狀態下被切割。此時，切割機DC將圖5(A)所示之第1槽TRb內之切割區域Rdc之基板10a及/或10b切斷。藉此，將積層之基板10a及10b單片化為積層之半導體晶片。將積層之半導體晶片以樹脂等封裝，而作為製品完成。根據本實施形態，於切割步驟中，由於切割機DC在第1槽TRb內進行切斷，故即便一次切割所積層之複數個基板10a及10b，亦不易產生碎片或龜裂等。因此，可抑制形成於基板10a及10b之半導體元件等損傷。即，即便於將複數個半導體晶圓積層後一起進行單片化，亦可抑制半導體晶圓之元件損傷。又，根據本實施形態，由於切割機DC在第1槽TRb內進行切斷，故於第1槽TRb之內側壁保留了間隔膜40b。因此，於單片化為半導體晶片之後，基板10b之側面由間隔膜40b被覆。藉此，可保護基板10b不受金屬污染等。又，若第1槽TRb形成得較深，並將間隔膜40b設置於基板10a及10b之側面，則可保護基板10a及10b不受金屬污染等。圖8係表示第1實施形態之半導體裝置之構成例之剖視圖。利用上述實施形態之製造方法而形成之半導體裝置具有如圖8所示般之構成。半導體裝置1具備基板10a、基板10b、配線構造20a、20b、絕緣膜25a、25b、焊墊30a、30b、間隔膜40a、40b、障壁金屬50a、50b、TSV60a、60b及凸塊70b。作為第2半導體基板之基板10a具有包含半導體元件之第3面F1a及位於該第3面F1a之相反側之第4面F2a。半導體元件設置於基板10a之有效區。配線構造20a介隔層間絕緣膜而設置於基板10a之第3面F1a上之有效區或STI上。半導體元件及配線構造20a由絕緣膜25a被覆。焊墊30a係以連接於配線構造20a之方式設置。因此，於有效區或STI上，設置有作為導電體之配線構造20a及焊墊30a。作為金屬電極之TSV60a係以於基板10a之第4面F2a與第3面F1a之間貫通基板10a之方式設置。TSV60a將導電體20a、30a與基板10b之焊墊30b之間電性連接。間隔膜40a及障壁金屬50a設置於基板10a與TSV60a之間。障壁金屬50a抑制TSV60a之金屬材料之擴散。間隔膜40a於障壁金屬50a與基板10a之間，將TSV60a與基板10a之間、及障壁金屬50a與基板10a之間電分離。作為第1半導體基板之基板10b積層於基板10a之上方。基板10b具有包含半導體元件之第1面F1b及位於該第1面F1b之相反側之第2面F2b。半導體元件設置於基板10b之有效區。配線構造20b介隔層間絕緣膜而設置於基板10b之第1面F1b上之有效區或STI上。半導體元件及配線構造20b由絕緣膜25b被覆。焊墊30b係以連接於配線構造20b之方式設置。因此，於有效區或STI上，設置有作為導電體之配線構造20b及焊墊30b。作為金屬電極之TSV60b係以於基板10b之第2面F2b與第1面F1b之間貫通基板10b之方式設置。TSV60b將導電體20b、30b與凸塊70b之間電性連接。TSV60b經由導電體20b、30b亦與基板10a之TSV60a電性連接。間隔膜40b及障壁金屬50b設置於基板10b與TSV60b之間。障壁金屬50b抑制TSV60b之金屬材料之擴散。間隔膜40b於障壁金屬50b與基板10b之間將TSV60b及障壁金屬50b與基板10b電分離。凸塊70b設置於TSV60b上。凸塊70b被用於與其他半導體裝置等連接之情形。此處，作為絕緣膜之間隔膜40b設置在位於基板10a之第1面F1b之外緣與第2面F2b之外緣之間的第1側面F3b。於切割步驟中，切割機DC在切割區域Rdc之第1槽TRb內將基板10a及/或10b切斷。因此，位於第1槽TRb之內側面之間隔膜40b於切割之後仍被保留。藉此，如圖8所示，間隔膜40b設置於第1側面F3b。根據第1槽TRb之深度，間隔膜40b可被覆基板10b之第1側面F3b之整體，或者亦可被覆基板10b之第1側面F3b之一部分。又，於第1槽TRb到達至基板10a之情形時，間隔膜40b亦可被覆基板10a之側面F3a之全部或一部分。如此，藉由間隔膜40b被覆基板10b之第1側面F3b之全體或一部分、或者基板10a之側面F3a之全部或一部分，而可抑制基板10a及10b之金屬污染等。於上述實施形態中，對兩片基板10a及10b進行了說明，但積層之基板之數量亦可為3片以上。於該情形時，例如，只要將與基板10a相同之基板積層n(n為2以上之整數)片，且於其最上段之基板上積層基板10b即可。第1槽TRb之深度亦可到達至位於基板10b之下之複數個基板10a。繼而，對第1槽TRb之平面佈局進行說明。圖9(A)～圖9(D)係表示第1槽TRb之佈局之例之俯視圖。以虛線表示之區域係切割區域Rdc。該等圖表示基板10a及10b之表面之一部分。以實線框表示之區域係第1槽TRb。切割區域Rdc於第2面F2b上之x方向及正交於x方向之y方向上延伸。x方向與y方向之交點之角部分成為半導體晶片之角部分。於圖9(A)中，在切割區域Rdc之全體設置有第1槽TRb。於該情形時，在切割步驟中，切割機可容易地將基板10a及10b切斷。另一方面，於切割前，由於基板10a及10b之切割區域Rdc之機械強度降低，故於基板10a及10b之搬送時等，存在基板10a及10b龜裂之情形。因此，第1槽TRb不能形成得太深。於圖9(B)中，在切割區域Rdc之交叉部分設置有第1槽TRb。於除該交叉部分以外之切割區域Rdc(以下稱為中心部分)，未設置第1槽TRb。於切割步驟中，半導體晶片之角部分易受到損傷。因此，藉由在切割區域Rdc之交叉部分設置第1槽TRb，可抑制半導體晶片之損傷。另一方面，於切割區域Rdc之中心部分，由於未設置第1槽TRb，故切割前之基板10a及10b之機械強度不會過於降低。因此，於圖9(B)所示之平面佈局中，可抑制切割步驟中之半導體晶片之損傷，並且於基板10a及10b之搬送時等可抑制基板10a及10b龜裂。於此種平面佈局之情形時，第1槽TRb亦可形成為到達至基板10a。於圖9(C)中，在切割區域Rdc斷續地呈縫線孔狀地設置有第1槽TRb。換言之，於切割區域Rdc，基板10b呈梯狀保留。藉此，切割前之基板10a及10b之機械強度不會過於降低。因此，於圖9(C)所示之平面佈局中，可抑制切割步驟中之半導體晶片之損傷，並且於基板10a及10b之搬送時等可抑制基板10a及10b龜裂。因此，即便於圖9(C)所示之佈局中，第1槽TRb亦可形成為到達至基板10a。於圖9(D)中，在切割區域Rdc設置有多個較TSV60b小之第1槽TRb。於該情形時，第1槽TRb之開口直徑較TSV60b之開口直徑小，故第1槽TRb之深度較TSV60b之深度淺。因此，切割前之基板10a及10b之機械強度不會過於降低。另一方面，由於設置有多個第1槽TRb，故於切割步驟中容易進行切割，可抑制半導體晶片損傷。於第1實施形態中，以基板10a之第4面F2a與基板10b之第1面F1b對向之方式將基板10a及10b積層。於該情形時，基板10a之TSV60a中第4面F2a側之端部被熱壓接於基板10b之焊墊30b，因此無需凸塊。TSV60a係如圖3(B)～圖4(A)所示般利用金屬鑲嵌法而形成。以下，將TSV60a之製造方法稱為“TSV之金屬鑲嵌形成法”。另一方面，基板10b之TSV60b中第2面F2b側之端部與外部之半導體裝置等連接，因此於該端部之上形成凸塊70b。TSV60b係如圖6(B)～圖7(B)所示般使用微影技術及蝕刻技術而形成。以下，將TSV60b之製造方法稱為“TSV之微影形成法”。(變化例)圖19係表示變化例之半導體裝置之製造方法之剖視圖。於第1實施形態中，在形成圖2(A)所示之接觸孔CHa時，於與切割區域Rdc對應半導體基板10a之部分未形成槽。即，半導體基板10a之切割區域未被蝕刻。但是，亦可如圖19所示，於形成接觸孔CHa時，在半導體基板10a之切割區域Rdc形成第2槽TRa。於該情形時，在形成圖2(A)所示之接觸孔CHa時，不僅形成接觸孔CHa，而且自半導體基板10a之第4面F2a進行蝕刻而於半導體基板10a之切割區域Rdc形成自第4面F2a到達至第3面F1a之第2槽TRa。繼而，如參照圖2(B)所說明般，使用CVD法或ALD法形成間隔膜40a。此時，間隔膜40a亦被覆第2槽TRa之內表面。繼而，如參照圖3(A)所說明般，利用RIE法對間隔膜40a進行回蝕。藉此，第2槽TRa之底部之間隔膜40a亦被蝕刻。繼而，形成被覆第2槽TRa之遮罩材。此時，遮罩材未被覆第1接觸孔CHa。將遮罩材用作遮罩而於接觸孔CHa內形成障壁金屬50a及TSV60a。然後，將遮罩材去除，如參照圖4(A)及圖4(B)所說明般，以使半導體基板10b之第1面F1b朝向半導體基板10a之第4面F2a上之方式將半導體基板10b積層於半導體基板10a上。以與第1實施形態相同之方式對半導體基板10b進行加工。藉此，可獲得圖19所示之構造。其後，基板10a及10b於積層之狀態下被切割。此時，切割機DC經由圖19所示之第1及第2槽TRb、TRa而將切割區域Rdc之基板10a及/或10b切斷。藉此，基板10a及10b被單片化為積層之半導體晶片。於本變化例中亦可獲得與第1實施形態相同之效果。再者，積層之半導體基板之數量並不限定於兩片，亦可為3片以上。於該情形時，積層於半導體基板10b之下之複數個半導體基板亦可與半導體基板10a同樣地被加工。(第2實施形態)圖10(A)～圖10(D)係表示第2實施形態之半導體裝置之製造方法之一例之剖視圖。於圖10(A)～圖10(D)中，表示基板10a及10b之全體之剖視圖。又，於圖10(A)～圖10(D)中，將導電體20a、30a、20b、30b、間隔膜40a、40b、及障壁金屬50a、50b等簡化地表示或省略。圖11(A)以後之圖式亦同樣。於第2實施形態中，以使基板10a之第3面F1a與基板10b之第1面F1b對向之方式將基板10a及10b積層。基板10a之第4面F2a及基板10b之第2面F2b可與外部之半導體裝置等連接。因此，於第2實施形態中，基板10a及10b各自之TSV60a及60b可使用“TSV之微影形成法”而形成。例如，如圖10(A)所示，首先，基板10a及10b係將基板10a之第3面F1a與基板10b之第1面F1b貼合而積層。繼而，使用CMP法，對基板10b自第2面F2b進行研磨，而將基板10b薄膜化。其後，使用“TSV之微影形成法”形成TSV60b。因此，如圖10(B)所示，於TSV60b上形成凸塊70b。又，於切割區域形成第1槽TRb。再者，第1槽TRb之配置存在與圖示之配置不同之情況。繼而，如圖10(C)所示，使基板10a及10b反轉，利用接著劑110將基板10b接著於支持基板100上。藉此，基板10a之第4面F2a朝向上方。此時，凸塊70b埋藏於接著劑110而受到保護。繼而，使用CMP法，對基板10a自第4面F2a進行研磨，而將基板10a薄膜化。其後，使用“TSV之微影形成法”形成TSV60a。因此，如圖10(D)所示，於TSV60a上形成凸塊70a。又，於切割區域形成第2槽TRa。再者，第2槽TRa之配置亦存在與圖示之配置不同之情形。TSV60a之形成方法及第2槽TRa之形成方法可分別與TSV60b及第1槽TRb之形成方法相同。例如，於第2實施形態中，對基板10a自第4面F2a進行蝕刻，第2接觸孔以自基板10a之第4面F2a到達至第3面F1a之方式形成。第2接觸孔對應於圖5(B)之CHb。與此同時，於基板10a之第4面F2a中作為第2區域之切割區域形成第2槽TRa。第2槽TRa對應於圖5(B)之TRb。第2槽TRa之位置對應於第1槽TRb之位置，若將基板10a及10b之積層方向設為z，則第2槽TRa於z方向上位於第1槽TRb之正上方或正下方。再者，第1及第2槽TRb、TRa之平面佈局可為圖9(A)～圖9(D)中之任一種。繼而，以被覆第2槽TRa且露出第2接觸孔之方式形成第2遮罩材。第2遮罩材對應於圖6(A)所示之抗蝕劑膜PR。將該第2遮罩材用作遮罩而於第2接觸孔內形成作為第2金屬電極之TSV60a。進而，於TSV60a上形成凸塊70b。藉此，可獲得圖10(D)所示之構造。其後，將基板10a及10b自支持基板100及接著劑110拆卸，並且基板10a及10b於第1及第2槽TRb、TRa中被切割。如此，基板10a及10b亦可以使第3面F1a與第1面F1b對向之方式積層。藉此，於基板10a及10b之兩者可形成切割用之第1及第2槽TRb、TRa。因此，於第2實施形態中，更容易進行切割。又，第2實施形態可獲得與第1實施形態相同之效果。(第3實施形態)圖11(A)～圖11(D)係表示第3實施形態之半導體裝置之製造方法之一例的剖視圖。於第3實施形態中，積層有兩組第2實施形態中所示之使第3面F1a與第1面F1b對向而積層之基板10a及10b。即，於第3實施形態中，將4片基板10a_1、10b_1、基板10a_2、10b_2積層。如圖11(A)所示，以使基板10a_1之第3面F1a_1與基板10b_1之第1面F1b_1對向之方式將基板10a_1及10b_1積層。又，以使基板10a_2之第3面F1a_2與基板10b_2之第1面F1b_2對向之方式將基板10a_2及10b_2積層。另一方面，如圖11(B)及圖11(C)所示，藉由熱壓接將基板10b_1之第2面F2b_1與基板10b_2之第2面F2b_2接著。因此，於第3實施形態中，基板10b_1及10b_2各自之TSV60b_1及60b_2係使用“TSV之金屬鑲嵌形成法”而形成。基板10a_1及10a_2各自之TSV60a_1及60a_2能夠連接於外部之半導體裝置等。因此，基板10a_1及10a_2各自之TSV60a_1及60a_2係使用“TSV之金屬鑲嵌形成法”而形成。例如，如圖11(A)所示，首先，基板10a_1及10b_1係將基板10a_1之第3面F1a_1與基板10b_1之第1面F1b_1貼合而積層。此外，基板10a_2及10b_2係將基板10a_2之第3面F1a_2與基板10b_2之第1面F1b_2貼合而積層。為了方便起見，將基板10a_1及10b_1設為積層體ST1，將基板10a_2及10b_2稱為積層體ST2。繼而，使用CMP法，自積層體ST1之第2面F2b_1進行研磨，而將基板10b_1薄膜化。又，自積層體ST2之第2面F2b_2進行研磨，亦將基板10b_2薄膜化。其後，使用“TSV之金屬鑲嵌形成法”形成TSV60b_1、60b_2。因此，如圖11(B)所示，於TSV60b_1、60b_2上未形成凸塊70b。又，於切割區域未形成槽。繼而，如圖11(C)所示，使積層體ST2反轉，並將其積層於積層體ST1上。此時，積層體ST2之第2面F2b_2與積層體ST1之第2面F2b_1以對向之方式被熱壓接。藉此，TSV60b_1與TSV60b_2電性連接。繼而，使用CMP法，自積層體ST2之第4面F2a_2進行研磨，而將基板10a_2薄膜化。其後，使用“TSV之微影形成法”形成TSV60a_2。因此，如圖11(D)所示，於TSV60a_2上形成凸塊70a_2。又，於切割區域形成第2槽TRa_2。TSV60a_2之形成方法及第2槽TRa_2之形成方法可分別與第2實施形態之TSV60a及第2槽TRa之形成方法相同。繼而，如圖11(E)所示，使積層體ST1、ST2反轉，並利用接著劑110將積層體ST1、ST2接著於支持基板100上。藉此，基板10a_1之第4面F2a_1朝向上方。此時，凸塊70a_2埋藏於接著劑110而受到保護。繼而，使用CMP法，自第4面F2a_1進行研磨，而將基板10a_1薄膜化。其後，使用“TSV之微影形成法”形成TSV60a_1。因此，如圖11(F)所示，於TSV60a_1上形成凸塊70a_1。又，於切割區域形成第2槽TRa_1。TSV60a_1之形成方法及第2槽TRa_1之形成方法可分別與第2實施形態之TSV60a及第2槽TRa之形成方法相同。其後，積層體ST1、TR2於槽TRa_1、TRa_2中被切割。如此，亦可將使兩片基板之第1面彼此對向而成之積層體ST1、ST2進一步積層。於第3實施形態中，可在基板10a_1及10a_2之兩者形成切割用槽TRa_1、TRa_2。因此，第3實施形態可獲得與第2實施形態相同之效果。再者，於第3實施形態中，對兩組積層體ST1、ST2進行了說明，但積層之積層體之數量亦可為3片以上。於該情形時，例如，只要積層n(n為2以上之整數)組兩面均由金屬鑲嵌形成法形成之積層體，且將其最上段及最下段之積層體設為ST1、ST2即可。槽TRa_1、TRa_2之深度可形成為自最上段或最下段起之任意深度。(第4實施形態)圖12(A)～圖18係表示第4實施形態之半導體裝置之製造方法之一例的剖視圖。第4實施形態與第1實施形態之不同點在於，在將基板10a及10b積層之後，一次形成TSV60及第1槽TR。首先，與第1實施形態同樣地形成基板10a及10b，並分別將基板10a及10b薄膜化。繼而，如圖12(A)所示，利用熱壓接將基板10a及10b積層。於第4實施形態中，以基板10a之第4面F2a與基板10b之第1面F1b對向之方式將基板10a及10b積層。如圖12(B)所示，使用微影技術，於第2面F2b上形成抗蝕劑膜PR。抗蝕劑膜PR被覆第2面F2b中除TSV用接觸孔之形成區域及第1槽之形成區域以外之區域。繼而，如圖13(A)所示，將抗蝕劑膜PR用作遮罩，自第2面F2b利用RIE法對基板10a及10b進行蝕刻。藉此，形成自第2面F2b到達至第3面F1a之接觸孔(第1接觸孔)CH。與此同時，於第2面F2b中作為第1區域之切割區域Rdc形成第1槽TR。又，如圖13(B)所示，對焊墊30b朝橫向(相對於基板10a及10b之積層方向大致垂直之方向)進行蝕刻。藉此，焊墊30b較基板10a及10b之側面更朝橫向凹陷。再者，第1槽TR之平面佈局可為圖9(A)～圖9(D)中之任一種。繼而，如圖14(A)所示，於接觸孔CH之內側面、第1槽TR之內側面及底面、以及半導體基板10b之第2面F2b上形成間隔膜40(第1絕緣膜)。此處，焊墊30b於接觸孔CH內，自基板10a及10b之側面朝橫向凹陷。進而，接觸孔CH之縱橫比較高。因此，如圖14(B)所示，間隔膜40不易附著於焊墊30b之表面。因此，間隔膜40基本上不附著於焊墊30b之表面、或者即便形成亦非常薄。間隔膜40b及障壁金屬50b之材料可分別與間隔膜40a及障壁金屬50a之材料相同。繼而，藉由對間隔膜40利用RIE法進行回蝕，而對接觸孔CH之底部之間隔膜40進行蝕刻。此時，附著於焊墊30b之表面之間隔膜40亦被去除。繼而，如圖15(A)所示，於接觸孔CH內形成障壁金屬50。如圖15(B)所示，障壁金屬50與間隔膜40同樣地基本上不附著於焊墊30b之表面、或者形成得非常薄。繼而，如圖16(A)所示，使用微影技術，利用抗蝕劑膜PR被覆接觸孔CH及其周邊以外之區域。此時，抗蝕劑膜PR亦形成於第1槽TR上，而被覆第1槽TR。繼而，將抗蝕劑膜PR用作遮罩，於接觸孔CH內沈積TSV60。TSV60亦進入至焊墊30b之凹處，從而亦電性連接於焊墊30b。藉此，可使TSV60電性連接於導電體20b、30b、20a、30a。繼而，將抗蝕劑膜PR直接用作遮罩，利用鍍覆法於TSV60上形成凸塊70。於去除抗蝕劑膜PR之後，將凸塊70及TSV60之上部用作遮罩，藉由濕式蝕刻對障壁金屬50進行蝕刻。藉此，如圖17所示般第2面F2b上及第1槽TR之內側面及底面之障壁金屬50被去除，因此相鄰之TSV60及凸塊70被相互電分離。另一方面，由於位於凸塊70及TSV60之正下方之障壁金屬50被保留，故各TSV60及凸塊70維持電性連接於位於其下之導電體20b、30b、20a、30a之狀態。其後，將基板10a及10b於積層狀態下進行切割。此時，切割機DC將第1槽TR內之基板10a、10b切斷。藉此，如圖18所示，積層之基板10a及10b被單片化為積層之半導體晶片。積層之半導體晶片利用樹脂等封裝，而作為製品完成。根據第4實施形態，於切割步驟中，由於切割機DC在第1槽TR內進行切斷，故即便對積層之複數個基板10a及10b同時進行切割，亦不易發生碎片或龜裂等。因此，第4實施形態可獲得與第1實施形態相同之效果。又，於第1槽TR之內側壁保留了間隔膜40。因此，於單片化為半導體晶片之後，基板10b及10a之側面被間隔膜40被覆。藉此，可保護基板10b及10a不受金屬污染等。再者，於第4實施形態中，對兩片基板10a及10b進行了說明，但積層之基板之數量亦可為3片以上。於該情形時，例如，只要積層n(n為2以上之整數)片相同之基板，且自其最上段之基板形成第1槽TR即可。第1槽TR之深度可為自最上段之基板至最下段之基板為止之任意位置。對本發明之若干實施形態進行了說明，但該等實施形態係作為示例而提出，並不意圖限定發明之範圍。該等實施形態能以其他各種方式實施，可於不脫離發明之主旨之範圍內進行各種省略、替換及變更。該等實施形態或其變化包含於發明之範圍或主旨內，同樣地包含於申請專利範圍所記載之發明及其均等之範圍內。 [相關申請案] 本申請案享有以日本專利申請案2017-56174號(申請日：2017年3月22日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
10a‧‧‧基板
10a_1‧‧‧基板
10a_2‧‧‧基板
10b‧‧‧基板
10b_1‧‧‧基板
10b_2‧‧‧基板
20a‧‧‧配線構造
20b‧‧‧配線構造
25a‧‧‧絕緣膜
25b‧‧‧絕緣膜
30a‧‧‧焊墊
30b‧‧‧焊墊
40‧‧‧間隔膜
40a‧‧‧間隔膜
40b‧‧‧間隔膜
50‧‧‧障壁金屬
50a‧‧‧障壁金屬
50b‧‧‧障壁金屬
60‧‧‧TSV
60a‧‧‧TSV
60a_1‧‧‧TSV
60a_2‧‧‧TSV
60b‧‧‧TSV
60b_1‧‧‧TSV
60b_2‧‧‧TSV
70‧‧‧凸塊
70a‧‧‧凸塊
70a_1‧‧‧凸塊
70a_2‧‧‧凸塊
70b‧‧‧凸塊
100‧‧‧支持基板
110‧‧‧接著劑
CH‧‧‧接觸孔
Cha‧‧‧接觸孔
CHb‧‧‧接觸孔
DC‧‧‧切割機
F1a‧‧‧第3面
F1a_1‧‧‧第3面
F1a_2‧‧‧第3面
F1b‧‧‧第1面
F1b_1‧‧‧第1面
F1b_2‧‧‧第1面
F2a‧‧‧第4面
F2a_1‧‧‧第4面
F2a_2‧‧‧第4面
F2b‧‧‧第2面
F2b_1‧‧‧第2面
F2b_2‧‧‧第2面
F3a‧‧‧側面
F3b‧‧‧第1側面
PR‧‧‧抗蝕劑膜
Rch‧‧‧接觸孔之形成區域
Rdc‧‧‧切割區域
TR‧‧‧第1槽
TRa‧‧‧槽
TRa_1‧‧‧第2槽
TRa_2‧‧‧第2槽
TRb‧‧‧槽
ST1‧‧‧積層體
ST2‧‧‧積層體
圖1(A)～圖8係表示第1實施形態之半導體裝置之製造方法之一例的剖視圖。圖9(A)～(D)係表示第1槽TRb之佈局之例之俯視圖。圖10(A)～(D)係表示第2實施形態之半導體裝置之製造方法之一例的剖視圖。圖11(A)～(F)係表示第3實施形態之半導體裝置之製造方法之一例的剖視圖。圖12(A)～圖18係表示第4實施形態之半導體裝置之製造方法之一例的剖視圖。 圖19係表示第1實施形態之變化例之半導體裝置之製造方法之一例的剖視圖。

Claims (5)

  1. 一種半導體裝置之製造方法，其具備：將第1半導體基板與第2半導體基板積層，該第1半導體基板具有包含半導體元件之第1面及位於該第1面之相反側之第2面，該第2半導體基板具有包含半導體元件之第3面及位於該第3面之相反側之第4面；自上述第1半導體基板之上述第2面進行蝕刻，而形成自該第2面到達至上述第1面之第1接觸孔，並且於上述第1半導體基板之上述第2面中之第1區域形成第1槽；形成被覆上述第1槽之第1遮罩材；將上述第1遮罩材用作遮罩而於上述第1接觸孔內形成第1金屬電極；及 去除上述第1遮罩材之後，將上述第1半導體基板之上述第1區域切斷。
  2. 如請求項1之半導體裝置之製造方法，其中上述第1及第2半導體基板係將上述第1半導體基板之上述第1面與上述第2半導體基板之上述第3面貼合而積層，於去除上述第1遮罩材之後，進而具備：自上述第2半導體基板之上述第4面進行蝕刻，而形成自上述第2半導體基板之上述第4面到達至上述第3面之第2接觸孔，並且於上述第2半導體基板之上述第4面中之第2區域形成第2槽；形成被覆上述第2槽之第2遮罩材；及將上述第2遮罩材用作遮罩而於上述第2接觸孔內形成第2金屬電極；且 於去除上述第2遮罩材之後，將上述第1及第2半導體基板之上述第1及第2區域切斷。
  3. 如請求項1之半導體裝置之製造方法，其中於上述第1及第2半導體基板之積層前，進而具備：自上述第2半導體基板之上述第4面進行蝕刻，形成自該第4面到達至上述第3面之第2接觸孔，並且於上述第2半導體基板之上述第4面中之第2區域形成第2槽；形成被覆上述第2槽之第1遮罩材；將上述第1遮罩材用作遮罩，於上述第1接觸孔內形成第1金屬電極；及 於去除上述第1遮罩材之後，將上述第1半導體基板之上述第1面連接於上述第2半導體基板之上述第4面上，而將上述第1及第2半導體基板積層。
  4. 如請求項1之半導體裝置之製造方法，其中上述第1接觸孔係自上述第1半導體基板之上述第2面進行蝕刻而自該第1半導體基板之上述第2面到達至上述第2半導體基板之上述第3面，且上述第1槽形成於上述第1半導體基板之上述第2面中之上述第1區域。
  5. 一種半導體裝置，其具備：第1半導體基板，其具有包含半導體元件之第1面及位於該第1面之相反側之第2面；第2半導體基板，其具有包含半導體元件之第3面及位於該第3面之相反側之第4面，且積層於上述第1半導體基板；金屬電極，其設置於上述第1半導體基板之上述第2面與上述第1面之間、或上述第2半導體基板之上述第4面與上述第3面之間；及 絕緣膜，其設置於位於上述第1半導體基板之上述第1面之外緣與上述第2面之外緣之間的第1側面、或位於上述第2半導體基板之上述第3面之外緣與上述第4面之外緣之間的第2側面上。
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Families Citing this family (77)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
TWI822659B (zh) 2016-10-27 2023-11-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
EP3563411B1 (en) 2016-12-28 2021-04-14 Invensas Bonding Technologies, Inc. Method of processing a substrate on a temporary substrate
US20180182665A1 (en) 2016-12-28 2018-06-28 Invensas Bonding Technologies, Inc. Processed Substrate
WO2018126052A1 (en) 2016-12-29 2018-07-05 Invensas Bonding Technologies, Inc. Bonded structures with integrated passive component
US10522499B2 (en) 2017-02-09 2019-12-31 Invensas Bonding Technologies, Inc. Bonded structures
US10629577B2 (en) 2017-03-16 2020-04-21 Invensas Corporation Direct-bonded LED arrays and applications
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
US10784191B2 (en) 2017-03-31 2020-09-22 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10529634B2 (en) 2017-05-11 2020-01-07 Invensas Bonding Technologies, Inc. Probe methodology for ultrafine pitch interconnects
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US10658313B2 (en) 2017-12-11 2020-05-19 Invensas Bonding Technologies, Inc. Selective recess
US11011503B2 (en) 2017-12-15 2021-05-18 Invensas Bonding Technologies, Inc. Direct-bonded optoelectronic interconnect for high-density integrated photonics
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11256004B2 (en) 2018-03-20 2022-02-22 Invensas Bonding Technologies, Inc. Direct-bonded lamination for improved image clarity in optical devices
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US11244916B2 (en) 2018-04-11 2022-02-08 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US11171117B2 (en) 2018-06-12 2021-11-09 Invensas Bonding Technologies, Inc. Interlayer connection of stacked microelectronic components
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
EP3807927A4 (en) 2018-06-13 2022-02-23 Invensas Bonding Technologies, Inc. TSV AS A HIDEPAD
US10910344B2 (en) 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
WO2020010056A1 (en) 2018-07-03 2020-01-09 Invensas Bonding Technologies, Inc. Techniques for joining dissimilar materials in microelectronics
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11158606B2 (en) 2018-07-06 2021-10-26 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US11296044B2 (en) 2018-08-29 2022-04-05 Invensas Bonding Technologies, Inc. Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
KR20210104742A (ko) 2019-01-14 2021-08-25 인벤사스 본딩 테크놀로지스 인코포레이티드 접합 구조체
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US10854578B2 (en) 2019-03-29 2020-12-01 Invensas Corporation Diffused bitline replacement in stacked wafer memory
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
CN112151439A (zh) * 2019-06-28 2020-12-29 长鑫存储技术有限公司 晶圆及其制作方法、半导体器件
US11862602B2 (en) 2019-11-07 2024-01-02 Adeia Semiconductor Technologies Llc Scalable architecture for reduced cycles across SOC
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11876076B2 (en) 2019-12-20 2024-01-16 Adeia Semiconductor Technologies Llc Apparatus for non-volatile random access memory stacks
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
CN115088068A (zh) 2019-12-23 2022-09-20 伊文萨思粘合技术公司 用于接合结构的电冗余
CN113053802A (zh) * 2019-12-27 2021-06-29 台湾积体电路制造股份有限公司 半导体器件的形成方法
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
WO2021236361A1 (en) 2020-05-19 2021-11-25 Invensas Bonding Technologies, Inc. Laterally unconfined structure
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6013948A (en) * 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US20030042615A1 (en) * 2001-08-30 2003-03-06 Tongbi Jiang Stacked microelectronic devices and methods of fabricating same
US7453150B1 (en) * 2004-04-01 2008-11-18 Rensselaer Polytechnic Institute Three-dimensional face-to-face integration assembly
US7199449B2 (en) 2004-08-24 2007-04-03 Micron Technology, Inc. Wafer backside removal to complete through-holes and provide wafer singulation during the formation of a semiconductor device
TWM269570U (en) * 2004-12-24 2005-07-01 Domintech Co Ltd Improved structure of stacked chip package
US7485969B2 (en) * 2005-09-01 2009-02-03 Micron Technology, Inc. Stacked microelectronic devices and methods for manufacturing microelectronic devices
TWI324800B (en) 2005-12-28 2010-05-11 Sanyo Electric Co Method for manufacturing semiconductor device
JP4753725B2 (ja) * 2006-01-20 2011-08-24 エルピーダメモリ株式会社 積層型半導体装置
SG135979A1 (en) * 2006-03-08 2007-10-29 Micron Technology Inc Microelectronic device assemblies including assemblies with recurved leadframes, and associated methods
US7626269B2 (en) * 2006-07-06 2009-12-01 Micron Technology, Inc. Semiconductor constructions and assemblies, and electronic systems
SG139573A1 (en) * 2006-07-17 2008-02-29 Micron Technology Inc Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods
US8367471B2 (en) * 2007-06-15 2013-02-05 Micron Technology, Inc. Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices
SG150396A1 (en) * 2007-08-16 2009-03-30 Micron Technology Inc Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
KR20100021856A (ko) * 2008-08-18 2010-02-26 삼성전자주식회사 관통 전극을 갖는 반도체장치의 형성방법 및 관련된 장치
CN101766915A (zh) 2008-12-31 2010-07-07 鸿富锦精密工业（深圳）有限公司 电子玩具
US8503186B2 (en) * 2009-07-30 2013-08-06 Megica Corporation System-in packages
US8198174B2 (en) * 2009-08-05 2012-06-12 International Business Machines Corporation Air channel interconnects for 3-D integration
US8143097B2 (en) * 2009-09-23 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
JP5275192B2 (ja) * 2009-09-28 2013-08-28 ローム株式会社 半導体装置の製造方法、半導体装置およびウエハ積層構造物
JP2012064891A (ja) * 2010-09-17 2012-03-29 Toshiba Corp 半導体装置及びその製造方法
KR101690487B1 (ko) * 2010-11-08 2016-12-28 삼성전자주식회사 반도체 장치 및 제조 방법
US8742535B2 (en) * 2010-12-16 2014-06-03 Lsi Corporation Integration of shallow trench isolation and through-substrate vias into integrated circuit designs
KR101712630B1 (ko) 2010-12-20 2017-03-07 삼성전자 주식회사 반도체 소자의 형성 방법
US9385009B2 (en) * 2011-09-23 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming stacked vias within interconnect structure for Fo-WLCSP
JP2013206921A (ja) 2012-03-27 2013-10-07 Olympus Corp ウェハ積層体のダイシング方法および半導体装置
JPWO2014196105A1 (ja) 2013-06-03 2017-02-23 パナソニックＩｐマネジメント株式会社 半導体装置及びその製造方法
JP6380946B2 (ja) * 2013-11-18 2018-08-29 ローム株式会社 半導体装置および半導体装置の製造方法
US9431321B2 (en) 2014-03-10 2016-08-30 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device and semiconductor integrated circuit wafer
US20150262902A1 (en) * 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
TWI603447B (zh) * 2014-12-30 2017-10-21 精材科技股份有限公司 晶片封裝體及其製造方法
US20160260674A1 (en) * 2015-03-03 2016-09-08 Globalfoundries Inc. Removal of integrated circuit chips from a wafer
US9589903B2 (en) * 2015-03-16 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminate sawing-induced peeling through forming trenches
JP2016174101A (ja) * 2015-03-17 2016-09-29 株式会社東芝 半導体装置およびその製造方法
US9966360B2 (en) * 2016-07-05 2018-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US10163750B2 (en) * 2016-12-05 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure for heat dissipation

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