JP2009194249A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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Abstract
【解決手段】素子の形成された基板1SA,1SBからなる複数枚のウエハ1WA,1WBが貼り合わされてなり、各ウエハ1WA,1WBにおける別のウエハとの貼り合わせ面30a、30bには電気信号接続部9、26が設けられ、対向する電気信号接続部9、26同士のうちの少なくとも一方が、基板1SAが露出されている貼り合わせ面30aから突出して形成された凸状接続部であり、凸状接続部の形成されている貼り合わせ面30a上における前記電気信号接続部の配置されていない領域に、基板1SAと同じ材料からなり、半導体回路と絶縁され、貼り合わされたウエハ1WA,1WB間の間隔の寸法と同じ高さで貼り合わせ面30aから突出する補強凸部52が形成されている半導体装置とする。
【選択図】図19
Description
また、本発明は、複数枚のウエハを貼り合わせる際に、貼り合わせ面から突出する電気信号接続部に発生する損傷を効果的に防止することができ、信頼性に優れ、安定した性能の得られる半導体装置の製造方法を提供することを課題としている。
本発明者は、貼り合わせ面から突出する電気信号接続部(以下「凸状接続部」と呼ぶことがある。)の破損の原因について検討し、凸状接続部の破損が、複数枚のウエハを貼り合わせる際に負荷される荷重のばらつきにより、一部の凸状接続部に過剰な荷重が負荷されることによって発生することを見出した。そして、本発明者は、凸状接続部に負荷される荷重のばらつきを軽減することができ、凸状接続部を効果的に補強できる本発明の半導体装置および半導体装置の製造方法を想到した。
(2)図1(b)および図1(c)に示すように、複数の凸状接続部51bが隣接して配置された凸状接続部群51dが形成されている場合であって、凸状接続部群51dの周囲や近傍に他の凸状接続部51bを配置できるスペースがあるのに、周囲や近傍に他の凸状接続部51bが配置されていない場合に、凸状接続部群51dの最外周部に配置された凸状接続部、特に図1(b)および図1(c)に示すように凸状接続部群51dが矩形である場合には凸状接続部群51dの角部に配置された4つの凸状接続部51c。
(3)図1(d)に示すように、複数の凸状接続部51bが隣接して配置された凸状接続部群51dが2個以上形成されることにより、隣接する2個以上(図1(d)に示す例では2個)の凸状接続部群51dからなる凸状接続部集団51fが形成されている場合であって、凸状接続部集団51fの周囲や近傍に他の凸状接続部51bを配置できるスペースがあるのに、周囲や近傍に他の凸状接続部51bが配置されていない場合に、凸状接続部集団51fの最外周部に配置された凸状接続部、特に凸状接続部集団51fの外形が矩形である場合には凸状接続部集団51fの角部に配置された4つの凸状接続部51g。なお、凸状接続部集団51fにおいて、凸状接続部群51dの角部に配置された凸状接続部のうち、隣接する他の凸状接続部群51d側に配置された凸状接続部51eは、近傍に他の凸状接続部が配置されていることになるので、損傷が生じにくい。
また、上記の本発明の半導体装置においては、(イ)図2(b)および図2(c)に示すように、複数の前記凸状接続部51bが隣接して配置された凸状接続部群51dが形成され、前記補強凸部52が、前記凸状接続部群51dを取り囲むように複数配置されているものとすることができる。
また、上記の本発明の半導体装置においては、(ウ)図2(d)に示すように、複数の前記凸状接続部51bが隣接して配置された凸状接続部群51dが2個以上形成されることにより、隣接する2個以上の前記凸状接続部群51dからなる凸状接続部集団51fが形成され、前記補強凸部52が、前記凸状接続部集団51fを取り囲むように複数配置されているものとすることができる。
また、補強凸部が、基板が露出されている貼り合わせ面上に形成されたものであって、基板と同じ材料からなるものであるので、補強凸部は、基板を貼り合わせ面上から選択的にエッチングすることにより容易に形成できるものとなる。
図3〜図20は、本発明の半導体装置および半導体装置の製造方法を説明するための図である。図19は、本発明の半導体装置の一例を示した要部断面図であり、図3〜図18は、図19に示す半導体装置の製造工程を説明するための図であり、図20は、図19に示す半導体装置の製造工程を説明するためのフロー図である。
例えば、図2(a)に示すように、凸状接続部51aが、周囲や近傍に他の凸状接続部51aを配置できるスペースがあるのに、周囲や近傍に他の凸状接続部51aが配置されていない孤立した1つの凸状接続部51aである場合には、補強凸部52を、1つの凸状接続部51aを取り囲むように複数配置することが好ましい。
また、図2(d)に示すように、複数の前記凸状接続部51bが隣接して配置された凸状接続部群51dが2個以上形成されることにより、隣接する2個以上の凸状接続部群51dからなる凸状接続部集団51fが形成されている場合であって、凸状接続部集団51fの周囲や近傍に他の凸状接続部51bを配置できるスペースがあるのに、周囲や近傍に他の凸状接続部51bが配置されていない場合には、補強凸部52を、凸状接続部集団51fを取り囲むように複数配置することが好ましい。
最初に上側のウエハの製造工程(図20における1層目の上側ウエハの製造工程)を説明する。まず、上側のウエハ1WAを用意する(図20の工程100A)。続いて、図3に示すように、基板1SAの主面(すなわち、ウエハ1WAの主面)に、素子分離用の溝型の分離部2を形成する(図20の工程101A)。分離部2は、基板1SAの主面に分離溝2aを形成した後、分離溝2a内に、例えば酸化シリコン(SiO2)のような絶縁膜2bを埋め込むことにより形成する。また、基板1SAの活性領域の主面上に、例えば熱酸化法等により酸化シリコン等からなる絶縁膜3を形成する。
続いて、レジストパターンRAをエッチングマスクとして、そこから露出する絶縁膜3および基板1SAをエッチングすることにより、図4に示すように、基板1SAに深い分離溝5aを形成する。深い分離溝5aは、図4に示すように、基板1SAの主面から、その主面に対して交差(垂直に交差)する方向(すなわち、基板1SAの厚さ方向)に沿って延びており、素子分離用の分離溝2aよりも深い位置で終端している。
その後、第2薄型化処理として、ウエハ1WAの裏面に対して研磨処理を施す。第2薄型化処理は研磨で例示されるようにCMPのような機械的な要素と化学的な要素とを併せ持つ薄型化処理である。第2薄型化処理は、図13に示すように、貫通分離部5に達し、貫通配線部9に達しない状態(すなわち、貫通分離部5がウエハ1WAの裏面から露出し、貫通配線部9がウエハ1WAの裏面から露出されない状態)で処理を終了する。
次に、ウエハ1WAの主面にガラス支持基板21を固着した状態で、ウエハ1WAの裏面を薬液に浸し、レジストパターン52aをエッチングマスクとして、そこから露出する基板1SAをエッチング(ウエットエッチング、ドライエッチングもしくは両方)し、その後、レジストパターン52aを除去する。このことにより、図14に示すように、ウエハ1WAの裏面から貫通配線部9の端部9cを露出させて貼り合わせ面から突出する凸状接続部である貫通配線部9を形成するとともに、基板1SAの一部からなる柱状の補強凸部52を形成する。
このようにして上側のウエハ1WAの製造工程を終了する。
このようにして下側のウエハ1WBの製造工程を終了する。
なお、バンプ26が貫通配線部9に接続されており、貫通分離部5の枠内におさまっていない場合も存在する。この場合には、貼り合わせ面30aと貼り合わせ面30bとの間隔をバンプ26の高さに対して十分広く設定し、ウエハ1WAとバンプ26とが接触しないようにすればよい。
その後、上下のウエハ1WA,1WBの対向する貼り合わせ面30a、30bの隙間に絶縁性の接着剤30を注入する(図2の工程203)。その後、上側のウエハ1WAの主面からガラス支持基板21を剥離し、図19に示す半導体装置とする。
さらに、図20の工程100B〜106Bを経て中間層のウエハ1WCを用意する。この中間層のウエハ1WCには、最上層のウエハ1WAと同様に、貫通分離部5、貫通配線部9、補強凸部52が形成されている。中間層のウエハ1WCが最上層のウエハ1WAと異なるのは、中間層のウエハ1WCの主面上にバンプ下地導体パターン25とバンプ26とが形成されていることである。なお、この段階での中間層のウエハ1WCは、上記の第1〜第3薄型化処理が施されておらず厚いままとされている。
その後、上側の最上層のウエハ1WAの主面にガラス支持基板21を貼り合わせたままの状態で、下側の中間層のウエハ1WCを裏面側から図13および図14で説明したのと同様の薄型化処理により薄型化する(図20の中央の工程107A)。これにより、下側の中間層のウエハ1WCの裏面(貼り合わせ面30a)から貫通分離部5および貫通配線部9を露出(突出)させるとともに、補強凸部52を形成(突出)する。中間層のウエハ1WCの薄型化は、2枚のウエハ1WA,1WCを貼り合わせたままの状態で行うので、薄型化処理時におけるウエハ1WCの機械的強度を確保でき、ウエハ1WCのハンドリングの安定性を向上させることができる。
Claims (7)
- 素子の形成された基板からなる複数枚のウエハが貼り合わされてなり、各ウエハにおける別のウエハとの貼り合わせ面には電気信号接続部が設けられ、前記電気信号接続部と、対向する別のウエハに設けられた前記電気信号接続部とが電気的に接続されることにより所望の半導体回路が形成されている半導体装置において、
対向する電気信号接続部同士のうちの少なくとも一方が、前記基板が露出されている前記貼り合わせ面から突出して形成された凸状接続部であり、前記凸状接続部の形成されている前記貼り合わせ面上における前記電気信号接続部の配置されていない領域に、前記基板と同じ材料からなり、前記半導体回路と絶縁され、貼り合わされた前記ウエハ間の間隔の寸法と同じ高さで前記貼り合わせ面から突出する補強凸部が形成されていることを特徴とする半導体装置。 - 前記補強凸部が、1つの前記凸状接続部を取り囲むように複数配置されていることを特徴とする請求項1に記載の半導体装置。
- 複数の前記凸状接続部が隣接して配置された凸状接続部群が形成され、
前記補強凸部が、前記凸状接続部群を取り囲むように複数配置されていることを特徴とする請求項1に記載の半導体装置。 - 複数の前記凸状接続部が隣接して配置された凸状接続部群が2個以上形成されることにより、隣接する2個以上の前記凸状接続部群からなる凸状接続部集団が形成され、
前記補強凸部が、前記凸状接続部集団を取り囲むように複数配置されていることを特徴とする請求項1に記載の半導体装置。 - 前記凸状接続部のうちの少なくとも一部が、前記ウエハの一方の面と他方の面とを導通させる貫通配線部の端部であることを特徴とする請求項1〜請求項4のいずれかに記載の半導体装置。
- 請求項1〜請求項5のいずれかに半導体装置の製造方法であって、
前記複数枚のウエハのうちの少なくとも1つのウエハの前記基板が露出されている貼り合わせ面に、前記貼り合わせ面から突出する凸状接続部を形成する工程と、
前記凸状接続部の形成されている前記貼り合わせ面上における前記電気信号接続部の配置されていない領域に、前記基板と同じ材料からなり、前記半導体回路と絶縁され、貼り合わされる前記ウエハ間の間隔の寸法と同じ高さで前記貼り合わせ面から突出する補強凸部を形成する工程と、
前記複数枚のウエハを貼り合わせ、各ウエハの電気信号接続部同士を互いに電気的に接続することにより所望の半導体回路を形成する工程とを有していることを特徴とする半導体装置の製造方法。 - 前記凸状接続部を形成する工程および前記補強凸部を形成する工程が、
前記基板の一方の面に溝を形成し、前記溝に導体膜を埋め込むことにより、前記凸状接続部となる導電部を形成する工程と、
前記基板を他方の面から選択的にエッチングすることにより、前記凸状接続部となる導電部の一部を露出させて貼り合わせ面から突出する前記凸状接続部を形成するとともに、前記基板の一部からなる柱状の補強凸部を形成する工程とを有していることを特徴とする請求項6に記載の半導体装置の製造方法。
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US9324744B2 (en) | 2012-02-29 | 2016-04-26 | Canon Kabushiki Kaisha | Solid-state image sensor having a trench and method of manufacturing the same |
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