JP2018160519A - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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- JP2018160519A JP2018160519A JP2017056174A JP2017056174A JP2018160519A JP 2018160519 A JP2018160519 A JP 2018160519A JP 2017056174 A JP2017056174 A JP 2017056174A JP 2017056174 A JP2017056174 A JP 2017056174A JP 2018160519 A JP2018160519 A JP 2018160519A
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Abstract
Description
図1(A)〜図8は、第1実施形態による半導体装置の製造方法の一例を示す断面図である。図1(A)〜図8では、基板10aおよび10bの一部の断面を示す。第1実施形態では、半導体基板10aおよび10bの両方に金属電極としてのTSVを形成し、かつ、半導体基板10a上に半導体基板10bを積層する。半導体基板10aおよび10bは、例えば、NAND型EEPROM(Electrically Erasable and Programmable Read-Only Memory)等を備えた半導体基板でよい。半導体基板10aおよび10bは、ダイシング前のウェハ状態であり、まだ半導体チップに個片化されていない。
図19は、変形例に従った半導体装置の製造方法を示す断面図である。
図10(A)〜図10(D)は、第2実施形態に従った半導体装置の製造方法の一例を示す断面図である。図10(A)〜図10(D)には、基板10aおよび10bの全体の断面図を示す。また、図10(A)〜図10(D)では、導電体20a、30a、20b、30b、スペーサ膜40a、40b、および、バリアメタル50a、50b等は、簡略化して示されまたは省略されている。図11(A)以降の図面についても同様である。
図11(A)〜図11(D)は、第3実施形態に従った半導体装置の製造方法の一例を示す断面図である。第3実施形態では、第2実施形態で示した第3面F1aと第1面F1bとを対向させて積層した基板10aおよび10bを2組積層させている。即ち、第3実施形態では、4枚の基板10a_1、10b_1、基板10a_2、10b_2が積層される。
図12(A)〜図18は、第4実施形態による半導体装置の製造方法の一例を示す断面図である。第4実施形態では、基板10aおよび10bを積層後に、TSV60および第1溝TRを一括で形成する点で、第1実施形態と異なる。
Claims (5)
- 半導体素子を有する第1面と該第1面に対して反対側にある第2面とを有する第1半導体基板と、半導体素子を有する第3面と該第3面に対して反対側にある第4面とを有する第2半導体基板とを積層し、
前記第1半導体基板の前記第2面からエッチングして該第2面から前記第1面に達する第1コンタクトホールを形成し、かつ、前記第1半導体基板の前記第2面のうち第1領域に第1溝を形成し、
前記第1溝を被覆する第1マスク材を形成し、
前記第1マスク材をマスクとして用いて前記第1コンタクトホール内に第1金属電極を形成し、
前記第1マスク材の除去後、前記第1半導体基板の前記第1領域を切断する、ことを具備した半導体装置の製造方法。 - 前記第1および第2半導体基板は、前記第1半導体基板の前記第1面と前記第2半導体基板の前記第3面とを貼り合わせて積層され、
前記第1マスク材の除去後、
前記第2半導体基板の前記第4面からエッチングして前記第2半導体基板の前記第4面から前記第3面に達する第2コンタクトホールを形成し、かつ、前記第2半導体基板の前記第4面のうち第2領域に第2溝を形成し、
前記第2溝を被覆する第2マスク材を形成し、
前記第2マスク材をマスクとして用いて前記第2コンタクトホール内に第2金属電極を形成することをさらに具備し、
前記第2マスク材の除去後、前記第1および第2半導体基板の前記第1および第2領域を切断する、請求項1に記載の半導体装置の製造方法。 - 前記第1および第2半導体基板の積層前に、
前記第2半導体基板の前記第4面からエッチングして該第4面から前記第3面に達する第2コンタクトホールを形成し、かつ、前記第2半導体基板の前記第4面のうち第2領域に第2溝を形成し、
前記第2溝を被覆する第1マスク材を形成し、
前記第1マスク材をマスクとして用いて前記第1コンタクトホール内に第1金属電極を形成し、
前記第1マスク材の除去後、前記第2半導体基板の前記第4面上に前記第1半導体基板の前記第1面を接続して前記第1および第2半導体基板を積層する、ことをさらに具備する請求項1に記載の半導体装置の製造方法。 - 前記第1コンタクトホールは、前記第1半導体基板の前記第2面からエッチングして該第1半導体基板の前記第2面から前記第2半導体基板の前記第3面に達し、かつ、前記第1溝は、前記第1半導体基板の前記第2面のうち前記第1領域に形成される、請求項1に記載の半導体装置の製造方法。
- 半導体素子を有する第1面と該第1面に対して反対側にある第2面とを有する第1半導体基板と、
半導体素子を有する第3面と該第3面に対して反対側にある第4面とを有し、前記第1半導体基板に積層された第2半導体基板と、
前記第1半導体基板の前記第2面と前記第1面との間、あるいは、前記第2半導体基板の前記第4面と前記第3面との間に設けられた金属電極と、
前記第1半導体基板の前記第1面の外縁と前記第2面の外縁との間にある第1側面、または、前記第2半導体基板の前記第3面の外縁と前記第4面の外縁との間にある第2側面上に設けられた絶縁膜とを備えた半導体装置。
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TW106122791A TWI635544B (zh) | 2017-03-22 | 2017-07-07 | 半導體裝置之製造方法及半導體裝置 |
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US20180277493A1 (en) | 2018-09-27 |
US20190139908A1 (en) | 2019-05-09 |
CN108630596A (zh) | 2018-10-09 |
US10741505B2 (en) | 2020-08-11 |
CN108630596B (zh) | 2022-01-11 |
JP6640780B2 (ja) | 2020-02-05 |
US10211165B2 (en) | 2019-02-19 |
TWI635544B (zh) | 2018-09-11 |
TW201836022A (zh) | 2018-10-01 |
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