CN108630596B - 半导体装置的制造方法及半导体装置 - Google Patents

半导体装置的制造方法及半导体装置 Download PDF

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CN108630596B
CN108630596B CN201710660942.6A CN201710660942A CN108630596B CN 108630596 B CN108630596 B CN 108630596B CN 201710660942 A CN201710660942 A CN 201710660942A CN 108630596 B CN108630596 B CN 108630596B
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substrate
semiconductor
substrates
semiconductor substrate
contact hole
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CN108630596A (zh
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志摩真也
高野英治
久米一平
野田有辉
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

本发明的实施方式提供一种半导体装置的制造方法及半导体装置。所述制造方法是将第1、第2半导体衬底积层，该第1半导体衬底具有包含半导体元件的第1面及位于该第1面的相反侧的第2面，该第2半导体衬底具有包含半导体元件的第3面及位于该第3面的相反侧的第4面。从第2面起进行蚀刻而形成从该第2面到达至第1面的第1接触孔，并且在第2面中的第1区域形成第1槽。形成被覆第1槽的第1掩模材料。将第1掩模材料用作掩模，在第1接触孔内形成第1金属电极。在去除第1掩模材料之后，将第1区域切断。

Description

半导体装置的制造方法及半导体装置
[相关申请]
本申请享有以日本专利申请2017-56174号(申请日：2017年3月22日)为基础申请的优先权。本申请是通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置的制造方法及半导体装置。
背景技术
开发有通过将多个半导体芯片积层，来减少半导体装置整体的占有面积的技术。被积层的半导体芯片彼此是通过被称为TSV(Through-Silicon Via，硅穿孔)的贯通金属而电连接。
这种半导体装置以往是通过如下方法制造，也就是在通过切割而由半导体晶片单片化为半导体芯片之后，将多个半导体芯片积层。另一方面，考虑有在将多个半导体晶片积层之后一起进行切割。但是，如果对积层的多个半导体晶片同时进行切割，则存在积层内部的电路等易因碎片或龟裂等而受到损伤的问题。
发明内容
本发明的实施方式提供一种能够一边抑制半导体晶片的损伤，一边在将多个半导体晶片积层之后一起进行单片化的半导体装置的制造方法及半导体装置。
本实施方式的半导体装置的制造方法是将第1半导体衬底与第2半导体衬底积层，该第1半导体衬底具有包含半导体元件的第1面及位于该第1面的相反侧的第2面，该第2半导体衬底具有包含半导体元件的第3面及位于该第3面的相反侧的第4面。从第 1半导体衬底的第2面起进行蚀刻而形成从该第2面到达至第1面的第1接触孔，并且在第1半导体衬底的第2面中的第1区域形成第1槽。形成被覆第1槽的第1掩模材料。将第1掩模材料用作掩模而在第1接触孔内形成第1金属电极。在去除第1掩模材料之后，将第1半导体衬底的第1区域切断。
附图说明
图1(A)及(B)、图2(A)及(B)、图3(A)及(B)、图4(A)及(B)、图5(A)及(B)、图6(A) 及(B)、图7(A)及(B)、图8是表示第1实施方式的半导体装置的制造方法之一例的剖视图。
图9(A)～(D)是表示第1槽TRb的布局的示例的俯视图。
图10(A)～(D)是表示第2实施方式的半导体装置的制造方法的一例的剖视图。
图11(A)～(F)是表示第3实施方式的半导体装置的制造方法的一例的剖视图。
图12(A)及(B)、图13(A)及(B)、图14(A)及(B)、图15(A)及(B)、图16、图17、图 18是表示第4实施方式的半导体装置的制造方法的一例的剖视图。
图19是表示第1实施方式的变化例的半导体装置的制造方法的一例的剖视图。
具体实施方式
以下，参照附图，对本发明的实施方式进行说明。本实施方式并非限定本发明。在以下的实施方式中，半导体衬底的上下方向是表示在将供设置半导体元件的正面或其相反侧的背面设为上的情况下的相对方向，有时与按照重力加速度的上下方向不同。
(第1实施方式)
图1(A)～图8是表示第1实施方式的半导体装置的制造方法的一例的剖视图。在图1(A)～图8中，表示衬底10a及10b的部分截面。在第1实施方式中，在半导体衬底10a 及10b这两个衬底上形成作为金属电极的TSV，并且在半导体衬底10a上积层半导体衬底10b。半导体衬底10a及10b例如可为具备NAND(Not-And，与非)型 EEPROM(Electrically Erasableand Programmable Read-Only Memory，电可擦除只读存储器)等的半导体衬底。半导体衬底10a及10b为切割前的晶片状态，尚未被单片化为半导体芯片。
首先，在作为第2半导体衬底的半导体衬底10a的第3面F1a上，形成未图示的 STI(Shallow Trench Isolation，浅沟槽隔离)，而规定为主动区(active area)。半导体衬底10a例如为硅衬底。STI例如为硅氧化膜。接下来，在主动区形成半导体元件(未图示)。半导体元件例如可为存储单元阵列、晶体管、电阻元件、电容器元件等。在形成半导体元件时，在主动区或STI上，介隔层间绝缘膜而形成例如配线构造20a。半导体元件及配线构造20a由绝缘膜25a被覆。接下来，以连接于配线构造20a的方式形成焊垫30a。因此，在主动区或STI上，形成作为导电体的配线构造20a及焊垫30a。配线构造20a 及焊垫30a使用钨或钛等低电阻金属。以下，也将配线构造20a及焊垫30a统一称为导电体20a、30a。
于在半导体衬底10a的第3面F1a形成半导体元件等之后，半导体衬底10a从与第 3面F1a为相反侧的第4面F2a被研磨，例如被薄膜化成约30μm以下。由此，可获得图1(A)所示的构造。此外，在图1(A)中，表示为第3面F1a朝下。
如图1(B)所示，使用光刻技术，在第4面F2a上形成抗蚀剂膜PR。抗蚀剂膜PR被覆第4面F2a中除了被用于TSV的接触孔的形成区域以外的区域。
接下来，如图2(A)所示，将抗蚀剂膜PR用作掩模，利用RIE(Reactive IonEtching，反应性离子蚀刻)法从第4面F2a对衬底10a进行蚀刻。由此，形成从第4面F2a到达至第3面F1a的接触孔(第2接触孔)CHa。为了将TSV连接于导电体20a、30a，接触孔 CHa形成于存在导电体20a、30a的区域。由此，在接触孔CHa的底部，导电体20a露出。
在去除抗蚀剂膜PR之后，如图2(B)所示那样，使用CVD(Chemical VaporDeposition，化学气相沉积)法或ALD(Atomic Layer Deposition，原子层沉积)法，在接触孔CHa的内侧面、底面及半导体衬底10a的第4面F2a上形成间隔膜40a。间隔膜40a例如使用硅氧化膜等绝缘膜。
接下来，如图3(A)所示，通过利用RIE法对间隔膜40a进行回蚀，而对接触孔CHa 的底部的间隔膜40a进行蚀刻。由于接触孔CHa的纵横比大，所以间隔膜40a在第4面 F2a上相对较厚地形成，在接触孔CHa的底部基本不形成。因此，通过对间隔膜40a进行回蚀，而接触孔CHa贯通间隔膜40a，到达至导电体20a、30a。也就是说，接触孔 CHa延长至导电体20a、30a。
接下来，如图3(B)所示，在接触孔CHa内形成障壁金属50a。障壁金属50a例如使用Ti或Cu等。
接下来，如图4(A)所示，在接触孔CHa内沉积作为金属电极的TSV60a的金属材料。TSV60a例如使用Cu等金属材料。由此，能够使TSV60a及障壁金属50a连接于导电体 20a、30a。
接下来，如图4(A)所示，使用CMP(Chemical Mechanical Polishing，化学机械抛光) 法，对TSV60a进行平坦化，在保留接触孔CHa内的TSV60a及障壁金属50a的状态下，将位于第4面F2a上的TSV60a及障壁金属50a去除。由此，TSV60a及障壁金属50a 在相邻的接触孔CHa间电绝缘。
接下来，如图4(B)所示，将半导体衬底10b积层于半导体衬底10a的第4面F2a上。作为第1半导体衬底的半导体衬底10b具有与图1(A)的半导体衬底10a大致相同的构成。因此，在半导体衬底10b的第1面F1b上，形成未图示的STI，在主动区形成半导体元件等(未图示)。在主动区或STI上，介隔层间绝缘膜而形成例如配线构造20b。半导体元件及配线构造20b由绝缘膜25b被覆。焊垫30b是以连接于配线构造20b的方式形成。因此，在主动区或STI上，形成作为导电体的配线构造20b及焊垫30b。以下，也将配线构造20b及焊垫30b统一称为导电体20b、30b。
于在半导体衬底10b的第1面F1b形成半导体元件等之后，半导体衬底10b从与第 1面F1b为相反侧的第2面F2b被研磨，例如被薄膜化成约30μm以下。由此，形成具有与半导体衬底10a相同构成的半导体衬底10b。
半导体衬底10b是使第1面F1b朝向半导体衬底10a的第4面F2a而积层于半导体衬底10a上。在积层之后，半导体衬底10a及10b通过热压接而粘接。此时，半导体衬底10b的焊垫30b与半导体衬底10a的TSV60a接触，而半导体衬底10a与10b电连接。
接下来，如图5(A)所示，使用光刻技术，在第2面F2b上形成抗蚀剂膜PR。抗蚀剂膜PR被覆除了接触孔的形成区域Rch及切割区域Rdc以外的区域。接触孔的形成区域Rch是半导体衬底10b的第2面F2b中形成被用于TSV的接触孔的区域。切割区域 Rdc是在使积层的半导体衬底10a及10b变成个别的半导体芯片时被切断的区域。
接下来，如图5(B)所示，将抗蚀剂膜PR用作掩模，利用RIE法从第2面F2b对半导体衬底10b进行蚀刻。由此，形成接触孔CHb作为从第2面F2b到达至第1面F1b 的第1接触孔。为了将TSV连接于导电体20b、30b，接触孔CHb形成于存在导电体20b、 30b的区域。由此，在接触孔CHb的底部，导电体20b露出。另外，在第2面F2b中作为第1区域的切割区域Rdc，形成第1槽TRb。
由于第1槽TRb的开口部的面积比接触孔CHb的开口部的面积宽，所以形成为比接触孔CHb深。由于切割区域Rdc是通过切割而被切断的区域，所以第1槽TRb也可以形成为比接触孔CHb深。更确切地，由于在接下来的切割步骤中，切割机DC容易将半导体衬底10a及10b切断，所以第1槽TRb优选为较深地形成。另一方面，由于半导体衬底10a及10b非常薄，所以如果第1槽TRb过深，则有在切割步骤之前意外地发生龟裂等担忧。因此，第1槽TRb可以某种程度上形成为较浅、或者也可以形成于切割区域Rdc的一部分而非整体。关于第1槽TRb的平面布局，在下文中，参照图9(A)～图 9(D)进行说明。
在去除抗蚀剂膜PR之后，如参照图2(B)～图3(B)所说明那样，形成间隔膜40b(第1绝缘膜)及障壁金属50b。由此，如图6(B)所示，在接触孔CHb的内侧面、第1槽TRb 的内侧面及底面、以及半导体衬底10b的第2面F2b上形成间隔膜40b及障壁金属50b。间隔膜40b及障壁金属50b的材料可分别与间隔膜40a及障壁金属50a的材料相同。
由于位于接触孔CHb及第1槽TRb的底面的间隔膜40b被利用RIE法回蚀，所以在接触孔CHb的底面，无间隔膜40b。作为第1绝缘膜的间隔膜40b位于接触孔CHb 及第1槽TRb的各内侧面。另一方面，障壁金属50b设置于接触孔CHb及第1槽TR 的底面。由此，在接触孔CHb内，障壁金属50b保持与衬底10b电绝缘的状态电连接于导电体20b、30b。
接下来，如图6(B)所示，使用光刻技术，利用作为第1掩模材料的抗蚀剂膜PR被覆接触孔CHb及其周边以外的区域。此时，抗蚀剂膜PR也形成在第1槽TRb上，被覆第1槽TRb。
接下来，将抗蚀剂膜PR用作掩模，在接触孔CHb内沉积作为第1金属电极的TSV60b。TSV60b的材料可与TSV60a的材料相同。由此，可使TSV60b电连接于导电体20b、30b。
接下来，将图6(B)的抗蚀剂膜PR直接用作掩模，利用镀覆法在TSV60b上形成凸块70b。凸块70b例如可使用锡或铜等可镀覆的金属材料。去除抗蚀剂膜PR之后，可获得图7(A)所示的构造。
接下来，如图7(B)所示，将凸块70b及TSV60b用作掩模，通过湿式蚀刻对障壁金属50b进行蚀刻。由此，第2面F2b上的障壁金属50b及第1槽TRb的内表面的障壁金属50b被去除。因此，相邻的TSV60b及凸块70b被相互电分离。另一方面，由于位于凸块70b及TSV60b的正下方的障壁金属50b被保留，所以各TSV60b及凸块70b维持电连接于位于其下的导电体20b、30b的状态。
然后，如图8所示，衬底10a及10b在积层的状态下被切割。此时，切割机DC将图5(A)所示的第1槽TRb内的切割区域Rdc的衬底10a及/或10b切断。由此，积层的衬底10a及10b被单片化为积层的半导体芯片。积层的半导体芯片利用树脂等封装，而作为产品完成。
根据本实施方式，在切割步骤中，由于切割机DC在第1槽TRb内进行切断，所以即便同时切割积层的多个衬底10a及10b，也不易产生碎片或龟裂等。因此，可抑制形成于衬底10a及10b的半导体元件等损伤。也就是说，即便在将多个半导体晶片积层后一起进行单片化，也能够抑制半导体晶片的元件损伤。
另外，根据本实施方式，由于切割机DC在第1槽TRb内进行切断，所以在第1槽 TRb的内侧壁保留了间隔膜40b。因此，在单片化为半导体芯片之后，衬底10b的侧面由间隔膜40b被覆。由此，可保护衬底10b不受金属污染等。另外，如果第1槽TRb 形成得深，并将间隔膜40b设置于衬底10a及10b的侧面，则可保护衬底10a及10b不受金属污染等。
图8是表示第1实施方式的半导体装置的构成例的剖视图。利用所述实施方式的制造方法而形成的半导体装置具有如图8所示那样的构成。
半导体装置1具备衬底10a、衬底10b、配线构造20a、20b、绝缘膜25a、25b、焊垫30a、30b、间隔膜40a、40b、障壁金属50a、50b、TSV60a、60b及凸块70b。
作为第2半导体衬底的衬底10a具有包含半导体元件的第3面F1a及位于该第3面F1a的相反侧的第4面F2a。半导体元件设置于衬底10a的主动区。配线构造20a介隔层间绝缘膜而设置于衬底10a的第3面F1a上的主动区或STI上。半导体元件及配线构造20a由绝缘膜25a被覆。焊垫30a是以连接于配线构造20a的方式设置。因此，在主动区或STI上，设置有作为导电体的配线构造20a及焊垫30a。
作为金属电极的TSV60a是以在衬底10a的第4面F2a与第3面F1a之间贯通衬底 10a的方式设置。TSV60a将导电体20a、30a与衬底10b的焊垫30b之间电连接。
间隔膜40a及障壁金属50a设置于衬底10a与TSV60a之间。障壁金属50a抑制TSV60a的金属材料的扩散。间隔膜40a在障壁金属50a与衬底10a之间，将TSV60a与衬底10a之间、及障壁金属50a与衬底10a之间电分离。
作为第1半导体衬底的衬底10b积层于衬底10a的上方。衬底10b具有包含半导体元件的第1面F1b及位于该第1面F1b的相反侧的第2面F2b。半导体元件设置于衬底 10b的主动区。配线构造20b介隔层间绝缘膜而设置于衬底10b的第1面F1b上的主动区或STI上。半导体元件及配线构造20b由绝缘膜25b被覆。焊垫30b是以连接于配线构造20b的方式设置。因此，在主动区或STI上，设置有作为导电体的配线构造20b及焊垫30b。
作为金属电极的TSV60b是以在衬底10b的第2面F2b与第1面F1b之间贯通衬底 10b的方式设置。TSV60b将导电体20b、30b与凸块70b之间电连接。TSV60b还经由导电体20b、30b与衬底10a的TSV60a电连接。
间隔膜40b及障壁金属50b设置于衬底10b与TSV60b之间。障壁金属50b抑制TSV60b的金属材料的扩散。间隔膜40b在障壁金属50b与衬底10b之间将TSV60b及障壁金属50b与衬底10b电分离。
凸块70b设置于TSV60b上。凸块70b被用于与其它半导体装置等连接的情况。
此处，作为绝缘膜的间隔膜40b设置在位于衬底10b的第1面F1b的外缘与第2面F2b的外缘之间的第1侧面F3b。在切割步骤中，切割机DC在切割区域Rdc的第1槽 TRb内将衬底10a及/或10b切断。因此，位于第1槽TRb的内侧面的间隔膜40b在切割之后仍被保留。由此，如图8所示，间隔膜40b设置于第1侧面F3b。
根据第1槽TRb的深度，间隔膜40b可被覆衬底10b的第1侧面F3b的整体，或者也可被覆衬底10b的第1侧面F3b的一部分。另外，在第1槽TRb到达至衬底10a的情况下，间隔膜40b也可被覆衬底10a的侧面F3a的全部或一部分。
像这样，通过间隔膜40b被覆衬底10b的第1侧面F3b的全体或一部分、或者衬底10a的侧面F3a的全部或一部分，能够抑制衬底10a及10b的金属污染等。
在所述实施方式中，对两片衬底10a及10b进行了说明，但积层的衬底的数量也可为3片以上。在该情况下，例如，只要将与衬底10a相同的衬底积层n(n为2以上的整数)片，并在其最上段的衬底上积层衬底10b即可。第1槽TRb的深度也可到达至位于衬底10b之下的多个衬底10a。
接下来，对第1槽TRb的平面布局进行说明。
图9(A)～图9(D)是表示第1槽TRb的布局的示例的俯视图。利用虚线表示的区域是切割区域Rdc。这些图表示衬底10a及10b的表面的一部分。利用实线框表示的区域是第1槽TRb。切割区域Rdc在第2面F2b上的x方向及直交于x方向的y方向上延伸。 x方向与y方向的交点的角部分成为半导体芯片的角部分。
在图9(A)中，在切割区域Rdc的全体设置着第1槽TRb。在该情况下，在切割步骤中，切割机可容易地将衬底10a及10b切断。另一方面，在切割之前，由于衬底10a及 10b的切割区域Rdc的机械强度降低，所以在搬送衬底10a及10b时等，存在衬底10a 及10b龟裂的情况。因此，第1槽TRb不能形成得太深。
在图9(B)中，在切割区域Rdc的交叉部分设置着第1槽TRb。在除了该交叉部分以外的切割区域Rdc(以下称为中心部分)，未设置第1槽TRb。在切割步骤中，半导体芯片的角部分易受到损伤。因此，通过在切割区域Rdc的交叉部分设置第1槽TRb，能够抑制半导体芯片的损伤。另一方面，在切割区域Rdc的中心部分，由于未设置第1槽 TRb，所以切割前的衬底10a及10b的机械强度不会降低那么多。因此，在图9(B)所示的平面布局中，能够抑制切割步骤中的半导体芯片的损伤，并且在搬送衬底10a及10b 时等能够抑制衬底10a及10b龟裂。在这种平面布局的情况下，第1槽TRb也可以形成为到达至衬底10a。
在图9(C)中，在切割区域Rdc，断续地呈缝线孔状地设置着第1槽TRb。换句话说，在切割区域Rdc，衬底10b呈梯状保留。由此，切割前的衬底10a及10b的机械强度不会降低那么多。因此，在图9(C)所示的平面布局中，能够抑制切割步骤中的半导体芯片的损伤，并且在搬送衬底10a及10b时等能够抑制衬底10a及10b龟裂。因此，即便在图9(C)所示的布局中，第1槽TRb也可以形成为到达至衬底10a。
在图9(D)中，在切割区域Rdc设置着很多比TSV60b小的第1槽TRb。在该情况下，第1槽TRb的开口直径比TSV60b的开口直径小，所以第1槽TRb的深度比TSV60b 的深度浅。因此，切割前的衬底10a及10b的机械强度不会降低那么多。另一方面，由于设置着很多第1槽TRb，所以在切割步骤中容易进行切割，能够抑制半导体芯片损伤。
在第1实施方式中，以衬底10a的第4面F2a与衬底10b的第1面F1b对向的方式，将衬底10a及10b积层。在该情况下，衬底10a的TSV60a中第4面F2a侧的端部被热压接于衬底10b的焊垫30b，因此无需凸块。TSV60a是如图3(B)～图4(A)所示那样利用金属镶嵌法而形成。以下，将TSV60a的制造方法称为“TSV的金属镶嵌形成法”。另一方面，衬底10b的TSV60b中第2面F2b侧的端部与外部的半导体装置等连接，因此在该端部之上形成凸块70b。TSV60b是如图6(B)～图7(B)所示那样使用光刻技术及蚀刻技术而形成。以下，将TSV60b的制造方法称为“TSV的光刻形成法”。
(变化例)
图19是表示变化例的半导体装置的制造方法的剖视图。
在第1实施方式中，在形成图2(A)所示的接触孔CHa时，在半导体衬底10a中与切割区域Rdc对应的部分，未形成槽。也就是说，半导体衬底10a的切割区域未被蚀刻。
但是，也可以如图19所示，在形成接触孔CHa时，在半导体衬底10a的切割区域 Rdc形成第2槽TRa。在该情况下，在形成图2(A)所示的接触孔CHa时，不仅形成接触孔CHa，而且从半导体衬底10a的第4面F2a起进行蚀刻而在半导体衬底10a的切割区域Rdc形成从第4面F2a到达至第3面F1a的第2槽TRa。
接下来，如参照图2(B)所说明那样，使用CVD法或ALD法，形成间隔膜40a。此时，间隔膜40a也被覆第2槽TRa的内表面。接下来，如参照图3(A)所说明那样，利用 RIE法对间隔膜40a进行回蚀。由此，第2槽TRa的底部的间隔膜40a也被蚀刻。接下来，形成被覆第2槽TRa的掩模材料。此时，掩模材料未被覆第1接触孔CHa。将掩模材料用作掩模，在接触孔CHa内形成障壁金属50a及TSV60a。
然后，将掩模材料去除，如参照图4(A)及图4(B)所说明那样，以使半导体衬底10b的第1面F1b朝向半导体衬底10a的第4面F2a上的方式将半导体衬底10b积层于半导体衬底10a上。以与第1实施方式相同的方式对半导体衬底10b进行加工。由此，可获得图19所示的构造。
然后，衬底10a及10b在积层的状态下被切割。此时，切割机DC经由图19所示的第1及第2槽TRb、TRa而将切割区域Rdc的衬底10a及/或10b切断。由此，衬底10a 及10b被单片化为积层的半导体芯片。在本变化例中也能够获得与第1实施方式相同的效果。
此外，积层的半导体衬底的数量并不限定于两片，也可为3片以上。在该情况下，积层于半导体衬底10b之下的多个半导体衬底也可与半导体衬底10a同样地被加工。
(第2实施方式)
图10(A)～图10(D)是表示第2实施方式的半导体装置的制造方法的一例的剖视图。在图10(A)～图10(D)中，表示衬底10a及10b的全体的剖视图。另外，在图10(A)～图 10(D)中，将导电体20a、30a、20b、30b、间隔膜40a、40b、及障壁金属50a、50b等简化地表示或省略。图11(A)以后的附图也一样。
在第2实施方式中，以使衬底10a的第3面F1a与衬底10b的第1面F1b对向的方式，将衬底10a及10b积层。衬底10a的第4面F2a及衬底10b的第2面F2b可与外部的半导体装置等连接。因此，在第2实施方式中，衬底10a及10b各自的TSV60a及60b 可使用“TSV的光刻形成法”而形成。
例如，如图10(A)所示，首先，衬底10a及10b是将衬底10a的第3面F1a与衬底 10b的第1面F1b贴合而积层。
接下来，使用CMP法，对衬底10b从第2面F2b起进行研磨，而将衬底10b薄膜化。然后，使用“TSV的光刻形成法”形成TSV60b。因此，如图10(B)所示，在TSV60b 上形成凸块70b。另外，在切割区域形成第1槽TRb。此外，第1槽TRb的配置存在与图示的配置不同的情况。
接下来，如图10(C)所示，使衬底10a及10b反转，利用粘接剂110将衬底10b粘接在支撑衬底100上。由此，衬底10a的第4面F2a被朝向上方。此时，凸块70b埋藏于粘接剂110而受到保护。
接下来，使用CMP法，对衬底10a从第4面F2a起进行研磨，而将衬底10a薄膜化。然后，使用“TSV的光刻形成法”形成TSV60a。因此，如图10(D)所示，在TSV60a 上形成凸块70a。另外，在切割区域形成第2槽TRa。此外，第2槽TRa的配置也存在与图示的配置不同的情况。TSV60a的形成方法及第2槽TRa的形成方法可分别与 TSV60b及第1槽TRb的形成方法相同。
例如，在第2实施方式中，对衬底10a从第4面F2a起进行蚀刻，第2接触孔以从衬底10a的第4面F2a到达至第3面F1a的方式形成。第2接触孔对应于图5(B)的CHb。与此同时，在衬底10a的第4面F2a中作为第2区域的切割区域形成第2槽TRa。第2 槽TRa对应于图5(B)的TRb。第2槽TRa的位置对应于第1槽TRb的位置，如果将衬底10a及10b的积层方向设为z，则第2槽TRa在z方向上位于第1槽TRb的正上方或正下方。此外，第1及第2槽TRb、TRa的平面布局可为图9(A)～图9(D)中的任一种。
接下来，以被覆第2槽TRa且使第2接触孔露出的方式形成第2掩模材料。第2掩模材料对应于图6(A)所示的抗蚀剂膜PR。将该第2掩模材料用作掩模，在第2接触孔内形成作为第2金属电极的TSV60a。进而，在TSV60a上形成凸块70b。由此，可获得图10(D)所示的构造。
然后，将衬底10a及10b从支撑衬底100及粘接剂110拆卸，并且衬底10a及10b 在第1及第2槽TRb、TRa中被切割。
这样一来，衬底10a及10b也可以使第3面F1a与第1面F1b对向的方式积层。由此，在衬底10a及10b的两者，可形成切割用的第1及第2槽TRb、TRa。因此，在第 2实施方式中，更容易进行切割。另外，第2实施方式能够获得与第1实施方式相同的效果。
(第3实施方式)
图11(A)～图11(D)是表示第3实施方式的半导体装置的制造方法的一例的剖视图。在第3实施方式中，积层有两组第2实施方式中所示的使第3面F1a与第1面F1b对向而积层的衬底10a及10b。也就是说，在第3实施方式中，将4片衬底10a_1、10b_1、衬底10a_2、10b_2积层。
如图11(A)所示，以使衬底10a_1的第3面F1a_1与衬底10b_1的第1面F1b_1对向的方式，将衬底10a_1及10b_1积层。另外，以使衬底10a_2的第3面F1a_2与衬底 10b_2的第1面F1b_2对向的方式，将衬底10a_2及10b_2积层。
另一方面，如图11(B)及图11(C)所示，通过热压接将衬底10b_1的第2面F2b_1与衬底10b_2的第2面F2b_2粘接。因此，在第3实施方式中，衬底10b_1及10b_2各自的TSV60b_1及60b_2是使用“TSV的金属镶嵌形成法”而形成。
衬底10a_1及10a_2各自的TSV60a_1及60a_2能够连接于外部的半导体装置等。因此，衬底10a_1及10a_2各自的TSV60a_1及60a_2是使用“TSV的金属镶嵌形成法”而形成。
例如，如图11(A)所示，首先，衬底10a_1及10b_1是将衬底10a_1的第3面F1a_1 与衬底10b_1的第1面F1b_1贴合而积层。另外，衬底10a_2及10b_2是将衬底10a_2 的第3面F1a_2与衬底10b_2的第1面F1b_2贴合而积层。为了方便起见，将衬底10a_1 及10b_1设为积层体ST1，将衬底10a_2及10b_2称为积层体ST2。
接下来，使用CMP法，从积层体ST1的第2面F2b_1起进行研磨，而将衬底10b_1 薄膜化。另外，从积层体ST2的第2面F2b_2起进行研磨，也将衬底10b_2薄膜化。然后，使用“TSV的金属镶嵌形成法”形成TSV60b_1、60b_2。因此，如图11(B)所示，在 TSV60b_1、60b_2上，未形成凸块70b。另外，在切割区域未形成槽。
接下来，如图11(C)所示，使积层体ST2反转，并积层于积层体ST1上。此时，积层体ST2的第2面F2b_2与积层体ST1的第2面F2b_1以对向的方式被热压接。由此， TSV60b_1与TSV60b_2电连接。
接下来，使用CMP法，从积层体ST2的第4面F2a_2起进行研磨，而将衬底10a_2 薄膜化。然后，使用“TSV的光刻形成法”形成TSV60a_2。因此，如图11(D)所示，在 TSV60a_2上形成凸块70a_2。另外，在切割区域形成第2槽TRa_2。TSV60a_2的形成方法及第2槽TRa_2的形成方法可分别与第2实施方式的TSV60a及第2槽TRa的形成方法相同。
接下来，如图11(E)所示，使积层体ST1、ST2反转，并利用粘接剂110将积层体 ST1、ST2粘接在支撑衬底100上。由此，衬底10a_1的第4面F2a_1朝向上方。此时，凸块70a_2埋藏于粘接剂110而受到保护。
接下来，使用CMP法，从第4面F2a_1起进行研磨，而将衬底10a_1薄膜化。然后，使用“TSV的光刻形成法”形成TSV60a_1。因此，如图11(F)所示，在TSV60a_1上形成凸块70a_1。另外，在切割区域形成第2槽TRa_1。TSV60a_1的形成方法及第2槽 TRa_1的形成方法可分别与第2实施方式的TSV60a及第2槽TRa的形成方法相同。
然后，积层体ST1、TR2在槽TRa_1、TRa_2中被切割。
这样一来，还可将使两片衬底的第1面彼此对向而成的积层体ST1、ST2进一步积层。在第3实施方式中，可在衬底10a_1及10a_2这两个衬底上形成切割用槽TRa_1、 TRa_2。因此，第3实施方式能够获得与第2实施方式相同的效果。
此外，在第3实施方式中，对两组积层体ST1、ST2进行了说明，但积层的积层体的数量也可为3片以上。在该情况下，例如，只要积层n(n为2以上的整数)组两面均由金属镶嵌形成法形成的积层体，且将其最上段及最下段的积层体设为ST1、ST2即可。槽TRa_1、TRa_2的深度可从最上段或最下段起形成至任意深度。
(第4实施方式)
图12(A)～图18是表示第4实施方式的半导体装置的制造方法的一例的剖视图。第4实施方式与第1实施方式的不同点是，在将衬底10a及10b积层之后，一次形成TSV60 及第1槽TR。
首先，与第1实施方式同样地形成衬底10a及10b，并分别将衬底10a及10b薄膜化。
接下来，如图12(A)所示，利用热压接将衬底10a及10b积层。在第4实施方式中，以衬底10a的第4面F2a与衬底10b的第1面F1b对向的方式将衬底10a及10b积层。
如图12(B)所示，使用光刻技术，在第2面F2b上形成抗蚀剂膜PR。抗蚀剂膜PR 被覆第2面F2b中除了TSV用接触孔的形成区域及第1槽的形成区域以外的区域。
接下来，如图13(A)所示，将抗蚀剂膜PR用作掩模，从第2面F2b起利用RIE法对衬底10a及10b进行蚀刻。由此，形成从第2面F2b到达至第3面F1a的接触孔(第1 接触孔)CH。与此同时，在第2面F2b中作为第1区域的切割区域Rdc形成第1槽TR。另外，如图13(B)所示，对焊垫30b朝横向(相对于衬底10a及10b的积层方向大致垂直的方向)进行蚀刻。由此，焊垫30b比衬底10a及10b的侧面更朝横向凹陷。此外，第1 槽TR的平面布局可为图9(A)～图9(D)中的任一种。
接下来，如图14(A)所示，在接触孔CH的内侧面、第1槽TR的内侧面及底面、以及半导体衬底10b的第2面F2b上形成间隔膜40(第1绝缘膜)。此处，焊垫30b在接触孔CH内，从衬底10a及10b的侧面朝横向凹陷。进而，接触孔CH的纵横比高。因此，如图14(B)所示，间隔膜40不易附着于焊垫30b的表面。因此，间隔膜40基本不附着于焊垫30b的表面、或者即便形成也非常薄。间隔膜40b及障壁金属50b的材料可分别与间隔膜40a及障壁金属50a的材料相同。
接下来，通过对间隔膜40利用RIE法进行回蚀，而对接触孔CH的底部的间隔膜 40进行蚀刻。此时，附着于焊垫30b的表面的间隔膜40也被去除。
接下来，如图15(A)所示，在接触孔CH内形成障壁金属50。如图15(B)所示，障壁金属50与间隔膜40同样地基本不附着于焊垫30b的表面、或者形成得非常薄。
接下来，如图16所示，使用光刻技术，而利用抗蚀剂膜PR被覆接触孔CH及其周边以外的区域。此时，抗蚀剂膜PR也形成于第1槽TR上，而被覆第1槽TR。
接下来，将抗蚀剂膜PR用作掩模，在接触孔CH内沉积TSV60。TSV60也进入到焊垫30b的凹处，从而也电连接于焊垫30b。由此，可使TSV60电连接于导电体20b、 30b、20a、30a。
接下来，将抗蚀剂膜PR直接用作掩模，利用镀覆法在TSV60上形成凸块70。在去除抗蚀剂膜PR之后，将凸块70及TSV60的上部用作掩模，通过湿式蚀刻对障壁金属 50进行蚀刻。由此，如图17所示那样第2面F2b上及第1槽TR的内侧面及底面的障壁金属50被去除，因此相邻的TSV60及凸块70被相互电分离。另一方面，由于位于凸块70及TSV60的正下方的障壁金属50被保留，所以各TSV60及凸块70维持电连接于位于其下的导电体20b、30b、20a、30a的状态。
然后，将衬底10a及10b在积层状态下进行切割。此时，切割机DC将第1槽TR 内的衬底10a、10b切断。由此，如图18所示，积层的衬底10a及10b被单片化为积层的半导体芯片。积层的半导体芯片是利用树脂等封装，而作为产品完成。
根据第4实施方式，在切割步骤中，由于切割机DC在第1槽TR内进行切断，所以即便对积层的多个衬底10a及10b同时进行切割，也不易发生碎片或龟裂等。因此，第4实施方式能够获得与第1实施方式相同的效果。
另外，在第1槽TR的内侧壁保留了间隔膜40。因此，在单片化为半导体芯片之后，衬底10b及10a的侧面被间隔膜40被覆。由此，能够保护衬底10b及10a不受金属污染等。
此外，在第4实施方式中，对两片衬底10a及10b进行了说明，但积层的衬底的数量也可为3片以上。在该情况下，例如，只要积层n(n为2以上的整数)片相同的衬底，并从其最上段的衬底起形成第1槽TR即可。第1槽TR的深度可为从最上段的衬底至最下段的衬底为止的任意位置。
对本发明的若干个实施方式进行了说明，但这些实施方式是作为示例而提出的，并不意图限定发明的范围。这些实施方式能以其它各种方式实施，可在不脱离发明的主旨的范围内，进行各种省略、替换及变更。这些实施方式或其变化包含在发明的范围或主旨内，同样地包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
10a、10b 衬底
20a、20b 配线构造
30a、30b 焊垫
25a、25b 绝缘膜
CHa、CHb 接触孔
40a、40b 间隔膜
50a、50b 障壁金属
60a、60b TSV
70a、70b 凸块
TRa、TRb 槽
Rdc 切割区域

Claims (4)

1.一种半导体装置的制造方法，其特征在于包括：
将第1半导体衬底与第2半导体衬底积层，该第1半导体衬底具有包含半导体元件的第1面及位于该第1面的相反侧的第2面，该第2半导体衬底具有包含半导体元件的第3面及位于该第3面的相反侧的第4面；
从所述第1半导体衬底之所述第2面起进行蚀刻，而形成从该第2面到达至所述第1面的第1接触孔，并且在所述第1半导体衬底的所述第2面中的第1区域形成第1槽；
形成被覆所述第1槽的第1掩模材料；
将所述第1掩模材料用作掩模，在所述第1接触孔内形成第1金属电极；及
在去除所述第1掩模材料之后，将所述第1半导体衬底的所述第1区域切断。
2.根据权利要求1所述的半导体装置的制造方法，其特征在于：
所述第1及第2半导体衬底是将所述第1半导体衬底的所述第1面与所述第2半导体衬底的所述第3面贴合而积层，
在去除所述第1掩模材料之后，还包括：
从所述第2半导体衬底的所述第4面起进行蚀刻，而形成从所述第2半导体衬底的所述第4面到达至所述第3面的第2接触孔，并且在所述第2半导体衬底的所述第4面中的第2区域形成第2槽；
形成被覆所述第2槽的第2掩模材料；及
将所述第2掩模材料用作掩模而在所述第2接触孔内形成第2金属电极；且
在去除所述第2掩模材料之后，将所述第1及第2半导体衬底的所述第1及第2区域切断。
3.根据权利要求1所述的半导体装置的制造方法，其特征在于：
在将所述第1及第2半导体衬底积层之前，还包括：
从所述第2半导体衬底的所述第4面起进行蚀刻，而形成从该第4面到达至所述第3面之第2接触孔，并且在所述第2半导体衬底的所述第4面中的第2区域形成第2槽；
形成被覆所述第2槽的第1掩模材料；
将所述第1掩模材料用作掩模，在所述第1接触孔内形成第1金属电极；及
在去除所述第1掩模材料之后，将所述第1半导体衬底的所述第1面连接于所述第2半导体衬底的所述第4面上而将所述第1及第2半导体衬底积层。
4.根据权利要求1所述的半导体装置的制造方法，其特征在于：
所述第1接触孔是从所述第1半导体衬底的所述第2面起进行蚀刻而从该第1半导体衬底的所述第2面到达至所述第2半导体衬底之所述第3面，且所述第1槽形成于所述第1半导体衬底的所述第2面中的所述第1区域。
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