TW201824545A - 高壓半導體裝置 - Google Patents

高壓半導體裝置 Download PDF

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Publication number
TW201824545A
TW201824545A TW105144152A TW105144152A TW201824545A TW 201824545 A TW201824545 A TW 201824545A TW 105144152 A TW105144152 A TW 105144152A TW 105144152 A TW105144152 A TW 105144152A TW 201824545 A TW201824545 A TW 201824545A
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region
doped
conductive type
conductivity type
regions
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TW105144152A
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TWI609486B (zh
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牧 伊
陳柏安
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新唐科技股份有限公司
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Priority to TW105144152A priority Critical patent/TWI609486B/zh
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Publication of TWI609486B publication Critical patent/TWI609486B/zh
Priority to CN201711471935.8A priority patent/CN108269851B/zh
Priority to US15/858,792 priority patent/US10529849B2/en
Publication of TW201824545A publication Critical patent/TW201824545A/zh

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Abstract

本發明實施例提供一種高壓半導體裝置。高壓半導體裝置包括位於基板結構上的閘極結構。位於基板結構內的汲極摻雜區。超接面摻雜結構，位於基板結構內，且接近汲極摻雜區。超接面摻雜結構包括複數個第一導電類型摻雜次區，第一導電類型摻雜次區沿第一方向延伸且沿第二方向設置。複數個第二導電類型摻雜次區，沿第一方向延伸且沿第二方向與第一摻雜部分交錯設置。第一導電類型摻雜次區各別沿第二方向的寬度沿第二方向呈線性遞減，和第二導電類型摻雜次區各別沿第二方向的寬度沿第二方向呈線性遞減。

Description

高壓半導體裝置
本發明實施例係有關於一種半導體裝置，特別是有關於一種高壓半導體裝置。
高壓積體電路(HVIC)因具有符合成本效益且易相容於其它製程等優點，因而已廣泛應用於發光二極體(LED)、顯示器驅動積體電路元件、電源供應器、電力管理、通訊、車用電子的電源控制系統中。然而，習知的高壓積體電路會因為閉鎖效應(latch up)、低擊穿電壓、低元件切換速度及較大的元件面積等問題而無法進一步的改善。
因此，在此技術領域中，有需要一種高壓半導體裝置，以改善上述缺點。
本發明之一實施例係提供一種高壓半導體裝置。上述高壓半導體裝置包括一基板結構；一閘極結構，位於上述基板結構上；一汲極摻雜區，位於上述基板結構內，且接近上述閘極結構的一第一側；以及一超接面摻雜結構，位於上述基板結構內，且接近上述汲極摻雜區，其中上述超接面摻雜結構包括：複數個第一導電類型摻雜次區，具有一第一導電類型，上述些第一導電類型摻雜次區沿一第一方向延伸且沿一第二 方向設置；以及複數個第二導電類型摻雜次區，具有相反於上述第一導電類型的一第二導電類型，上述些第二導電類型摻雜次區沿上述第一方向延伸且沿上述第二方向與上述些第一摻雜部分交錯設置，其中上述些第一導電類型摻雜次區各別沿上述第二方向的寬度沿上述第二方向呈線性遞減，和其中上述些第二導電類型摻雜次區各別沿上述第二方向的寬度沿上述第二方向呈線性遞減。
本發明之另一實施例係提供一種高壓半導體裝置。上述高壓半導體裝置包括一基板結構；一閘極結構，位於上述基板結構上；一汲極摻雜區，位於上述基板結構內，且接近上述閘極結構的一第一側；以及一超接面摻雜結構，位於上述基板結構內，且接近上述汲極摻雜區，其中上述超接面摻雜結構包括：複數個第一導電類型摻雜次區，具有一第一導電類型，上述些第一導電類型摻雜次區沿一第一方向延伸且沿一第二方向設置；以及複數個第二導電類型摻雜次區，具有相反於上述第一導電類型的一第二導電類型，上述些第二導電類型摻雜次區沿上述第一方向延伸且沿上述第二方向與上述些第一摻雜部分交錯設置，其中上述些第一導電類型摻雜次區各別沿上述第一方向的深度、沿上述第二方向的寬度和摻質濃度的至少一個沿上述第二方向呈線性遞減。
本發明之又一實施例係提供一種高壓半導體裝置。上述高壓半導體裝置包括一基板結構；一閘極結構，位於上述基板結構上；一汲極摻雜區，位於上述基板結構內，且接近上述閘極結構的一第一側；以及一超接面摻雜結構，位於上述基 板結構內，且接近上述汲極摻雜區，其中上述超接面摻雜結構包括：彼此相鄰的一第一導電類型摻雜次區和一第二導電類型摻雜次區，上述第一導電類型摻雜次區具有一第一導電類型，上述第二導電類型摻雜次區具有相反於上述第一導電類型的一第二導電類型，其中上述第一導電類型摻雜次區和上述第二導電類型摻雜次區沿一第一方向延伸且沿一第二方向設置，其中上述第一導電類型摻雜次區和上述第二導電類型摻雜次區沿上述第一方向的深度、沿上述第二方向的寬度和摻質濃度的至少一個沿上述第二方向彼此不同。
500a、500b‧‧‧高壓半導體裝置
102‧‧‧接線區
104‧‧‧源極區
106‧‧‧閘極區
108‧‧‧飄移區
110‧‧‧汲極區
200‧‧‧半導體基板
202‧‧‧低電位區
204‧‧‧電位轉換區
206‧‧‧隔離區
208‧‧‧高電位區
211、221‧‧‧頂面
212‧‧‧第二導電類型埋藏摻雜層
220‧‧‧磊晶層
222‧‧‧高壓第一導電類型井區
223‧‧‧第二導電類型深井區
224‧‧‧高壓第二導電類型井區
225‧‧‧第一導電類型井區
226‧‧‧第一導電類型井區
227‧‧‧第二導電類型緩衝摻雜區
228‧‧‧第二導電類型漂移摻雜區
229‧‧‧第一導電類型場摻雜區
230‧‧‧第一導電類型漂移摻雜區
234‧‧‧第一導電類型接線摻雜區
236‧‧‧第二導電類型接線摻雜區
238‧‧‧第二導電類型漂移摻雜區
240‧‧‧隔絕結構
290、292、490、492‧‧‧遮罩圖案
290a、290b、290c、290d、292a、292b、292c、292d、490a、490b、490c、492a、492b、492c‧‧‧開口
Wa、Wb、Wc、Wd、W1、W2、W3‧‧‧寛度
250‧‧‧閘極結構
256‧‧‧第一方向
252‧‧‧第二方向
260‧‧‧交界處
270‧‧‧橫向擴散金屬氧化物半導體
284、484‧‧‧超接面摻雜結構
280a、280b、280c、280d、480a、480b、480c‧‧‧第一導電類型摻雜次區
282a、282b、282c、282d、482a、482b、482c‧‧‧第二導電類型摻雜次區
300‧‧‧基板結構
S‧‧‧源極
D‧‧‧汲極
第1圖顯示本發明一些實施例之高壓半導體裝置之剖面示意圖。
第2A、2B圖為顯示形成於飄移區中的超接面摻雜結構的的部分製程步驟。
第3圖顯示本發明一些實施例之高壓半導體裝置之剖面示意圖。
第4A、4B圖為顯示形成隔離區中的超接面摻雜結構的的部分製程步驟。
為了讓本發明之目的、特徵、及優點能更明顯易懂，下文特舉實施例，並配合所附圖示，做詳細之說明。本發明說明書提供不同的實施例來說明本發明不同實施方式的技 術特徵。其中，實施例中的各元件之配置係為說明之用，並非用以限制本發明。且實施例中圖式標號之部分重複，係為了簡化說明，並非意指不同實施例之間的關聯性。
本發明實施例係提供用於超高壓橫向擴散金屬氧化物半導體(ultra high-voltage laterally diffused metal oxide semiconductor，以下簡稱UHV LDMOS)元件或高壓積體電路(HVIC)元件的一種高壓半導體裝置。上述高壓半導體裝置包括一超接面摻雜結構(super junction doped structure)。上述超接面摻雜結構的寬度、深度和摻質濃度的至少一個沿一方向呈線性遞減，以構成一減低表面電場結構(reduced surface field，RESURF)。因此，超接面摻雜結構可有效降低高壓半導體裝置的表面電場，並且可使高壓半導體裝置達到高崩潰電壓(breakdown voltage，BVD)的效果。
第1圖顯示本發明一些實施例之高壓半導體裝置500a之剖面示意圖。在本實施例中，高壓半導體裝置500a可為一超高壓橫向擴散金屬氧化物半導體(ultra high-voltage laterally diffused metal oxide semiconductor，以下簡稱UHV LDMOS)元件。高壓半導體裝置500a的主要元件可包括一基板結構300、一閘極結構250、一源極摻雜區、一超接面摻雜結構284和一汲極摻雜區和一接線摻雜區。
如第1圖所示，上述基板結構300包括一半導體基板200和全面性形成於半導體基板200的頂面211上的一磊晶層220。上述半導體基板200係摻雜摻質以具有第一導電類型。舉例來說，當第一導電類型為P型時，上述半導體基板200可為一 P型基板。在本發明一些實施例中，半導體基板200的摻雜濃度可為約1 x 1011-1 x 1015/cm3，因而半導體基板200可視為一輕摻雜P型半導體基板200。此處的「輕摻雜」意指摻雜濃度小於1 x 1015/cm3。在本發明一些實施例中，上述半導體基板200可為矽基板。在本發明其他實施例中，可利用鍺化矽(SiGe)、塊狀半導體(bulk semiconductor)、應變半導體(strained semiconductor)、化合物半導體(compound semiconductor)，或其他常用之半導體基板做為半導體基板200。上述磊晶層220的材質可包括矽、鍺、矽與鍺、III-V族化合物或上述之組合。上述磊晶層220具有第二導電類型，且第二導電類型不同於第一導電類型。舉例來說，當第一導電類型為P型時，上述第二導電類型為N型，且磊晶層220可視為一N型磊晶層220。在本發明一些實施例中，磊晶層220可具有例如磷(P)之摻質。
如第1圖所示，基板結構300包括一接線區(pick-up region)102、一源極區(source region)104、一閘極區(gate region)106、一飄移區(drift region)108和一汲極區(drain region)110，沿平行於磊晶層220的頂面211的一方向(例如第二方向252)由左至右依序配置。
如第1圖所示，上述高壓半導體裝置500a包括複數個隔絕結構240，設置於磊晶層220的頂面221上，以定義出接線區102、源極區104、閘極區106和汲極區110中的多個主動區域，且覆蓋飄移區108。舉例來說，隔絕結構240定義出上述閘極結構250、源極摻雜區、汲極摻雜區以及接線摻雜區的形成位置。在本發明一些實施例中，上述隔絕結構240可包括局部 氧化物(Local Oxidation of Silicon，LOCOS)或淺溝槽隔絕物(Shallow Trench Isolation，STI)。
如第1圖所示，高壓半導體裝置500a包括一高壓第一導電類型井區222、一高壓第二導電類型井區224和一第二導電類型深井區223，設置於磊晶層220內。高壓第一導電類型井區222位於接線區102中、高壓第二導電類型井區224位於源極區104中，而第二導電類型深井區223位於飄移區108和汲極區110中。舉例來說，當第一導電類型為P型時，上述第二導電類型為N型，上述高壓第一導電類型井區222可視為高壓P型井區(HVPW)222、上述高壓第二導電類型井區224可視為高壓N型井區(HVNW)224，且上述第二導電類型深井區223可視為N型深井區(DNW)223。在本發明一些實施例中，上述高壓第二導電類型井區224和第二導電類型深井區223的底面可位於磊晶層220內，而高壓第一導電類型井區222的底面可對齊於基板200和磊晶層220的交界處260(位置同基板200的頂面211)。可利用離子植入製程形成高壓第一導電類型井區222、一高壓第二導電類型井區224和一第二導電類型深井區223。
在本發明一些實施例中，高壓半導體裝置500a的接線區102中可包括由下而上依序設置於高壓第一導電類型井區222上的一第一導電類型漂移摻雜區(drift doped region)230、一第一導電類型井區226、一第一導電類型場摻雜區(field doped region)229和一第一導電類型接線摻雜區(pick-up doped region)234。舉例來說，當第一導電類型為P型時，上述第一導電類型漂移摻雜區230可視為P型漂移摻雜區(P-drift doped region)230，上述第一導電類型井區226可視為P型井區226，上述第一導電類型場摻雜區229可視為P型場摻雜區(P-field doped region)229，而上述第一導電類型接線摻雜區234可視為P型接線摻雜區234。
在本發明一些實施例中，上述第一導電類型接線摻雜區234的摻雜濃度大於第一導電類型場摻雜區229的摻雜濃度，第一導電類型場摻雜區229的摻雜濃度大於第一導電類型井區226的摻雜濃度，第一導電類型井區226的摻雜濃度大於P型漂移摻雜區230的摻雜濃度，且P型漂移摻雜區230的摻雜濃度大於高壓第一導電類型井區222的摻雜濃度。可利用不同的離子植入製程分別形成第一導電類型漂移摻雜區230、第一導電類型井區226、第一導電類型場摻雜區229和第一導電類型接線摻雜區234。
如第1圖所示，高壓半導體裝置500a的源極區104中可包括由下而上依序設置於高壓第二導電類型井區224上的一第一導電類型井區225、第一導電類型接線摻雜區234和第二導電類型接線摻雜區236。舉例來說，當第一導電類型為P型時，第二導電類型為N型，上述第一導電類型井區225可視為P型隔絕井區(isolated PW(IPW))225、上述第一導電類型接線摻雜區234可視為P型接線摻雜區234，且上述第二導電類型接線摻雜區236可視為N型接線摻雜區236。並且，源極區104中的第一導電類型井區225、第一導電類型接線摻雜區234和第二導電類型接線摻雜區236一起構成源極摻雜區。
在本發明一些實施例中，上述第一導電類型接線 摻雜區234的摻雜濃度大於第一導電類型井區225的摻雜濃度。上述第二導電類型接線摻雜區236的摻雜濃度大於高壓第二導電類型井區224的摻雜濃度。可利用數道離子植入製程分別形成上述第一導電類型井區225、第一導電類型接線摻雜區234和第二導電類型接線摻雜區236。
如第1圖所示，高壓半導體裝置500a的汲極區110中可包括由下而上依序設置於第二導電類型深井區223上的一第二導電類型漂移摻雜區228、一第二導電類型緩衝摻雜區227和一第二導電類型接線摻雜區236。舉例來說，當第一導電類型為P型時，第二導電類型為N型，上述第二導電類型漂移摻雜區228可視為N型漂移摻雜區(N-drift doped region)228，上述第二導電類型緩衝摻雜區227可視為N型緩衝摻雜區227，且上述第二導電類型接線摻雜區236可視為N型接線摻雜區236。並且，汲極區110中的第二導電類型漂移摻雜區228、第二導電類型緩衝摻雜區227和第二導電類型接線摻雜區236一起構成汲極摻雜區。
在本發明一些實施例中，上述第二導電類型接線摻雜區236的摻雜濃度大於第二導電類型緩衝摻雜區227的摻雜濃度，且第二導電類型緩衝摻雜區227的摻雜濃度的摻雜濃度大於第二導電類型漂移摻雜區228的摻雜濃度。可利用數道離子植入製程分別形成上述第二導電類型漂移摻雜區228、第二導電類型緩衝摻雜區227和第二導電類型接線摻雜區236。
如第1圖所示，上述高壓半導體裝置500的閘極結構250設置於磊晶層220的頂面221上，且位於閘極區106中。高 壓半導體裝置500a的源極摻雜區和汲極摻雜區分別位於閘極結構250的相反側。閘極結構250接近於源極區104的一第一側覆蓋部分高壓第二導電類型井區224，閘極結構250接近於飄移區108的一第二側覆蓋飄移區108中的部分隔絕結構240及其下的第二導電類型深井區223。閘極結構250藉由飄移區108中的隔絕結構240與汲極摻雜區隔開。閘極結構250包括一閘極絕緣材料(圖未顯示)和位於閘極絕緣材料上的一閘極導電材料。可利用例如化學氣相沉積法(CVD)或原子層沉積法(ALD)之一薄膜沉積製程及後續的一圖案化製程形成上述閘極結構250。
接下來利用第1圖說明高壓半導體裝置500a之一超接面摻雜結構284的形成位置。上述超接面摻雜結構284位於飄移區108中的隔絕結構240下方的第二導電類型深井區223內，且與汲極摻雜區隔開一距離。並且，上述超接面摻雜結構284位於閘極結構250與汲極摻雜區之間。在本發明一些實施例中，超接面摻雜結構284包括複數個第一導電類型摻雜次區280a、280b、280c和280d，以及複數個第二導電類型摻雜次區282a、282b、282c和282d。第一導電類型摻雜次區280a、280b、280c和280d具有第一導電類型。第一導電類型摻雜次區280a、280b、280c和280d沿一第一方向256延伸且沿一第二方向252設置。另外，第二導電類型摻雜次區282a、282b、282c和282d具有第二導電類型，沿第一方向256延伸且沿第二方向252與第一導電類型摻雜次區280a、280b、280c和280d交錯設置。
在如第1圖所示的剖面圖中，第一導電類型摻雜次區280a、280b、280c和280d和第二導電類型摻雜次區282a、282b、 282c和282d具有且為沿第一方向256延伸的長條柱狀。值得注意的是，第一方向256實質平行於基板結構300的頂面221的一法線方向，而第二方向252實質平行於閘極結構250朝向汲極摻雜區的一方向。
如第1圖所示，第二導電類型摻雜次區282a的相反兩側分別鄰接兩個第一導電類型摻雜次區280a和280b，第一導電類型摻雜次區280b的相反兩側分別鄰接兩個第二導電類型摻雜次區282a、282b。上述第一導電類型摻雜次區和第二導電類型摻雜次區的鄰接關係可依上述關係類推。然而，在其他實施例中，第一導電類型摻雜次區280a、280b、280c和280d的位置可與第二導電類型摻雜次區282a、282b、282c和282d互換。
舉例來說，當第一導電類型為P型時，第二導電類型為N型，上述第一導電類型摻雜次區280a、280b、280c和280d分別為P型摻雜次區280a、280b、280c和280d，而上述第二導電類型摻雜次區282a、282b、282c和282d分別為N型摻雜次區282a、282b、282c和282d。因此，第一導電類型摻雜次區可與鄰接的第二導電類型摻雜次區形成一PN接面(PN junction)。舉例來說，第一導電類型摻雜次區280a和鄰接的第二導電類型摻雜次區282a可形成一PN接面，第一導電類型摻雜次區280b可與兩個鄰接的第二導電類型摻雜次區282a、282b分別形成兩個PN接面。超接面摻雜結構284之其他PN接面的形成位置可由上述第一導電類型摻雜次區和第二導電類型摻雜次區的鄰接關係類推。
在本發明一些實施例中，在超接面摻雜結構284中， 可設計第一導電類型摻雜次區280a、280b、280c和280d沿第一方向256的深度、沿第二方向252的寬度和摻質濃度的至少一個沿第二方向252呈線性遞減。類似地，第二導電類型摻雜次區282a、282b、282c和282d沿第一方向256的深度、沿第二方向252的寬度和摻質濃度的至少一個沿第二方向252呈線性遞減。在第1圖所示之實施例中，第一導電類型摻雜次區280a、280b、280c和280d各別的寬度Wa、Wb、Wc、Wd沿第二方向252呈線性遞減，且第二導電類型摻雜次區282a、282b、282c和282d各別的寬度Wa、Wb、Wc、Wd沿第二方向252呈線性遞減。
接下來利用第2A、2B圖說明第1圖所示實施例之超接面摻雜結構284的形成方式。第2A、2B圖為第1圖所示之半導體裝置的飄移區108的局部放大圖，並顯示形成飄移區108中的超接面摻雜結構284的部分製程步驟。上述製程於形成第1圖所示的隔絕結構240之前進行，因而隔絕結構240在此不予顯示。
如第2A圖所示，可進行一微影製程，於飄移區108中的磊晶層220的頂面221上形成一遮罩圖案290。上述遮罩圖案290可具有複數個開口290a~290d，暴露出飄移區108中的部分第二導電類型深井區223。其中，為清楚繪示起見，此處是以4個開口(開口290a~290d)來舉例，但不以此為限，在其他實施例中，也可視需要設置開口的數目。在第2A圖所示的一些實施例中，遮罩圖案290的開口290a係設置位於接近閘極結構250，且從閘極結構250朝汲極摻雜區(由第二導電類型漂移摻雜區228、第二導電類型緩衝摻雜區227和第二導電類型接線摻雜區 236構成，如第1圖所示)依序設置開口290b~290d。在本實施例中，分別設計上述遮罩圖案290的開口290a~290d的寛度Wa、Wb、Wc、Wd依序從閘極結構250朝汲極摻雜區呈線性遞減。上述遮罩圖案290的開口290a~290d中任意相鄰的其中兩個開口中，較接近閘極結構250的開口寛度大於相對遠離閘極結構250的開口寛度。舉例來說，對上述遮罩圖案290相鄰的兩個開口290a、290b而言，接近閘極結構250的開口290a的寛度Wa大於相對遠離閘極結構250的開口290b的寛度Wb。上述遮罩圖案290之其他相鄰兩個開口的寛度關係可依上述關係類推。
然後，請再參考第2A圖，利用上述遮罩圖案290做為一遮罩進行一離子植入製程植入第一導電類型摻質，以於開口290a~290d暴露出的第二導電類型深井區223中的部分第二導電類型深井區223中形成複數個第一導電類型摻雜次區280a~280d。由於上述遮罩圖案290的開口290a~290d的寛度Wa~Wd依序沿第二方向252(從閘極結構250至汲極摻雜區)呈線性遞減，因此形成的第一導電類型摻雜次區280a~280d的深度及/或摻質濃度沿第二方向252呈線性遞減。第一導電類型摻雜次區280a~280d中任意相鄰的其中兩個隔離摻雜次區中，接近閘極結構250的中心區域的第一導電類型摻雜次區的深度及/或摻質濃度可大於相對遠離閘極結構250的另一個第一導電類型摻雜次區的深度及/或摻質濃度。舉例來說，就相鄰的兩個第一導電類型摻雜次區280a、280b而言，接近閘極結構250的第一導電類型摻雜次區280a的深度及/或摻質濃度可大於相對遠離閘極結構250的第一導電類型摻雜次區280b的深度及/ 或摻質濃度。其他相鄰兩個第一導電類型摻雜次區的深度關係可依上述關係類推。之後，移除遮罩圖案290。
在本發明一些實施例中，第一導電類型摻雜次區280a~280d可與第一導電類型漂移摻雜區230同時形成。
接著，請參考第2B圖，可進行另一道微影製程，於飄移區108中的磊晶層220的頂面221上形成一遮罩圖案292。上述遮罩圖案292可具有複數個開口292a~292d，暴露出飄移區108中的部分第二導電類型深井區223。其中，為清楚繪示起見，此處是以4個開口(開口292a~292d)來舉例，但不以此為限，在其他實施例中，也可視需要設置開口的數目。在第2B圖所示的一些實施例中，遮罩圖案292的開口292a~292d的寛度Wa~Wd大小關係可類似於上述遮罩圖案290的開口290a~290d，在此不做重複說明。
在其他實施例中，也可設計遮罩圖案292的開口具有其他的寬度，僅須符合開口寬度從閘極結構250朝汲極摻雜區呈線性遞減的條件即可。
然後，請再參考第2B圖，利用上述遮罩圖案292做為一遮罩進行一離子植入製程植入第二導電類型摻質，以於開口292a~292d暴露出的第二導電類型深井區223中的部分第二導電類型深井區223中形成複數個第二導電類型摻雜次區282a~282d。第二導電類型摻雜次區282a~282d會分別相鄰第一導電類型摻雜次區280a~280d。第二導電類型摻雜次區282a~282d的深度及/或摻質濃度關係可類似於第一導電類型摻雜次區280a~280d，在此不做重複說明。之後，移除遮罩圖 案292。
在本發明一些實施例中，第二導電類型摻雜次區282a~282d可與第二導電類型漂移摻雜區228同時形成。
接著，進行一退火製程，使第2B圖所示的第一導電類型摻雜次區280a~280d和第二導電類型摻雜次區282a~282d的摻質均勻擴散以形成具有複數個PN接面的超接面摻雜結構284，如第1圖所示。
在本發明一些實施例中，可於例如UHV LDMOS元件的高壓半導體裝置500a的閘極結構250與汲極摻雜區之間設置超接面摻雜結構284，其可視為一飄移摻雜區(drift doped region)。上述超接面摻雜結構284的寬度、深度和摻質濃度的至少一個從閘極結構250朝向汲極摻雜區的方向(第二方向252)呈線性遞減，上述設計有助於使飄移摻雜區成為完全空乏(fully depleted)達到電荷平衡，且構成一減低表面電場結構(reduced surface field，RESURF)，以降低UHV LDMOS元件的表面電場。並且上述超接面摻雜結構可於一固定飄移摻雜區的長度條件下同時達到高崩潰電壓(breakdown voltage，BVD)和低導通電阻(on resistance，Ron)的效果。
第3圖顯示本發明一些實施例之高壓半導體裝置500b之剖面示意圖。在本實施例中，高壓半導體裝置500b可為一高壓積體電路(HVIC)元件。高壓半導體裝置500b的主要元件可包括一基板結構300、一橫向擴散金屬氧化物半導體270、一一超接面摻雜結構484和一接線摻雜區。上述圖式中的各元件如有與第1圖所示相同或相似的部分，則可參考前面的相關敍 述，在此不做重複說明。
如第3圖所示，基板結構300包括半導體基板200和全面性形成於半導體基板200的頂面211上的磊晶層220。並且，基板結構300包括一低電位區(low side region)202、一高電位區(high side region)208、及設於與低電位區202和高電位區208之間的一電位轉換區(level shift region)204和一隔離區206，沿平行於磊晶層220的頂面211的一方向(例如第二方向252)由左至右依序配置。上述隔離區206位於將電位轉換區204與高電位區208之間，以將電位轉換區204與高電位區208彼此隔開。
如第3圖所示，上述高壓半導體裝置500b包括複數個隔絕結構240，設置於磊晶層220的頂面221上，上述多個隔絕結構232分別覆蓋低電位區202、電位轉換區204、隔離區206和高電位區208中的半導體基板200的部分頂面221，以定義出低電位區202、電位轉換區204、隔離區206和高電位區208中的多個主動區域。舉例來說，隔絕結構240定義出上述低電位區202中之接線摻雜區(pick-up doped region)的形成位置，電位轉換區204的LDMOS元件的閘極、源極摻雜區、汲極摻雜區的形成位置，以及高電位區208中之接線摻雜區的形成位置。
在本發明一些實施例中，上述低電位區202係用以提供低壓積體電路元件(操作電壓例如低於20V)形成於其上，上述高電位區208係用以提供高壓積體電路元件(操作電壓例如大於等於600V)形成於其上。並且，上述電位轉換區204可包括橫向擴散金屬氧化物半導體(laterally diffused metal oxide semiconductor，以下簡稱LDMOS)元件270形成於其上。而隔離 區206係用以在橫向擴散金屬氧化物半導體之閘極設於關閉狀態時，電性隔離上述低電位區202和高電位區208。
上述電位轉換區204的LDMOS元件270的源極S可電性耦接至低電位區202中的低壓積體電路元件。並且，上述電位轉換區204的LDMOS元件270的汲極D可藉由跨越隔離區206的金屬內連線(圖未顯示)電性耦接至高電位區208中的高壓積體電路元件，當上述LDMOS元件之閘極係設於開通狀態時，可用以將低電位區202的低電壓位準轉換成高電位區208的高電壓位準。
如第3圖所示，高壓半導體裝置500a包括一高壓第一導電類型井區222，設置於低電位區202和電位轉換區204的磊晶層220中。高壓第一導電類型井區222的邊界可位於LDMOS元件270的一閘極結構250的正下方。高壓第一導電類型井區222可用以提供LDMOS元件270的源極摻雜區和低壓積體電路元件的接線摻雜區形成於其中。舉例來說，當第一導電類型為P型時，上述第二導電類型為N型，上述高壓第一導電類型井區222可視為高壓P型井區(HVPW)222。在本發明一些實施例中，上述高壓第一導電類型井區222的底面可位於磊晶層220內，或可對齊於半導體基板200和磊晶層220的交界處260(位置同半導體基板200的頂面211)。
如第3圖所示，高壓半導體裝置500b包括一高壓第二導電類型井區224，設置於高電位區208中的磊晶層220內。高壓第二導電類型井區224可提供高壓積體電路元件的隔離摻雜區形成於其中。舉例來說，當第一導電類型為P型時，上述 第二導電類型為N型，上述高壓第二導電類型井區224可視為高壓N型井區(HVNW)224。
在本發明一些實施例中，高壓半導體裝置500b的低電位區202中的接線摻雜區可包括由下而上依序設置於高壓第一導電類型井區222上的一第一導電類型漂移摻雜區230、一第一導電類型井區226和一第一導電類型接線摻雜區(pick-up doped region)234。舉例來說，當第一導電類型為P型時，上述第一導電類型漂移摻雜區230可視為P型漂移摻雜區(P-drift doped region)230，上述第一導電類型井區226可視為P型井區226，而上述第一導電類型接線摻雜區234可視為P型接線摻雜區234。
在本發明一些實施例中，上述第一導電類型接線摻雜區234的摻雜濃度大於第一導電類型井區226的摻雜濃度，第一導電類型井區226的摻雜濃度大於P型漂移摻雜區230的摻雜濃度，且P型漂移摻雜區230的摻雜濃度大於高壓第一導電類型井區222的摻雜濃度。
在本發明一些實施例中，高壓半導體裝置500b的高電位區208中之接線摻雜區中可包括由下而上依序設置於高壓第二導電類型井區224上的第二導電類型漂移摻雜區238和第二導電類型接線摻雜區236。舉例來說，當第一導電類型為P型時，第二導電類型為N型，上述第二導電類型漂移摻雜區238可視為N型漂移摻雜區N型井區/N型漂移摻雜區(NW/N-drift doped region)238，且上述第二導電類型接線摻雜區236可視為N型接線摻雜區236。
在本發明一些實施例中，上述磊晶層220的摻雜濃度低於述高壓第二導電類型井區224的摻雜濃度，上述高壓第二導電類型井區224的摻雜濃度低於上述第二導電類型漂移摻雜區238的摻雜濃度，且上述第二導電類型漂移摻雜區238的摻雜濃度低於第二導電類型接線摻雜區236的摻雜濃度。在本發明一些實施例中，第二導電類型漂移摻雜區228和第二導電類型漂移摻雜區238可於同一製程步驟形成，或於不同製程步驟形成。
如第3圖所示，在高壓半導體裝置500b中，LDMOS元件270的源極摻雜區橫跨設置於低電位區202和電位轉換區204。源極摻雜區可包括由下而上依序設置於高壓第一導電類型井區222上的一第二導電類型漂移摻雜區228、第二導電類型緩衝摻雜區227和第二導電類型接線摻雜區236。舉例來說，當第一導電類型為P型時，第二導電類型為N型，上述第二導電類型漂移摻雜區228可視為N型漂移摻雜區(N-drift doped region)228，上述第二導電類型緩衝摻雜區227可視為N型緩衝摻雜區227，且上述第二導電類型接線摻雜區236可視為N型接線摻雜區236。
如第3圖所示，在高壓半導體裝置500b中，LDMOS元件270的汲極摻雜區設置於電位轉換區204中，且接近於電位轉換區204和隔離區206的交界處。汲極摻雜區可包括由下而上依序設置於磊晶層220中的一第二導電類型漂移摻雜區228、一第二導電類型緩衝摻雜區227和一第二導電類型接線摻雜區236。舉例來說，當第一導電類型為P型時，第二導電類型為N 型，上述第二導電類型漂移摻雜區228可視為N型漂移摻雜區(N-drift doped region)228，上述第二導電類型緩衝摻雜區227可視為N型緩衝摻雜區227，且上述第二導電類型接線摻雜區236可視為N型接線摻雜區236。
如第3圖所示，在高壓半導體裝置500b中，LDMOS元件270的閘極結構250設置於磊晶層220的頂面221上，且位於電位轉換區204中。LDMOS元件270的源極摻雜區和汲極摻雜區分別位於閘極結構250的相反側。上述閘極結構250覆蓋位於高壓第一導電類型井區222和磊晶層220上的部分隔絕結構240，且覆蓋高壓第一導電類型井區222和其上的第二導電類型漂移摻雜區228(低電位區202和閘極結構250之間)。上述閘極結構250藉由另一個隔絕結構240(閘極結構250和高電位區208之間)與汲極摻雜區的第二導電類型漂移摻雜區228相隔一距離。
在本發明一些實施例中，高壓半導體裝置500b可包括複數個第二導電類型埋藏摻雜層212，設置接近隔離區206的高電位區208的部分半導體基板200內，以及接近隔離區206和電位轉換區204之間的部分半導體基板200內。並且，第二導電類型埋藏摻雜層212會擴散延伸進入磊晶層220中。上述第二導電類型埋藏摻雜層212具有一第二導電類型，且第二導電類型不同於第一導電類型。舉例來說，當第一導電類型為P型時，上述第二導電類型為N型，且第二導電類型埋藏摻雜層212可視為一N型埋藏摻雜層。
接下來利用第3圖說明高壓半導體裝置500b之一超接面摻雜結構484的形成位置。上述超接面摻雜結構484位於 隔離區206中的隔絕結構240下方，且位於磊晶層220中，且分別與LDMOS元件270的汲極摻雜區和高電位區208的接線摻雜區隔開。超接面摻雜結構484可做為高壓半導體裝置500b之隔離摻雜區。在本發明一些實施例中，超接面摻雜結構484包括複數個第一導電類型摻雜次區480a、480b和480c，以及複數個第二導電類型摻雜次區482a、482b和482c。第一導電類型摻雜次區480a、480b和480c具有第一導電類型。第一導電類型摻雜次區480a、480b和480c沿一第一方向256(意即基板結構300的頂面(位置相同於磊晶層220的頂面221)的一法線方向)延伸且沿一第二方向(從接近超接面摻雜結構484的一中心區域至接近超接面摻雜結構484的一外圍區域的方向)設置。另外，第二導電類型摻雜次區482a、482b和482c具有第二導電類型，沿第一方向256延伸且沿第二方向(從接近超接面摻雜結構484的中心區域至接近超接面摻雜結構484的外圍區域的方向)與第一導電類型摻雜次區480a、480b和480c交錯設置。
在如第3圖所示的剖面圖中，第一導電類型摻雜次區480a、480b和480c和第二導電類型摻雜次區482a、482b和482c具有且為沿第一方向256延伸的長條柱狀。值得注意的是，上述第一方向256實質平行於基板結構300的頂面221的法線方向，而第二方向實質平行於從接近超接面摻雜結構484的中心區域至接近超接面摻雜結構484的外圍區域的方向。
如第3圖所示，第二導電類型摻雜次區482a的相反兩側分別鄰接兩個第一導電類型摻雜次區480a和480b，第一導電類型摻雜次區480b的相反兩側分別鄰接兩個第二導電類型 摻雜次區482a、482b。上述第一導電類型摻雜次區和第二導電類型摻雜次區的鄰接關係可依上述關係類推。然而，在其他實施例中，第一導電類型摻雜次區480a、480b和480c的位置可與第二導電類型摻雜次區482a、482b和482c互換。
在本發明一些實施例中，在超接面摻雜結構484中，可設計第一導電類型摻雜次區480a、480b和480c沿第一方向256的深度、沿第二方向(從接近超接面摻雜結構484的中心區域至接近超接面摻雜結構484的外圍區域)的寬度和摻質濃度的至少一個沿第二方向呈線性遞減。類似地，第二導電類型摻雜次區482a、482b和482c沿第一方向256的深度、沿第二方向(從接近超接面摻雜結構484的中心區域至接近超接面摻雜結構484的外圍區域)的寬度和摻質濃度的至少一個沿第二方向呈線性遞減。在第1圖所示之實施例中，第一導電類型摻雜次區480a、480b和480c各別的寬度沿第二方向呈線性遞減，且第二導電類型摻雜次區482a、482b和482c各別的寬度沿第二方向呈線性遞減。而且，超接面摻雜結構484的底面對齊於磊晶層220的一底面(位置相同於半導體基板200的頂面211)。在本發明一些其他實施例中，超接面摻雜結構484的最低處可以在磊晶層的底面的上方(即為不與半導體基板200的頂面211接觸)。
接下來利用第4A、4B圖說明第3圖所示實施例之超接面摻雜結構484的形成方式。第4A、4B圖為第3圖所示之高壓半導體裝置的隔離區206的局部放大圖，並顯示形成隔離區206中的超接面摻雜結構484的部分製程步驟。上述製程於形成第3圖所示的隔絕結構240之前進行，因而隔絕結構240在此不 予顯示。
如第4A圖所示，可進行一微影製程，於隔離區206中的磊晶層220的頂面221上形成一遮罩圖案490。上述遮罩圖案490可具有複數個開口490a~490c。遮罩圖案490的開口480a係設置位於接近隔離區206的一中心區域，且從隔離區206的中心區域朝隔離區206的一外圍區域(例如接近隔離區206與電位轉換區204的交界處和隔離區206與高電位區208的交界處，如第1圖所示)依序設置開口490b~490c。並且，分別設計上述遮罩圖案490的開口490a~490c的寛度W1~W3依序從接近隔離區206的中心區域至接近隔離區206的一外圍區域呈線性遞減。上述遮罩圖案490的開口490a~490c中任意相鄰的其中兩個開口中，較接近隔離區206的中心區域大於相對遠離隔離區206的中心區域的開口寛度。
然後，利用上述遮罩圖案490做為一遮罩進行一離子植入製程，以於開口490a~490c暴露出的隔離區206中的部分磊晶層220中植入第一導電類型摻質，以形成複數個第一導電類型摻雜次區480a、480b和480c。由於上述遮罩圖案490的開口490a~490c的寛度W1~W3依序從接近隔離區206的中心區域至外圍區域呈線性遞減，因此形成的第一導電類型摻雜次區480a、480b和480c的深度及/或摻質濃度從接近從隔離區206的中心區域朝隔離區206的外圍區域(例如接近隔離區206與電位轉換區204的交界處和隔離區206與高電位區208的交界處)呈線性遞減。在本發明一些其他實施例中，相鄰的兩個隔離摻雜次區係彼此部分重疊。之後，移除遮罩圖案490。
在本發明一些實施例中，第一導電類型摻雜次區480a、480b和480c可與高壓第一導電類型井區222同時形成。
接著，如第4B圖所示，可進行另一微影製程，於隔離區206中的磊晶層220的頂面221上形成另一遮罩圖案492。上述遮罩圖案492可具有複數個開口492a~492c。在第4B圖所示的一些實施例中，遮罩圖案492的開口492a~492c的寛度W1~W3大小關係可類似於上述遮罩圖案490的開口490a~490c，在此不做重複說明。
在其他實施例中，也可設計遮罩圖案492的開口具有其他的寬度，僅須符合開口寬度從接近隔離區206的中心區域至外圍區域呈線性遞減的條件即可。
然後，請再參考第4B圖，利用上述遮罩圖案492做為一遮罩進行一離子植入製程植入第二導電類型摻質，以於開口482a~482c暴露出的磊晶層220中形成複數個第二導電類型摻雜次區482a、482b和482c。第二導電類型摻雜次區482a、482b和482c會分別相鄰第一導電類型摻雜次區480a、480b和480c。第二導電類型摻雜次區482a、482b和482c的深度及/或摻質濃度關係可類似於第一導電類型摻雜次區480a、480b和480c，在此不做重複說明。之後，移除遮罩圖案492。
在本發明一些實施例中，第二導電類型摻雜次區492a、492b和492c可與高壓第二導電類型井區224同時形成。
接著，進行一退火製程，使第4B圖所示的第一導電類型摻雜次區480a~480c和第二導電類型摻雜次區482a~482c的摻質均勻擴散以形成具有複數個PN接面的超接面 摻雜結構484，如第3圖所示。
在本發明一些實施例中，可於例如高壓積體電路(HVIC)元件的高壓半導體裝置500b的隔離區內設置超接面摻雜結構484，其可視為用以電性隔絕高電位區206和低電位區202的一隔絕摻雜區。上述超接面摻雜結構484的寬度、深度和摻質濃度的至少一個從接近超接面摻雜結構484(或隔離區206)的一中心區域至接近超接面摻雜結構484的一外圍區域呈線性遞減，上述設計有助於使超接面摻雜結構成為完全空乏(fully depleted)達到電荷平衡，且可使高壓半導體的表面電場均勻分佈，因而可提升高壓積體電路的的崩潰電壓(breakdown voltage，BVD)。另一方面，上述超接面摻雜結構可在提升崩潰電壓要求的同時增加其在高電位區和低電位區的有效寬度，所以可具有足夠濃的表面摻質濃度，進一步抑制橫向漏電現象(lateral punch-through leakage current)。
雖然本發明已以實施例揭露於上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。

Claims (10)

  1. 一種高壓半導體裝置，包括：一基板結構；一閘極結構，位於該基板結構上；一汲極摻雜區，位於該基板結構內，且接近該閘極結構的一第一側；以及一超接面摻雜結構，位於該基板結構內，且接近該汲極摻雜區，其中該超接面摻雜結構包括：複數個第一導電類型摻雜次區，具有一第一導電類型，該些第一導電類型摻雜次區沿一第一方向延伸且沿一第二方向設置；以及複數個第二導電類型摻雜次區，具有相反於該第一導電類型的一第二導電類型，該些第二導電類型摻雜次區沿該第一方向延伸且沿該第二方向與該些第一摻雜部分交錯設置，其中該些第一導電類型摻雜次區各別沿該第二方向的寬度沿該第二方向呈線性遞減，和其中該些第二導電類型摻雜次區各別沿該第二方向的寬度沿該第二方向呈線性遞減。
  2. 如申請專利範圍第1項所述之高壓半導體裝置，其中該些第一導電類型摻雜次區各別沿該第一方向的深度沿該第二方向呈線性遞減，或其中該些第二導電類型摻雜次區各別沿該第一方向的深度沿該第二方向呈線性遞減。
  3. 如申請專利範圍第1項所述之高壓半導體裝置，其中該些 第一導電類型摻雜次區各別的摻質濃度沿該第二方向呈線性遞減，或其中該些第二導電類型摻雜次區各別的摻質濃度沿該第二方向呈線性遞減。
  4. 如申請專利範圍第1項所述之高壓半導體裝置，其中該基板結構包括：一半導體基板，具有一第一導電類型；一磊晶層，設於該半導體基板上，其中該磊晶層具有一第二導電類型，且該第一導電類型與該第二導電類型不同。
  5. 如申請專利範圍第4項所述之高壓半導體裝置，更包括：一源極摻雜區，位於該基板結構內，且接近該閘極結構的相反於該第一側的一第二側。
  6. 如申請專利範圍第5項所述之高壓半導體裝置，其中該基板結構包括：一高電位區；一低電位區，其與該高電位區彼此隔開；以及一電位轉換區和一隔離區，設置於該高電位區與該低電位區之間，其中該隔離區將該電位轉換區與該高電位區彼此隔開；其中該超接面摻雜結構位於該隔離區中。
  7. 一種高壓半導體裝置，包括：一基板結構；一閘極結構，位於該基板結構上；一汲極摻雜區，位於該基板結構內，且接近該閘極結構 的一第一側；以及一超接面摻雜結構，位於該基板結構內，且接近該汲極摻雜區，其中該超接面摻雜結構包括：複數個第一導電類型摻雜次區，具有一第一導電類型，該些第一導電類型摻雜次區沿一第一方向延伸且沿一第二方向設置；以及複數個第二導電類型摻雜次區，具有相反於該第一導電類型的一第二導電類型，該些第二導電類型摻雜次區沿該第一方向延伸且沿該第二方向與該些第一摻雜部分交錯設置，其中該些第一導電類型摻雜次區各別沿該第一方向的深度、沿該第二方向的寬度和摻質濃度的至少一個沿該第二方向呈線性遞減。
  8. 如申請專利範圍第7項所述之高壓半導體裝置，其中該第一方向實質平行於該基板結構的一頂面的一法線方向，該第二方向實質平行於該閘極結構朝向該汲極摻雜區的一方向。
  9. 一種高壓半導體裝置，包括：一基板結構；一閘極結構，位於該基板結構上；一汲極摻雜區，位於該基板結構內，且接近該閘極結構的一第一側；以及一超接面摻雜結構，位於該基板結構內，且接近該汲極摻雜區，其中該超接面摻雜結構包括： 彼此相鄰的一第一導電類型摻雜次區和一第二導電類型摻雜次區，該第一導電類型摻雜次區具有一第一導電類型，該第二導電類型摻雜次區具有相反於該第一導電類型的一第二導電類型，其中該第一導電類型摻雜次區和該第二導電類型摻雜次區沿一第一方向延伸且沿一第二方向設置，其中該第一導電類型摻雜次區和該第二導電類型摻雜次區沿該第一方向的深度、沿該第二方向的寬度和摻質濃度的至少一個沿該第二方向彼此不同。
  10. 如申請專利範圍第9項所述之高壓半導體裝置，其中該超接面摻雜結構包括：另一第二導電類型摻雜次區，相鄰於該第一導電類型摻雜次區，且與該第二導電類型摻雜次區分別位於該第一導電類型摻雜次區的相反側，其中該第一導電類型摻雜次區和該另一第二導電類型摻雜次區沿該第一方向的深度、沿該第二方向的寬度和摻質濃度的至少一個彼此相同。
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