CN108269851A - 高压半导体装置 - Google Patents

高压半导体装置 Download PDF

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Publication number
CN108269851A
CN108269851A CN201711471935.8A CN201711471935A CN108269851A CN 108269851 A CN108269851 A CN 108269851A CN 201711471935 A CN201711471935 A CN 201711471935A CN 108269851 A CN108269851 A CN 108269851A
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conduction type
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along
doping time
semiconductor device
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CN108269851B (zh
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伊牧
陈柏安
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Nuvoton Technology Corp
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Nuvoton Technology Corp
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Abstract

本发明实施例提供一种高压半导体装置。高压半导体装置包括位于基板结构上的栅极结构。位于基板结构内的漏极掺杂区。超接面掺杂结构，位于基板结构内，且接近漏极掺杂区。超接面掺杂结构包括多个第一导电类型掺杂次区，第一导电类型掺杂次区沿第一方向延伸且沿第二方向设置。多个第二导电类型掺杂次区，沿第一方向延伸且沿第二方向与第一掺杂部分交错设置。第一导电类型掺杂次区各自沿第二方向的宽度沿第二方向呈线性递减，和第二导电类型掺杂次区各自沿第二方向的宽度沿第二方向呈线性递减。

Description

高压半导体装置
技术领域
本发明实施例是有关于一种半导体装置，特别是有关于一种高压半导体装置。
背景技术
高压集成电路(HVIC)因具有符合成本效益且易相容于其它工艺等优点，因而已广泛应用于发光二极管(LED)、显示器驱动集成电路元件、电源供应器、电力管理、通信、车用电子的电源控制系统中。然而，已知的高压集成电路会因为闭锁效应(latch up)、低击穿电压、低元件切换速度及较大的元件面积等问题而无法进一步的改善。
因此，在此技术领域中，有需要一种高压半导体装置，以改善上述缺点。
发明内容
本发明的一实施例是提供一种高压半导体装置。上述高压半导体装置包括一基板结构；一栅极结构，位于上述基板结构上；一漏极掺杂区，位于上述基板结构内，且接近上述栅极结构的一第一侧；以及一超接面掺杂结构，位于上述基板结构内，且接近上述漏极掺杂区，其中上述超接面掺杂结构包括：多个第一导电类型掺杂次区，具有一第一导电类型，上述多个第一导电类型掺杂次区沿一第一方向延伸且沿一第二方向设置；以及多个第二导电类型掺杂次区，具有相反于上述第一导电类型的一第二导电类型，上述多个第二导电类型掺杂次区沿上述第一方向延伸且沿上述第二方向与上述多个第一掺杂部分交错设置，其中上述多个第一导电类型掺杂次区各自沿上述第二方向的宽度沿上述第二方向呈线性递减，和其中上述多个第二导电类型掺杂次区各自沿上述第二方向的宽度沿上述第二方向呈线性递减。
在本发明一实施例中，所述多个第一导电类型掺杂次区各自沿所述第一方向的深度沿所述第二方向呈线性递减，或其中所述多个第二导电类型掺杂次区各自沿所述第一方向的深度沿所述第二方向呈线性递减。
在本发明一实施例中，所述多个第一导电类型掺杂次区各自的掺质浓度沿所述第二方向呈线性递减，或其中所述多个第二导电类型掺杂次区各自的掺质浓度沿所述第二方向呈线性递减。
在本发明一实施例中，所述基板结构包括：一半导体基板，具有一第一导电类型；一磊晶层，设于所述半导体基板上，其中所述磊晶层具有一第二导电类型，且所述第一导电类型与所述第二导电类型不同。
在本发明一实施例中，所述的高压半导体装置更包括：一源极掺杂区，位于所述基板结构内，且接近所述栅极结构的相反于所述第一侧的一第二侧，所述基板结构具有一顶面，所述源极掺杂区、所述闸极结构、所述汲极掺杂区皆在所述顶面。
在本发明一实施例中，所述基板结构包括：一高电位区；一低电位区，其与所述高电位区彼此隔开；以及一电位转换区和一隔离区，设置于所述高电位区与所述低电位区之间，其中所述隔离区将所述电位转换区与所述高电位区彼此隔开；其中所述超接面掺杂结构位于所述隔离区中。
本发明的另一实施例是提供一种高压半导体装置。上述高压半导体装置包括一基板结构；一栅极结构，位于上述基板结构上；一漏极掺杂区，位于上述基板结构内，且接近上述栅极结构的一第一侧；以及一超接面掺杂结构，位于上述基板结构内，且接近上述漏极掺杂区，其中上述超接面掺杂结构包括：多个第一导电类型掺杂次区，具有一第一导电类型，上述多个第一导电类型掺杂次区沿一第一方向延伸且沿一第二方向设置；以及多个第二导电类型掺杂次区，具有相反于上述第一导电类型的一第二导电类型，上述多个第二导电类型掺杂次区沿上述第一方向延伸且沿上述第二方向与上述多个第一掺杂部分交错设置，其中上述多个第一导电类型掺杂次区各自沿上述第一方向的深度、沿上述第二方向的宽度和掺质浓度的至少一个沿上述第二方向呈线性递减。
在本发明一实施例中，所述第一方向平行于所述基板结构的一顶面的一法线方向，所述第二方向平行于所述栅极结构朝向所述漏极掺杂区的一方向。
本发明的又一实施例是提供一种高压半导体装置。上述高压半导体装置包括一基板结构；一栅极结构，位于上述基板结构上；一漏极掺杂区，位于上述基板结构内，且接近上述栅极结构的一第一侧；以及一超接面掺杂结构，位于上述基板结构内，且接近上述漏极掺杂区，其中上述超接面掺杂结构包括：彼此相邻的一第一导电类型掺杂次区和一第二导电类型掺杂次区，上述第一导电类型掺杂次区具有一第一导电类型，上述第二导电类型掺杂次区具有相反于上述第一导电类型的一第二导电类型，其中上述第一导电类型掺杂次区和上述第二导电类型掺杂次区沿一第一方向延伸且沿一第二方向设置，其中上述第一导电类型掺杂次区和上述第二导电类型掺杂次区沿上述第一方向的深度、沿上述第二方向的宽度和掺质浓度的至少一个沿上述第二方向彼此不同。
在本发明一实施例中，所述超接面掺杂结构包括：另一第二导电类型掺杂次区，相邻于所述第一导电类型掺杂次区，且与所述第二导电类型掺杂次区分别位于所述第一导电类型掺杂次区的相反侧，其中所述第一导电类型掺杂次区和所述另一第二导电类型掺杂次区沿所述第一方向的深度、沿所述第二方向的宽度和掺质浓度的至少一个彼此相同。
附图说明
图1显示本发明一些实施例的高压半导体装置的剖面示意图。
图2A、图2B为显示形成于漂移区中的超接面掺杂结构的部分工艺步骤。
图3显示本发明一些实施例的高压半导体装置的剖面示意图。
图4A、图4B为显示形成隔离区中的超接面掺杂结构的部分工艺步骤。
附图标记
500a、500b～高压半导体装置；
102～接线区；
104～源极区；
106～栅极区；
108～漂移区；
110～漏极区；
200～半导体基板；
202～低电位区；
204～电位转换区；
206～隔离区；
208～高电位区；
211、221～顶面；
212～第二导电类型埋藏掺杂层；
220～磊晶层；
222～高压第一导电类型阱；
223～第二导电类型深阱；
224～高压第二导电类型阱；
225第一导电类型阱；
226～第一导电类型阱；
227～第二导电类型缓冲掺杂区；
228～第二导电类型漂移掺杂区；
229～第一导电类型场掺杂区；
230～第一导电类型漂移掺杂区；
234～第一导电类型接线掺杂区；
236～第二导电类型接线掺杂区；
238～第二导电类型漂移掺杂区；
240～隔绝结构；
290、292、490、492～遮罩图案；
290a、290b、290c、290d、292a、292b、292c、292d、490a、490b、490c、492a、492b、492c～开口；
Wa、Wb、Wc、Wd、W1、W2、W3～宽度；
250～栅极结构；
256～第一方向；
252～第二方向；
260～交界处；
270～横向扩散金属氧化物半导体；
284、484～超接面掺杂结构；
280a、280b、280c、280d、480a、480b、480c～第一导电类型掺杂次区；
282a、282b、282c、282d、482a、482b、482c～第二导电类型掺杂次区；
300～基板结构；
S～源极；
D～漏极。
具体实施方式
为了让本发明的目的、特征、及优点能更明显易懂，下文特举实施例，并配合所附图示，做详细的说明。本发明说明书提供不同的实施例来说明本发明不同实施方式的技术特征。其中，实施例中的各元件的配置为说明之用，并非用以限制本发明。且实施例中图式标号的部分重复，是为了简化说明，并非意指不同实施例之间的关联性。
本发明实施例是提供用于超高压横向扩散金属氧化物半导体(ultra high-voltage laterally diffused metal oxide semiconductor，以下简称UHV LDMOS)元件或高压集成电路(HVIC)元件的一种高压半导体装置。上述高压半导体装置包括一超接面掺杂结构(super junction doped structure)。上述超接面掺杂结构的宽度、深度和掺质浓度的至少一个沿一方向呈线性递减，以构成一减低表面电场结构(reduced surface field，RESURF)。因此，超接面掺杂结构可有效降低高压半导体装置的表面电场，并且可使高压半导体装置达到高崩溃电压(breakdown voltage，BVD)的效果。
图1显示本发明一些实施例的高压半导体装置500a的剖面示意图。在本实施例中，高压半导体装置500a可为一超高压横向扩散金属氧化物半导体(ultra high-voltagelaterally diffused metal oxide semiconductor，以下简称UHV LDMOS)元件。高压半导体装置500a的主要元件可包括一基板结构300、一栅极结构250、一源极掺杂区、一超接面掺杂结构284和一漏极掺杂区和一接线掺杂区。
如图1所示，上述基板结构300包括一半导体基板200和全面性形成于半导体基板200的顶面211上的一磊晶层220。上述半导体基板200是掺杂掺质以具有第一导电类型。举例来说，当第一导电类型为P型时，上述半导体基板200可为一P型基板。在本发明一些实施例中，半导体基板200的掺杂浓度可为约1x1011-1x1015/cm3，因而半导体基板200可视为一轻掺杂P型半导体基板200。此处的“轻掺杂”意指掺杂浓度小于1x1015/cm3。在本发明一些实施例中，上述半导体基板200可为硅基板。在本发明其他实施例中，可利用锗化硅(SiGe)、块状半导体(bulk semiconductor)、应变半导体(strained semiconductor)、化合物半导体(compound semiconductor)，或其他常用的半导体基板作为半导体基板200。上述磊晶层220的材质可包括硅、锗、硅与锗、III-V族化合物或上述的组合。上述磊晶层220具有第二导电类型，且第二导电类型不同于第一导电类型。举例来说，当第一导电类型为P型时，上述第二导电类型为N型，且磊晶层220可视为一N型磊晶层220。在本发明一些实施例中，磊晶层220可具有例如磷(P)的掺质。
如图1所示，基板结构300包括一接线区(pick-up region)102、一源极区(sourceregion)104、一栅极区(gate region)106、一漂移区(drift region)108和一漏极区(drainregion)110，沿平行于磊晶层220的顶面221的一方向(例如第二方向252)由左至右依序配置。
如图1所示，上述高压半导体装置500a包括多个隔绝结构240，设置于磊晶层220的顶面221上，以定义出接线区102、源极区104、栅极区106和漏极区110中的多个主动区域，且覆盖漂移区108。举例来说，隔绝结构240定义出上述栅极结构250、源极掺杂区、漏极掺杂区以及接线掺杂区的形成位置。在本发明一些实施例中，上述隔绝结构240可包括局部氧化物(Local Oxidation of Silicon，LOCOS)或浅沟槽隔绝物(Shallow Trench Isolation，STI)。
如图1所示，高压半导体装置500a包括一高压第一导电类型阱222、一高压第二导电类型阱224和一第二导电类型深阱223，设置于磊晶层220内。高压第一导电类型阱222位于接线区102中、高压第二导电类型阱224位于源极区104中，而第二导电类型深阱223位于漂移区108和漏极区110中。举例来说，当第一导电类型为P型时，上述第二导电类型为N型，上述高压第一导电类型阱222可视为高压P型阱(HVPW)222、上述高压第二导电类型阱224可视为高压N型阱(HVNW)224，且上述第二导电类型深阱223可视为N型深阱(DNW)223。在本发明一些实施例中，上述高压第二导电类型阱224和第二导电类型深阱223的底面可位于磊晶层220内，而高压第一导电类型阱222的底面可对齐于基板200和磊晶层220的交界处260(位置同基板200的顶面211)。可利用离子植入工艺形成高压第一导电类型阱222、一高压第二导电类型阱224和一第二导电类型深阱223。
在本发明一些实施例中，高压半导体装置500a的接线区102中可包括由下而上依序设置于高压第一导电类型阱222上的一第一导电类型漂移掺杂区(drift doped region)230、一第一导电类型阱226、一第一导电类型场掺杂区(field doped region)229和一第一导电类型接线掺杂区(pick-up doped region)234。举例来说，当第一导电类型为P型时，上述第一导电类型漂移掺杂区230可视为P型漂移掺杂区(P-drift doped region)230，上述第一导电类型阱226可视为P型阱226，上述第一导电类型场掺杂区229可视为P型场掺杂区(P-field doped region)229，而上述第一导电类型接线掺杂区234可视为P型接线掺杂区234。
在本发明一些实施例中，上述第一导电类型接线掺杂区234的掺杂浓度大于第一导电类型场掺杂区229的掺杂浓度，第一导电类型场掺杂区229的掺杂浓度大于第一导电类型阱226的掺杂浓度，第一导电类型阱226的掺杂浓度大于P型漂移掺杂区230的掺杂浓度，且P型漂移掺杂区230的掺杂浓度大于高压第一导电类型阱222的掺杂浓度。可利用不同的离子植入工艺分别形成第一导电类型漂移掺杂区230、第一导电类型阱226、第一导电类型场掺杂区229和第一导电类型接线掺杂区234。
如图1所示，高压半导体装置500a的源极区104中可包括由下而上依序设置于高压第二导电类型阱224上的一第一导电类型阱225、第一导电类型接线掺杂区234和第二导电类型接线掺杂区236。举例来说，当第一导电类型为P型时，第二导电类型为N型，上述第一导电类型阱225可视为P型隔绝阱(isolated PW(IPW))225、上述第一导电类型接线掺杂区234可视为P型接线掺杂区234，且上述第二导电类型接线掺杂区236可视为N型接线掺杂区236。并且，源极区104中的第一导电类型阱225、第一导电类型接线掺杂区234和第二导电类型接线掺杂区236一起构成源极掺杂区。
在本发明一些实施例中，上述第一导电类型接线掺杂区234的掺杂浓度大于第一导电类型阱225的掺杂浓度。上述第二导电类型接线掺杂区236的掺杂浓度大于高压第二导电类型阱224的掺杂浓度。可利用数道离子植入工艺分别形成上述第一导电类型阱225、第一导电类型接线掺杂区234和第二导电类型接线掺杂区236。
如图1所示，高压半导体装置500a的漏极区110中可包括由下而上依序设置于第二导电类型深阱223上的一第二导电类型漂移掺杂区228、一第二导电类型缓冲掺杂区227和一第二导电类型接线掺杂区236。举例来说，当第一导电类型为P型时，第二导电类型为N型，上述第二导电类型漂移掺杂区228可视为N型漂移掺杂区(N-drift doped region)228，上述第二导电类型缓冲掺杂区227可视为N型缓冲掺杂区227，且上述第二导电类型接线掺杂区236可视为N型接线掺杂区236。并且，漏极区110中的第二导电类型漂移掺杂区228、第二导电类型缓冲掺杂区227和第二导电类型接线掺杂区236一起构成漏极掺杂区。
在本发明一些实施例中，上述第二导电类型接线掺杂区236的掺杂浓度大于第二导电类型缓冲掺杂区227的掺杂浓度，且第二导电类型缓冲掺杂区227的掺杂浓度的掺杂浓度大于第二导电类型漂移掺杂区228的掺杂浓度。可利用数道离子植入工艺分别形成上述第二导电类型漂移掺杂区228、第二导电类型缓冲掺杂区227和第二导电类型接线掺杂区236。
如图1所示，上述高压半导体装置500的栅极结构250设置于磊晶层220的顶面221上，且位于栅极区106中。高压半导体装置500a的源极掺杂区和漏极掺杂区分别位于栅极结构250的相反侧。栅极结构250接近于源极区104的一第一侧覆盖部分高压第二导电类型阱224，栅极结构250接近于漂移区108的一第二侧覆盖漂移区108中的部分隔绝结构240及其下的第二导电类型深阱223。栅极结构250通过漂移区108中的隔绝结构240与漏极掺杂区隔开。栅极结构250包括一栅极绝缘材料(图未显示)和位于栅极绝缘材料上的一栅极导电材料。可利用例如化学气相沉积法(CVD)或原子层沉积法(ALD)的一薄膜沉积工艺及后续的一图案化工艺形成上述栅极结构250。
接下来利用图1说明高压半导体装置500a的一超接面掺杂结构284的形成位置。上述超接面掺杂结构284位于漂移区108中的隔绝结构240下方的第二导电类型深阱223内，且与漏极掺杂区隔开一距离。并且，上述超接面掺杂结构284位于栅极结构250与漏极掺杂区之间。在本发明一些实施例中，超接面掺杂结构284包括多个第一导电类型掺杂次区280a、280b、280c和280d，以及多个第二导电类型掺杂次区282a、282b、282c和282d。第一导电类型掺杂次区280a、280b、280c和280d具有第一导电类型。第一导电类型掺杂次区280a、280b、280c和280d沿一第一方向256延伸且沿一第二方向252设置。另外，第二导电类型掺杂次区282a、282b、282c和282d具有第二导电类型，沿第一方向256延伸且沿第二方向252与第一导电类型掺杂次区280a、280b、280c和280d交错设置。
在如图1所示的剖面图中，第一导电类型掺杂次区280a、280b、280c和280d和第二导电类型掺杂次区282a、282b、282c和282d具有且为沿第一方向256延伸的长条柱状。值得注意的是，第一方向256实质平行于基板结构300的顶面221的一法线方向，而第二方向252实质平行于栅极结构250朝向漏极掺杂区的一方向。
如图1所示，第二导电类型掺杂次区282a的相反两侧分别邻接两个第一导电类型掺杂次区280a和280b，第一导电类型掺杂次区280b的相反两侧分别邻接两个第二导电类型掺杂次区282a、282b。上述第一导电类型掺杂次区和第二导电类型掺杂次区的邻接关系可依上述关系类推。然而，在其他实施例中，第一导电类型掺杂次区280a、280b、280c和280d的位置可与第二导电类型掺杂次区282a、282b、282c和282d互换。
举例来说，当第一导电类型为P型时，第二导电类型为N型，上述第一导电类型掺杂次区280a、280b、280c和280d分别为P型掺杂次区280a、280b、280c和280d，而上述第二导电类型掺杂次区282a、282b、282c和282d分别为N型掺杂次区282a、282b、282c和282d。因此，第一导电类型掺杂次区可与邻接的第二导电类型掺杂次区形成一PN接面(PN junction)。举例来说，第一导电类型掺杂次区280a和邻接的第二导电类型掺杂次区282a可形成一PN接面，第一导电类型掺杂次区280b可与两个邻接的第二导电类型掺杂次区282a、282b分别形成两个PN接面。超接面掺杂结构284的其他PN接面的形成位置可由上述第一导电类型掺杂次区和第二导电类型掺杂次区的邻接关系类推。
在本发明一些实施例中，在超接面掺杂结构284中，可设计第一导电类型掺杂次区280a、280b、280c和280d沿第一方向256的深度、沿第二方向252的宽度和掺质浓度的至少一个沿第二方向252呈线性递减。类似地，第二导电类型掺杂次区282a、282b、282c和282d沿第一方向256的深度、沿第二方向252的宽度和掺质浓度的至少一个沿第二方向252呈线性递减。在图1所示的实施例中，第一导电类型掺杂次区280a、280b、280c和280d各自的宽度Wa、Wb、Wc、Wd沿第二方向252呈线性递减，且第二导电类型掺杂次区282a、282b、282c和282d各自的宽度Wa、Wb、Wc、Wd沿第二方向252呈线性递减。
接下来利用图2A、图2B说明图1所示实施例的超接面掺杂结构284的形成方式。图2A、图2B为图1所示的半导体装置的漂移区108的局部放大图，并显示形成漂移区108中的超接面掺杂结构284的部分工艺步骤。上述工艺于形成图1所示的隔绝结构240之前进行，因而隔绝结构240在此不予显示。
如图2A所示，可进行一微影工艺，于漂移区108中的磊晶层220的顶面221上形成一遮罩图案290。上述遮罩图案290可具有多个开口290a～290d，暴露出漂移区108中的部分第二导电类型深阱223。其中，为清楚绘示起见，此处是以4个开口(开口290a～290d)来举例，但不以此为限，在其他实施例中，也可视需要设置开口的数目。在图2A所示的一些实施例中，遮罩图案290的开口290a是设置位于接近栅极结构250，且从栅极结构250朝漏极掺杂区(由第二导电类型漂移掺杂区228、第二导电类型缓冲掺杂区227和第二导电类型接线掺杂区236构成，如图1所示)依序设置开口290b～290d。在本实施例中，分别设计上述遮罩图案290的开口290a～290d的宽度Wa、Wb、Wc、Wd依序从栅极结构250朝漏极掺杂区呈线性递减。上述遮罩图案290的开口290a～290d中任意相邻的其中两个开口中，较接近栅极结构250的开口宽度大于相对远离栅极结构250的开口宽度。举例来说，对上述遮罩图案290相邻的两个开口290a、290b而言，接近栅极结构250的开口290a的宽度Wa大于相对远离栅极结构250的开口290b的宽度Wb。上述遮罩图案290的其他相邻两个开口的宽度关系可依上述关系类推。
然后，请再参考图2A，利用上述遮罩图案290作为一遮罩进行一离子植入工艺植入第一导电类型掺质，以于开口290a～290d暴露出的第二导电类型深阱223中的部分第二导电类型深阱223中形成多个第一导电类型掺杂次区280a～280d。由于上述遮罩图案290的开口290a～290d的宽度Wa～Wd依序沿第二方向252(从栅极结构250至漏极掺杂区)呈线性递减，因此形成的第一导电类型掺杂次区280a～280d的深度及/或掺质浓度沿第二方向252呈线性递减。第一导电类型掺杂次区280a～280d中任意相邻的其中两个隔离掺杂次区中，接近栅极结构250的中心区域的第一导电类型掺杂次区的深度及/或掺质浓度可大于相对远离栅极结构250的另一个第一导电类型掺杂次区的深度及/或掺质浓度。举例来说，就相邻的两个第一导电类型掺杂次区280a、280b而言，接近栅极结构250的第一导电类型掺杂次区280a的深度及/或掺质浓度可大于相对远离栅极结构250的第一导电类型掺杂次区280b的深度及/或掺质浓度。其他相邻两个第一导电类型掺杂次区的深度关系可依上述关系类推。之后，移除遮罩图案290。
在本发明一些实施例中，第一导电类型掺杂次区280a～280d可与第一导电类型漂移掺杂区230同时形成。
接着，请参考图2B，可进行另一道微影工艺，于漂移区108中的磊晶层220的顶面221上形成一遮罩图案292。上述遮罩图案292可具有多个开口292a～292d，暴露出漂移区108中的部分第二导电类型深阱223。其中，为清楚绘示起见，此处是以4个开口(开口292a～292d)来举例，但不以此为限，在其他实施例中，也可视需要设置开口的数目。在第2B图所示的一些实施例中，遮罩图案292的开口292a～292d的宽度Wa～Wd大小关系可类似于上述遮罩图案290的开口290a～290d，在此不做重复说明。
在其他实施例中，也可设计遮罩图案292的开口具有其他的宽度，仅须符合开口宽度从栅极结构250朝漏极掺杂区呈线性递减的条件即可。
然后，请再参考图2B，利用上述遮罩图案292作为一遮罩进行一离子植入工艺植入第二导电类型掺质，以于开口292a～292d暴露出的第二导电类型深阱223中的部分第二导电类型深阱223中形成多个第二导电类型掺杂次区282a～282d。第二导电类型掺杂次区282a～282d会分别相邻第一导电类型掺杂次区280a～280d。第二导电类型掺杂次区282a～282d的深度及/或掺质浓度关系可类似于第一导电类型掺杂次区280a～280d，在此不做重复说明。之后，移除遮罩图案292。
在本发明一些实施例中，第二导电类型掺杂次区282a～282d可与第二导电类型漂移掺杂区228同时形成。
接着，进行一退火工艺，使图2B所示的第一导电类型掺杂次区280a～280d和第二导电类型掺杂次区282a～282d的掺质均匀扩散以形成具有多个PN接面的超接面掺杂结构284，如图1所示。
在本发明一些实施例中，可于例如UHV LDMOS元件的高压半导体装置500a的栅极结构250与漏极掺杂区之间设置超接面掺杂结构284，其可视为一漂移掺杂区(drift dopedregion)。上述超接面掺杂结构284的宽度、深度和掺质浓度的至少一个从栅极结构250朝向漏极掺杂区的方向(第二方向252)呈线性递减，上述设计有助于使漂移掺杂区成为完全空乏(fully depleted)达到电荷平衡，且构成一减低表面电场结构(reduced surfacefield，RESURF)，以降低UHV LDMOS元件的表面电场。并且上述超接面掺杂结构可于一固定漂移掺杂区的长度条件下同时达到高崩溃电压(breakdown voltage，BVD)和低导通电阻(on resistance，Ron)的效果。
图3显示本发明一些实施例的高压半导体装置500b的剖面示意图。在本实施例中，高压半导体装置500b可为一高压集成电路(HVIC)元件。高压半导体装置500b的主要元件可包括一基板结构300、一横向扩散金属氧化物半导体270、一超接面掺杂结构484和一接线掺杂区。上述图式中的各元件如有与图1所示相同或相似的部分，则可参考前面的相关叙述，在此不做重复说明。
如图3所示，基板结构300包括半导体基板200和全面性形成于半导体基板200的顶面211上的磊晶层220。并且，基板结构300包括一低电位区(low side region)202、一高电位区(high side region)208、及设于与低电位区202和高电位区208之间的一电位转换区(level shift region)204和一隔离区206，沿平行于磊晶层220的顶面221的一方向(例如第二方向252)由左至右依序配置。上述隔离区206位于将电位转换区204与高电位区208之间，以将电位转换区204与高电位区208彼此隔开。
如图3所示，上述高压半导体装置500b包括多个隔绝结构240，设置于磊晶层220的顶面221上，上述多个隔绝结构240分别覆盖低电位区202、电位转换区204、隔离区206和高电位区208中的磊晶层220的部分顶面221，以定义出低电位区202、电位转换区204、隔离区206和高电位区208中的多个主动区域。举例来说，隔绝结构240定义出上述低电位区202中的接线掺杂区(pick-up doped region)的形成位置，电位转换区204的LDMOS元件的栅极、源极掺杂区、漏极掺杂区的形成位置，以及高电位区208中的接线掺杂区的形成位置。
在本发明一些实施例中，上述低电位区202是用以提供低压集成电路元件(操作电压例如低于20V)形成于其上，上述高电位区208是用以提供高压集成电路元件(操作电压例如大于等于600V)形成于其上。并且，上述电位转换区204可包括横向扩散金属氧化物半导体(laterally diffused metal oxide semiconductor，以下简称LDMOS)元件270形成于其上。而隔离区206是用以在横向扩散金属氧化物半导体的栅极设于关闭状态时，电性隔离上述低电位区202和高电位区208。
上述电位转换区204的LDMOS元件270的源极S可电性耦接至低电位区202中的低压集成电路元件。并且，上述电位转换区204的LDMOS元件270的漏极D可通过跨越隔离区206的金属内连线(图未显示)电性耦接至高电位区208中的高压集成电路元件，当上述LDMOS元件的栅极是设于开通状态时，可用以将低电位区202的低电压位准转换成高电位区208的高电压位准。
如图3所示，高压半导体装置500a包括一高压第一导电类型阱222，设置于低电位区202和电位转换区204的磊晶层220中。高压第一导电类型阱222的边界可位于LDMOS元件270的一栅极结构250的正下方。高压第一导电类型阱222可用以提供LDMOS元件270的源极掺杂区和低压集成电路元件的接线掺杂区形成于其中。举例来说，当第一导电类型为P型时，上述第二导电类型为N型，上述高压第一导电类型阱222可视为高压P型阱(HVPW)222。在本发明一些实施例中，上述高压第一导电类型阱222的底面可位于磊晶层220内，或可对齐于半导体基板200和磊晶层220的交界处260(位置同半导体基板200的顶面211)。
如图3所示，高压半导体装置500b包括一高压第二导电类型阱224，设置于高电位区208中的磊晶层220内。高压第二导电类型阱224可提供高压集成电路元件的隔离掺杂区形成于其中。举例来说，当第一导电类型为P型时，上述第二导电类型为N型，上述高压第二导电类型阱224可视为高压N型阱(HVNW)224。
在本发明一些实施例中，高压半导体装置500b的低电位区202中的接线掺杂区可包括由下而上依序设置于高压第一导电类型阱222上的一第一导电类型漂移掺杂区230、一第一导电类型阱226和一第一导电类型接线掺杂区(pick-up doped region)234。举例来说，当第一导电类型为P型时，上述第一导电类型漂移掺杂区230可视为P型漂移掺杂区(P-drift doped region)230，上述第一导电类型阱226可视为P型阱226，而上述第一导电类型接线掺杂区234可视为P型接线掺杂区234。
在本发明一些实施例中，上述第一导电类型接线掺杂区234的掺杂浓度大于第一导电类型阱226的掺杂浓度，第一导电类型阱226的掺杂浓度大于P型漂移掺杂区230的掺杂浓度，且P型漂移掺杂区230的掺杂浓度大于高压第一导电类型阱222的掺杂浓度。
在本发明一些实施例中，高压半导体装置500b的高电位区208中的接线掺杂区中可包括由下而上依序设置于高压第二导电类型阱224上的第二导电类型漂移掺杂区238和第二导电类型接线掺杂区236。举例来说，当第一导电类型为P型时，第二导电类型为N型，上述第二导电类型漂移掺杂区238可视为N型漂移掺杂区N型阱/N型漂移掺杂区(NW/N-driftdoped region)238，且上述第二导电类型接线掺杂区236可视为N型接线掺杂区236。
在本发明一些实施例中，上述磊晶层220的掺杂浓度低于述高压第二导电类型阱224的掺杂浓度，上述高压第二导电类型阱224的掺杂浓度低于上述第二导电类型漂移掺杂区238的掺杂浓度，且上述第二导电类型漂移掺杂区238的掺杂浓度低于第二导电类型接线掺杂区236的掺杂浓度。在本发明一些实施例中，第二导电类型漂移掺杂区228和第二导电类型漂移掺杂区238可于同一工艺步骤形成，或于不同工艺步骤形成。
如图3所示，在高压半导体装置500b中，LDMOS元件270的源极掺杂区横跨设置于低电位区202和电位转换区204。源极掺杂区可包括由下而上依序设置于高压第一导电类型阱222上的一第二导电类型漂移掺杂区228、第二导电类型缓冲掺杂区227和第二导电类型接线掺杂区236。举例来说，当第一导电类型为P型时，第二导电类型为N型，上述第二导电类型漂移掺杂区228可视为N型漂移掺杂区(N-drift doped region)228，上述第二导电类型缓冲掺杂区227可视为N型缓冲掺杂区227，且上述第二导电类型接线掺杂区236可视为N型接线掺杂区236。
如图3所示，在高压半导体装置500b中，LDMOS元件270的漏极掺杂区设置于电位转换区204中，且接近于电位转换区204和隔离区206的交界处。漏极掺杂区可包括由下而上依序设置于磊晶层220中的一第二导电类型漂移掺杂区228、一第二导电类型缓冲掺杂区227和一第二导电类型接线掺杂区236。举例来说，当第一导电类型为P型时，第二导电类型为N型，上述第二导电类型漂移掺杂区228可视为N型漂移掺杂区(N-drift doped region)228，上述第二导电类型缓冲掺杂区227可视为N型缓冲掺杂区227，且上述第二导电类型接线掺杂区236可视为N型接线掺杂区236。
如图3所示，在高压半导体装置500b中，LDMOS元件270的栅极结构250设置于磊晶层220的顶面221上，且位于电位转换区204中。LDMOS元件270的源极掺杂区和漏极掺杂区分别位于栅极结构250的相反侧。上述栅极结构250覆盖位于高压第一导电类型阱222和磊晶层220上的部分隔绝结构240，且覆盖高压第一导电类型阱222和其上的第二导电类型漂移掺杂区228(低电位区202和栅极结构250之间)。上述栅极结构250通过另一个隔绝结构240(栅极结构250和高电位区208之间)与漏极掺杂区的第二导电类型漂移掺杂区228相隔一距离。
在本发明一些实施例中，高压半导体装置500b可包括多个第二导电类型埋藏掺杂层212，设置接近隔离区206的高电位区208的部分半导体基板200内，以及接近隔离区206和电位转换区204之间的部分半导体基板200内。并且，第二导电类型埋藏掺杂层212会扩散延伸进入磊晶层220中。上述第二导电类型埋藏掺杂层212具有一第二导电类型，且第二导电类型不同于第一导电类型。举例来说，当第一导电类型为P型时，上述第二导电类型为N型，且第二导电类型埋藏掺杂层212可视为一N型埋藏掺杂层。
接下来利用第3图说明高压半导体装置500b的一超接面掺杂结构484的形成位置。上述超接面掺杂结构484位于隔离区206中的隔绝结构240下方，且位于磊晶层220中，且分别与LDMOS元件270的漏极掺杂区和高电位区208的接线掺杂区隔开。超接面掺杂结构484可作为高压半导体装置500b的隔离掺杂区。在本发明一些实施例中，超接面掺杂结构484包括多个第一导电类型掺杂次区480a、480b和480c，以及多个第二导电类型掺杂次区482a、482b和482c。第一导电类型掺杂次区480a、480b和480c具有第一导电类型。第一导电类型掺杂次区480a、480b和480c沿一第一方向256(意即基板结构300的顶面(位置相同于磊晶层220的顶面221)的一法线方向)延伸且沿一第二方向(从接近超接面掺杂结构484的一中心区域至接近超接面掺杂结构484的一外围区域的方向)设置。另外，第二导电类型掺杂次区482a、482b和482c具有第二导电类型，沿第一方向256延伸且沿第二方向(从接近超接面掺杂结构484的中心区域至接近超接面掺杂结构484的外围区域的方向)与第一导电类型掺杂次区480a、480b和480c交错设置。
在如图3所示的剖面图中，第一导电类型掺杂次区480a、480b和480c和第二导电类型掺杂次区482a、482b和482c具有且为沿第一方向256延伸的长条柱状。值得注意的是，上述第一方向256实质平行于基板结构300的顶面221的法线方向，而第二方向实质平行于从接近超接面掺杂结构484的中心区域至接近超接面掺杂结构484的外围区域的方向。
如图3所示，第二导电类型掺杂次区482a的相反两侧分别邻接两个第一导电类型掺杂次区480a和480b，第一导电类型掺杂次区480b的相反两侧分别邻接两个第二导电类型掺杂次区482a、482b。上述第一导电类型掺杂次区和第二导电类型掺杂次区的邻接关系可依上述关系类推。然而，在其他实施例中，第一导电类型掺杂次区480a、480b和480c的位置可与第二导电类型掺杂次区482a、482b和482c互换。
在本发明一些实施例中，在超接面掺杂结构484中，可设计第一导电类型掺杂次区480a、480b和480c沿第一方向256的深度、沿第二方向(从接近超接面掺杂结构484的中心区域至接近超接面掺杂结构484的外围区域)的宽度和掺质浓度的至少一个沿第二方向呈线性递减。类似地，第二导电类型掺杂次区482a、482b和482c沿第一方向256的深度、沿第二方向(从接近超接面掺杂结构484的中心区域至接近超接面掺杂结构484的外围区域)的宽度和掺质浓度的至少一个沿第二方向呈线性递减。在图1所示的实施例中，第一导电类型掺杂次区480a、480b和480c各自的宽度沿第二方向呈线性递减，且第二导电类型掺杂次区482a、482b和482c各自的宽度沿第二方向呈线性递减。而且，超接面掺杂结构484的底面对齐于磊晶层220的一底面(位置相同于半导体基板200的顶面211)。在本发明一些其他实施例中，超接面掺杂结构484的最低处可以在磊晶层的底面的上方(即为不与半导体基板200的顶面211接触)。
接下来利用图4A、图4B说明图3所示实施例的超接面掺杂结构484的形成方式。图4A、图4B为图3所示的高压半导体装置的隔离区206的局部放大图，并显示形成隔离区206中的超接面掺杂结构484的部分工艺步骤。上述工艺于形成图3所示的隔绝结构240之前进行，因而隔绝结构240在此不予显示。
如图4A所示，可进行一微影工艺，于隔离区206中的磊晶层220的顶面221上形成一遮罩图案490。上述遮罩图案490可具有多个开口490a～490c。遮罩图案490的开口480a是设置位于接近隔离区206的一中心区域，且从隔离区206的中心区域朝隔离区206的一外围区域(例如接近隔离区206与电位转换区204的交界处和隔离区206与高电位区208的交界处，如图1所示)依序设置开口490b～490c。并且，分别设计上述遮罩图案490的开口490a～490c的宽度W1～W3依序从接近隔离区206的中心区域至接近隔离区206的一外围区域呈线性递减。上述遮罩图案490的开口490a～490c中任意相邻的其中两个开口中，较接近隔离区206的中心区域大于相对远离隔离区206的中心区域的开口宽度。
然后，利用上述遮罩图案490作为一遮罩进行一离子植入工艺，以于开口490a～490c暴露出的隔离区206中的部分磊晶层220中植入第一导电类型掺质，以形成多个第一导电类型掺杂次区480a、480b和480c。由于上述遮罩图案490的开口490a～490c的宽度W1～W3依序从接近隔离区206的中心区域至外围区域呈线性递减，因此形成的第一导电类型掺杂次区480a、480b和480c的深度及/或掺质浓度从接近从隔离区206的中心区域朝隔离区206的外围区域(例如接近隔离区206与电位转换区204的交界处和隔离区206与高电位区208的交界处)呈线性递减。在本发明一些其他实施例中，相邻的两个隔离掺杂次区是彼此部分重叠。之后，移除遮罩图案490。
在本发明一些实施例中，第一导电类型掺杂次区480a、480b和480c可与高压第一导电类型阱222同时形成。
接着，如图4B所示，可进行另一微影工艺，于隔离区206中的磊晶层220的顶面221上形成另一遮罩图案492。上述遮罩图案492可具有多个开口492a～492c。在图4B所示的一些实施例中，遮罩图案492的开口492a～492c的宽度W1～W3大小关系可类似于上述遮罩图案490的开口490a～490c，在此不做重复说明。
在其他实施例中，也可设计遮罩图案492的开口具有其他的宽度，仅须符合开口宽度从接近隔离区206的中心区域至外围区域呈线性递减的条件即可。
然后，请再参考图4B，利用上述遮罩图案492作为一遮罩进行一离子植入工艺植入第二导电类型掺质，以于开口492a～492c暴露出的磊晶层220中形成多个第二导电类型掺杂次区482a、482b和482c。第二导电类型掺杂次区482a、482b和482c会分别相邻第一导电类型掺杂次区480a、480b和480c。第二导电类型掺杂次区482a、482b和482c的深度及/或掺质浓度关系可类似于第一导电类型掺杂次区480a、480b和480c，在此不做重复说明。之后，移除遮罩图案492。
在本发明一些实施例中，第二导电类型掺杂次区492a、492b和492c可与高压第二导电类型阱224同时形成。
接着，进行一退火工艺，使图4B所示的第一导电类型掺杂次区480a～480c和第二导电类型掺杂次区482a～482c的掺质均匀扩散以形成具有多个PN接面的超接面掺杂结构484，如图3所示。
在本发明一些实施例中，可于例如高压集成电路(HVIC)元件的高压半导体装置500b的隔离区内设置超接面掺杂结构484，其可视为用以电性隔绝高电位区208和低电位区202的一隔绝掺杂区。上述超接面掺杂结构484的第一导电类型掺杂次区和第二导电类型掺杂次区的宽度、深度和掺质浓度的至少一个从接近超接面掺杂结构484(或隔离区206)的一中心区域至接近超接面掺杂结构484的一外围区域呈线性递减，上述设计有助于使超接面掺杂结构成为完全空乏(fully depleted)达到电荷平衡，且可使高压半导体的表面电场均匀分布，因而可提升高压集成电路的崩溃电压(breakdown voltage，BVD)。另一方面，上述超接面掺杂结构可在提升崩溃电压要求的同时增加其在高电位区和低电位区的有效宽度，所以可具有足够浓的表面掺质浓度，进一步抑制横向漏电现象(lateral punch-throughleakage current)。
虽然本发明已以实施例揭露于上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视权利要求书所界定的为准。

Claims (10)

1.一种高压半导体装置，其特征在于，所述的高压半导体装置包括：
一基板结构；
一栅极结构，位于所述基板结构上；
一漏极掺杂区，位于所述基板结构内，且接近所述栅极结构的一第一侧；以及
一超接面掺杂结构，位于所述基板结构内，且接近所述漏极掺杂区，其中所述超接面掺杂结构包括：
多个第一导电类型掺杂次区，具有一第一导电类型，所述多个第一导电类型掺杂次区沿一第一方向延伸且沿一第二方向设置；以及
多个第二导电类型掺杂次区，具有相反于所述第一导电类型的一第二导电类型，所述多个第二导电类型掺杂次区沿所述第一方向延伸且沿所述第二方向与所述多个第一掺杂部分交错设置，
其中所述多个第一导电类型掺杂次区各自沿所述第二方向的宽度沿所述第二方向呈线性递减，和其中所述多个第二导电类型掺杂次区各自沿所述第二方向的宽度沿所述第二方向呈线性递减。
2.如权利要求1所述的高压半导体装置，其特征在于，所述多个第一导电类型掺杂次区各自沿所述第一方向的深度沿所述第二方向呈线性递减，或其中所述多个第二导电类型掺杂次区各自沿所述第一方向的深度沿所述第二方向呈线性递减。
3.如权利要求1所述的高压半导体装置，其特征在于，所述多个第一导电类型掺杂次区各自的掺质浓度沿所述第二方向呈线性递减，或其中所述多个第二导电类型掺杂次区各自的掺质浓度沿所述第二方向呈线性递减。
4.如权利要求1所述的高压半导体装置，其特征在于，所述基板结构包括：
一半导体基板，具有一第一导电类型；
一磊晶层，设于所述半导体基板上，其中所述磊晶层具有一第二导电类型，且所述第一导电类型与所述第二导电类型不同。
5.如权利要求4所述的高压半导体装置，其特征在于，所述的高压半导体装置更包括：
一源极掺杂区，位于所述基板结构内，且接近所述栅极结构的相反于所述第一侧的一第二侧，所述基板结构具有一顶面，所述源极掺杂区、闸极结构、汲极掺杂区皆在所述顶面。
6.如权利要求5所述的高压半导体装置，其特征在于，所述基板结构包括：
一高电位区；
一低电位区，其与所述高电位区彼此隔开；以及
一电位转换区和一隔离区，设置于所述高电位区与所述低电位区之间，其中所述隔离区将所述电位转换区与所述高电位区彼此隔开；
其中所述超接面掺杂结构位于所述隔离区中。
7.一种高压半导体装置，其特征在于，所述的高压半导体装置包括：
一基板结构；
一栅极结构，位于所述基板结构上；
一漏极掺杂区，位于所述基板结构内，且接近所述栅极结构的一第一侧；以及
一超接面掺杂结构，位于所述基板结构内，且接近所述漏极掺杂区，其中所述超接面掺杂结构包括：
多个第一导电类型掺杂次区，具有一第一导电类型，所述多个第一导电类型掺杂次区沿一第一方向延伸且沿一第二方向设置；以及
多个第二导电类型掺杂次区，具有相反于所述第一导电类型的一第二导电类型，所述多个第二导电类型掺杂次区沿所述第一方向延伸且沿所述第二方向与所述多个第一掺杂部分交错设置，
其中所述多个第一导电类型掺杂次区各自沿所述第一方向的深度、沿所述第二方向的宽度和掺质浓度的至少一个沿所述第二方向呈线性递减。
8.如权利要求7所述的高压半导体装置，其特征在于，所述第一方向平行于所述基板结构的一顶面的一法线方向，所述第二方向平行于所述栅极结构朝向所述漏极掺杂区的一方向。
9.一种高压半导体装置，其特征在于，所述的高压半导体装置包括：
一基板结构；
一栅极结构，位于所述基板结构上；
一漏极掺杂区，位于所述基板结构内，且接近所述栅极结构的一第一侧；以及
一超接面掺杂结构，位于所述基板结构内，且接近所述漏极掺杂区，其中所述超接面掺杂结构包括：
彼此相邻的一第一导电类型掺杂次区和一第二导电类型掺杂次区，所述第一导电类型掺杂次区具有一第一导电类型，所述第二导电类型掺杂次区具有相反于所述第一导电类型的一第二导电类型，其中所述第一导电类型掺杂次区和所述第二导电类型掺杂次区沿一第一方向延伸且沿一第二方向设置，
其中所述第一导电类型掺杂次区和所述第二导电类型掺杂次区沿所述第一方向的深度、沿所述第二方向的宽度和掺质浓度的至少一个沿所述第二方向彼此不同。
10.如权利要求9所述的高压半导体装置，其特征在于，所述超接面掺杂结构包括：
另一第二导电类型掺杂次区，相邻于所述第一导电类型掺杂次区，且与所述第二导电类型掺杂次区分别位于所述第一导电类型掺杂次区的相反侧，其中所述第一导电类型掺杂次区和所述另一第二导电类型掺杂次区沿所述第一方向的深度、沿所述第二方向的宽度和掺质浓度的至少一个彼此相同。
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