CN108242468B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN108242468B
CN108242468B CN201711204360.3A CN201711204360A CN108242468B CN 108242468 B CN108242468 B CN 108242468B CN 201711204360 A CN201711204360 A CN 201711204360A CN 108242468 B CN108242468 B CN 108242468B
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CN108242468A (zh
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苏布
陈鲁夫
陈柏安
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Nuvoton Technology Corp
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Abstract

本发明提供一种半导体装置及其制造方法。半导体装置包括基板，具有第一导电类型。磊晶层，设于基板上且具有第二导电类型。第二导电类型第一埋藏层，设置于基板的高电位区中，第二导电类型第一埋藏层具有第二导电类型。第二导电类型第二埋藏层，位于第二导电类型第一埋藏层的正上方，第二导电类型第二埋藏层具有第二导电类型。第二导电类型第一埋藏层的顶面与第二导电类型第二埋藏层的顶面分别与磊晶层的顶面相距不同距离。第二导电类型第一埋藏层的掺质浓度小于第二导电类型第二埋藏层的掺质浓度。

Description

半导体装置及其制造方法
技术领域
本发明是有关于一种半导体装置及其制造方法，特别是有关于一种高压半导体装置及其制造方法，具体的讲是一种半导体装置及其制造方法。
背景技术
高压集成电路(HVIC)因具有符合成本效益且易相容于其它制作工艺等优点，因而已广泛应用于发光二极管(LED)、显示器驱动集成电路元件、电源供应器、电力管理、通讯、车用电子的电源控制系统中。然而，现有技术的高压集成电路会因为闭锁效应(latch up)、低击穿电压、低元件切换速度及较大的元件面积等问题而无法进一步的改善。
因此，在此技术领域中，有需要一种高压半导体装置，以改善上述缺点。
发明内容
本发明的一实施例提供一种半导体装置。上述半导体装置包括一基板，具有一第一导电类型，上述基板包括：一高电位区；一低电位区，其与上述高电位区彼此隔开；以及一电位转换区和一隔离区，设于上述高电位区与上述低电位区之间，其中上述隔离区将上述电位转换区与上述高电位区彼此隔开；一磊晶层，设于上述基板上，其中上述磊晶层具有一第二导电类型，且上述第一导电类型与上述第二导电类型不同；一第二导电类型第一埋藏层，设置于上述高电位区中，其中上述第二导电类型第一埋藏层具有上述第二导电类型；一第二导电类型第二埋藏层，设置于上述第二导电类型第一埋藏层的正上方，其中上述第二导电类型第二埋藏层具有上述第二导电类型，其中上述第二导电类型第一埋藏层的一顶面与上述第二导电类型第二埋藏层的一顶面分别与上述磊晶层的一顶面相距不同距离，且其中上述第二导电类型第一埋藏层的掺质浓度小于上述第二导电类型第二埋藏层的掺质浓度。
本发明的另一实施例提供一种半导体装置的制造方法。上述半导体装置的制造方法包括提供一基板，具有一第一导电类型，上述基板包括：一高电位区；一低电位区，其与上述高电位区彼此隔开；以及一电位转换区和一隔离区，设于上述高电位区与上述低电位区之间，其中上述隔离区将上述电位转换区与上述高电位区彼此隔开；进行一第一离子植入制作工艺，于上述高电位区中的上述基板内形成一第二导电类型第一埋藏层，其中上述第二导电类型第一埋藏层具有一第二导电类型，且上述第一导电类型与上述第二导电类型不同；进行一第二离子植入制作工艺，于上述第二导电类型第一埋藏层的正上方形成一第二导电类型第二埋藏层，其中上述第二导电类型第二埋藏层具有上述第二导电类型；以及进行一磊晶成长制作工艺，于上述基板上形成一磊晶层，其中上述磊晶层具有上述第二导电类型，其中形成上述磊晶层之后，上述第二导电类型第二埋藏层扩散延伸进入上述磊晶层中。
附图说明
图1～图4显示本发明一些实施例的半导体装置的制作工艺剖面示意图。
【符号说明】
500～半导体装置；
200～基板；
202～低电位区；
204～电位转换区；
206～隔离区；
208～高电位区；
210～第二导电类型第一埋藏掺杂区；
211、213、217、221～顶面；
212～第二导电类型第一埋藏层；
212A～第一掺质；
214～第二导电类型第二埋藏层；
214A～第二掺质；
215、216～边缘；
220～磊晶层；
222～高压第一导电类型井区；
224～高压第二导电类型井区；
226～第一导电类型井区；
228～第二导电类型漂移掺杂区；
230～第一导电类型漂移掺杂区；
234～第一导电类型接线掺杂区；
236～第二导电类型接线掺杂区；
240～隔绝结构；
250～栅极结构；
260～交界处；
270～横向扩散金属氧化物半导体；
300、304～遮罩图案；
302、306～离子植入制作工艺；
W1～第一宽度；
W2～第二宽度；
D1、D2～距离。
具体实施方式
为了让本发明的目的、特征、及优点能更明显易懂，下文特举实施例，并配合所附图示，做详细的说明。本发明说明书提供不同的实施例来说明本发明不同实施方式的技术特征。其中，实施例中的各元件的配置为说明之用，并非用以限制本发明。且实施例中图式标号的部分重复，为了简化说明，并非意指不同实施例之间的关联性。
本发明实施例提供用于高压集成电路(HVIC)的一种半导体装置。上述于半导体装置的高电位区内的基板中设置由不同道离子植入制作工艺形成一N型深埋藏层(N-typeburier layer)和一N型浅埋藏层，其中N型深埋藏层设置于N型浅埋藏层的正下方，且上述N型深埋藏层的掺杂浓度设计小于N型浅埋藏层的掺杂浓度。此处的“深”和“浅”意指埋藏层的顶面距离半导体装置的一磊晶层的顶面的距离大小。举例来说，N型深埋藏层的顶面与半导体装置的磊晶层的顶面之间相距的距离大于N型浅埋藏层的顶面与半导体装置的磊晶层的顶面之间相距的距离。并且，用于形成上述N型深埋藏层和N型浅埋藏层使用的两道不同离子植入制作工艺的掺质剂量皆小于1014cm-2，因而在形成浓度较浓的N型浅埋藏层时不会影响元件表面掺杂轮廓(doping profile)。此外，上述N型深埋藏层和N型浅埋藏层可有效抑制高压集成电路的高电位区(high side region)中的垂直方向的击穿效应。
图1～图4显示本发明一些实施例的半导体装置500的制作工艺剖面示意图。请参考图1，首先提供基板200，上述基板200掺杂掺质以具有第一导电类型。举例来说，当第一导电类型为P型时，上述基板200可为一P型基板。在本发明一些实施例中，基板200的掺杂浓度可为约1x1011-1x1015/cm3，因而基板200可视为一轻掺杂P型基板200。此处的“轻掺杂”意指掺杂浓度小于1x1015/cm3。在本发明一些实施例中，上述基板200可为硅基板。在本发明其他实施例中，可利用锗化硅(SiGe)、块状半导体(bulk semiconductor)、应变半导体(strained semiconductor)、化合物半导体(compound semiconductor)，或其他常用的半导体基板做为基板200。
如图1所示，基板200包括一低电位区(low side region)202、一高电位区(highside region)208、及设于与低电位区202和高电位区208之间的一电位转换区(levelshift region)204和一隔离区206。上述隔离区206位于电位转换区204与高电位区208之间，以将电位转换区204与高电位区208彼此隔开。在如图1所示的一些实施例中，上述低电位区202、电位转换区204、隔离区206和高电位区208沿平行于基板200的一顶面211的一方向由左至右依序配置。
在本发明一些实施例中，上述低电位区202用以提供低压集成电路元件(操作电压例如低于20V)形成于其上，上述高电位区208用以提供高压集成电路元件(操作电压例如大于等于600V)形成于其上。并且，上述电位转换区204可包括横向扩散金属氧化物半导体(laterally diffused metal oxide semiconductor，以下简称LDMOS)元件形成于其上。而隔离区206用以在横向扩散金属氧化物半导体的栅极设于关闭状态时，电性隔离上述低电位区202和高电位区208。
上述电位转换区204的LDMOS元件的源极可电性耦接至低电位区202中的低压集成电路元件。并且，上述电位转换区204的LDMOS元件的汲极可藉由跨越隔离区206的金属内连线(图未显示)电性耦接至高电位区208中的高压集成电路元件，当上述LDMOS元件的栅极设于开通状态时，可用以将低电位区202的低电压位准转换成高电位区208的高电压位准。
请参考图2，可进行一微影制作工艺，于基板200的顶面211上形成一遮罩图案300，上述遮罩图案300可暴露出部分高电位区208中的基板200，并定义出后续的第二导电类型第一埋藏层区210的形成区域。值得注意的是，遮罩图案300并未暴露出低电位区202、电位转换区204和隔离区206中的基板200。然后，以上述遮罩图案300为罩幕，进行一离子植入制作工艺302，于高电位区208中的基板200内植入第一掺质212A以形成一第二导电类型第一埋藏掺杂区210。之后，移除遮罩图案300。上述第二导电类型第一埋藏掺杂区210具有一第二导电类型，且第二导电类型不同于第一导电类型。举例来说，当第一导电类型为P型时，上述第二导电类型为N型，且第二导电类型第一埋藏掺杂区210可视为一N型埋藏掺杂区210。
如图2所示，值得注意的是，上述离子植入制作工艺302仅于高电位区208中的基板200内植入第一掺质212A以形成第二导电类型第一埋藏掺杂区210，但未同时于上述低电位区202、电位转换区204、隔离区206内植入第一掺质212A以形成其他的第二导电类型埋藏掺杂区。上述第二导电类型第一埋藏掺杂区210完全位于高电位区208中。换句话说，上述第二导电类型第一埋藏掺杂区210的边缘215完全位于高电位区208中。
在本发明一些实施例中，上述离子植入制作工艺302使用的第一掺质212A可包括磷(P)。上述离子植入制作工艺302使用的掺杂剂量范围可为1x1011-5x1013/cm2，因此形成的上述第二导电类型第一埋藏层210的掺杂浓度范围可为1x1015-5x1018/cm3。进行上述离子植入制作工艺302之后，可进行一退火制作工艺以活化第一掺质212A且使上述第二导电类型第一埋藏掺杂区210内的第一掺质212A分布均匀。
接着，请参考图3，可进行另一微影制作工艺，于基板200的顶面211上形成一遮罩图案304，上述遮罩图案304可暴露出部分高电位区208中的基板200，并定义出后续的第二导电类型第二埋藏层的形成区域。上述遮罩图案304可完全暴露出第二导电类型第一埋藏掺杂区210。值得注意的是，遮罩图案304并未暴露出低电位区202、电位转换区204和隔离区206中的基板200。然后，以上述遮罩图案304为罩幕，进行另一离子植入制作工艺306，于高电位区208中的基板200内植入第二掺质214A，改变接近基板200的顶面211的部分第二导电类型第一埋藏掺杂区210的掺质浓度，以将图2所示的第二导电类型第一埋藏掺杂区210转变成一第二导电类型第一埋藏层212，并于上述第二导电类型第一埋藏层212的正上方形成一第二导电类型第二埋藏层214。之后，移除遮罩图案304。上述第二导电类型第二埋藏层214具有第二导电类型。举例来说，当第一导电类型为P型时，上述第二导电类型为N型，且上述第二导电类型第一埋藏层212和第二导电类型第二埋藏层214可分别视为N型埋藏层212和N型埋藏层214。在本发明一些实施例中，进行离子植入制作工艺302和306之后形成的上述第二导电类型第一埋藏层212的顶面213低于基板200的顶面211。
如图3所示，值得注意的是，上述离子植入制作工艺302仅于高电位区208中的基板200内植入第二掺质212A以形成第二导电类型第二埋藏层212，但未同时于上述低电位区202、电位转换区204、隔离区206内植入第二掺质212A以形成其他的第二导电类型埋藏层。上述第二导电类型第一埋藏层212完全位于高电位区208中。换句话说，上述第二导电类型第一埋藏层212的边缘215完全位于高电位区208中。
在图3所示的本发明实施例中，离子植入制作工艺302使用的第一掺质212A和离子植入制作工艺306使用的第二掺质214A可属于相同的掺质族群(例如第VA族)。值得注意的是，离子植入制作工艺302使用的第一掺质212A和离子植入制作工艺306使用的第二掺质214A为不同的掺质。详细来说，上述第一掺质212A的原子量小于第二掺质214A的原子量。另外，上述第一掺质212A的扩散系数(diffusivity)大于第二掺质214A的扩散系数。举例来说，当第一掺质212A为磷(P)时，第二掺质214A为砷(As)。
在图3所示的本发明实施例中，用以形成第二导电类型第二埋藏层214的离子植入制作工艺306使用的掺杂剂量设计大于用以形成第二导电类型第一埋藏掺杂210(如图2所示)的离子植入制作工艺302使用的掺杂剂量。举例来说，离子植入制作工艺306使用的掺杂剂量范围可为1x1013-1x1015/cm2，例如为5x1013/cm2。值得注意的是，进行两道离子植入制作工艺302和306之后形成的第二导电类型第二埋藏层214的掺杂浓度范围可为1x1017-1x1020/cm3，而进行两道离子植入制作工艺302和306之后形成的第二导电类型第一埋藏层212的掺杂浓度范围为1x1015-1x1018/cm3。换句话说，进行两道离子植入制作工艺302和306之后形成的第二导电类型第二埋藏层214的掺杂浓度大于进行两道离子植入制作工艺302和306之后形成的第二导电类型第一埋藏层212的掺杂浓度约一～二个数量级。
值得注意的是，在本发明一些实施例中，用以形成第二导电类型第一埋藏层212和第二导电类型第二埋藏层214两者使用的两道离子植入制作工艺302和306的掺质剂量皆小于5x1018cm-3，因而不会影响最终形成的半导体装置的元件表面掺杂浓度。
由于上述第二导电类型第一埋藏层212和第二导电类型第二埋藏层214两者的掺质原子量不同。相较于第二导电类型第一埋藏层212，位于其下方的第二导电类型第一埋藏层212具有较轻的掺质，因而具有较大的扩散系数。因此，上述第二导电类型第一埋藏层212的和第二导电类型第二埋藏层214两者可设计具有不同的宽度。举例来说，上述第二导电类型第一埋藏层212具有一第一宽度W1，第二导电类型第二埋藏层214具有一第二宽度W2，且第二宽度W2大于第一宽度W1。
进行如图3所示的上述离子植入制作工艺306之后，可进行另一退火制作工艺以活化第二掺质214A且使上述第二导电类型第二埋藏层214的掺杂浓度分布均匀。在本发明一些实施例中，上述第二导电类型第二埋藏层214的底面与上述第二导电类型第一埋藏层212的顶面213直接接触。且于进行如如图3所示的制作工艺步骤之后，上述第二导电类型第二埋藏层214的的顶面实质上与基板200的顶面211共平面。
接着，如图4所示，进行一磊晶成长(epitaxial growth)制作工艺，以于基板200的顶面211上全面性形成一磊晶层220。上述磊晶成长制作工艺可包括例如金属有机物化学气相沉积法(MOCVD)、金属有机物化学气相磊晶法(MOVPE)、电浆增强型化学气相沉积法(plasma-enhanced CVD)、遥控电浆化学气相沉积法(RP-CVD)、分子束磊晶法(MBE)、氢化物气相磊晶法(HVPE)、液相磊晶法(LPE)、氯化物气相磊晶法(Cl-VPE)或类似的方法。在本发明一些实施例中，可于进行磊晶成长制作工艺时，于反应气体中加入磷化氢(phosphine)或砷化三氢(arsine)进行原位(in-situ)掺杂以形成上述第二导电类型磊晶层206。本发明一些实施例中，可先磊晶成长未掺杂的磊晶层(图未显示)，之后再以磷离子或砷离子掺杂上述未掺杂的磊晶层以形成磊晶层220。
上述磊晶层220的材质可包括硅、锗、硅与锗、III-V族化合物或上述的组合。上述磊晶层220具有一第二导电类型，且第二导电类型不同于第一导电类型。举例来说，当第一导电类型为P型时，上述第二导电类型为N型，且磊晶层220可视为一N型磊晶层220。在本发明一些实施例中，磊晶层220可具有例如磷(P)的掺质，且磊晶层220的厚度范围可为2μm至8μm。
在进行上述磊晶成长制作工艺以形成磊晶层220的期间，上述第二导电类型第二埋藏层214扩散延伸进入磊晶层220中。意即形成磊晶层220之后，第二导电类型第二埋藏层214的一顶面217可位于基板200的顶面211上方。
如图4所示，第二导电类型第一埋藏层212的顶面213与第二导电类型第二埋藏层214的顶面217分别与磊晶层220的一顶面221相距不同距离。详细来说，第二导电类型第一埋藏层212的顶面213与磊晶层220的顶面221相距一距离D1，第二导电类型第二埋藏层214的顶面217与磊晶层220的顶面221相距一距离D2，且距离D1大于距离D2。
接着，如图4所示，进行数道离子植入制作工艺，以分别于低电位区202、电位转换区204、隔离区206和高电位区208内的磊晶层220中植入不同的掺质，以于低电位区202、电位转换区204和隔离区206内的磊晶层220中形成高压第一导电类型井区222，且于高电位区208中的磊晶层220内形成一高压第二导电类型井区224。举例来说，当第一导电类型为P型时，上述第二导电类型为N型，上述高压第一导电类型井区222可视为高压P型井区(HVPW)222，且上述高压第二导电类型井区224可视为高压N型井区(HVNW)224。在本发明一些实施例中，上述高压第一导电类型井区222和高压第二导电类型井区224的底面可位于磊晶层220内，且可对齐于基板200和磊晶层220的交界处260(位置同基板200的顶面211)。
接着，如图4所示，进行数道离子植入制作工艺，以分别于低电位区202、电位转换区204、隔离区206和高电位区208内的磊晶层220中植入不同的掺质，以于低电位区202和隔离区206内的磊晶层220中形成第一导电类型漂移掺杂区230，且于低电位区202、电位转换区204和高电位区208中的磊晶层220内形成一第二导电类型漂移掺杂区228。举例来说，当第一导电类型为P型时，上述第二导电类型为N型，上述第一导电类型漂移掺杂区230可视为P型漂移掺杂区(P-drift doped region)230，上述第二导电类型漂移掺杂区228可视为N型漂移掺杂区(N-drift doped region)228。
接着，如图4所示，进行一或多道离子植入制作工艺，以分别于低电位区202和高电位区208内的磊晶层220中植入掺质，以于低电位区202和高电位区208内的磊晶层220中形成第一导电类型井区226。举例来说，当第一导电类型为P型时，上述第一导电类型井区226可视为P型井区226。
在本发明一些实施例中，上述高压第一导电类型井区222的掺杂浓度低于上述第一导电类型漂移掺杂区230的掺杂浓度，且上述第一导电类型漂移掺杂区230的掺杂浓度低于第一导电类型井区226的掺杂浓度。上述磊晶层220的掺杂浓度低于上述高压第二导电类型井区224，上述高压第二导电类型井区224的的掺杂浓度低于上述第二导电类型漂移掺杂区228。
接着，如图4所示，可于磊晶层220的顶面221上形成一垫氧化层(图未显示)以及一垫氮化硅层(图未显示)，之后蚀刻垫氧化层以及垫氮化硅层以定义出低电位区202、电位转换区204、隔离区206和高电位区208中的多个主动区域。接着，可利用局部热氧化法，于磊晶层220的顶面221上形成多个隔绝结构240。如图4所示，上述多个分别隔绝结构232覆盖低电位区202、电位转换区204和隔离区206中的基板200的部分顶面221。举例来说，隔绝结构240定义出上述低电位区202中的接线掺杂区(pick-up doped region)的形成位置，电位转换区204的LDMOS元件的栅极、源极掺杂区、汲极掺杂区的形成位置，以及高电位区208中的接线掺杂区的形成位置。
然后，如图4所示，于电位转换区204内的磊晶层220的顶面221上形成一栅极结构250，上述栅极结构250覆盖位于高压第一导电类型井区222和第二导电类型漂移掺杂区228上的部分隔绝结构240，且覆盖高压第一导电类型井区222和其中一个第二导电类型漂移掺杂区228(低电位区202和栅极结构250之间)。上述栅极结构250藉由另一个隔绝结构240(栅极结构250和高电位区208之间)与其中另一个第二导电类型漂移掺杂区228相隔一距离。形成上述栅极结构250的方式包括进行例如化学气相沉积法(CVD)或原子层沉积法(ALD)的一薄膜沉积制作工艺，于磊晶层220的顶面221上顺应性形成一栅极绝缘材料(图未显示)。接着，进行包括物理气相沉积法(PVD)、化学气相沉积法(CVD)或原子层沉积法(ALD)或其他类似方式的一薄膜沉积制作工艺，于上述栅极绝缘材料上全面性形成一栅极导电材料。然后，进行一图案化制作工艺，移除部分栅极导电材料和栅极绝缘材料，以形成上述栅极结构250。
接着，如图4所示，再进行数道离子植入制作工艺，以分别于低电位区202、电位转换区204和高电位区208内的磊晶层220中植入不同的掺质，以于低电位区202中的磊晶层220内的第一导电类型井区226上形成第一导电类型接线掺杂区(pick-up doped region)234，且于电位转换区204和高电位区208中的磊晶层220内的不同的第二导电类型漂移掺杂区228上分别形成第二导电类型接线掺杂区236。举例来说，当第一导电类型为P型时，第二导电类型为N型，上述第一导电类型接线掺杂区234可视为P型接线掺杂区234，上述第二导电类型接线掺杂区236可视为N型接线掺杂区236。
在本发明一些实施例中，上述第一导电类型接线掺杂区234的掺杂浓度大于第一导电类型井区226的掺杂浓度。上述第二导电类型接线掺杂区236的掺杂浓度大于第二导电类型漂移掺杂区228的掺杂浓度。
经过上述制作工艺之后，于电位转换区204中形成一LDMOS元件270。LDMOS元件270具有栅极结构250，源极掺杂区和汲极掺杂区。低电位区202和栅极结构250之间的上述第二导电类型漂移掺杂区228和第二导电类型接线掺杂区236做为LDMOS元件270的源极掺杂区，而栅极结构250和高电位区208之间的上述第二导电类型漂移掺杂区228和第二导电类型接线掺杂区236做为LDMOS元件270的汲极掺杂区。并且，经过上述制作工艺之后，可完成本发明一些实施例中的半导体装置500。
本发明实施例的半导体装置500提供用于高压集成电路的一种高压半导体装置。本发明实施例的半导体装置500的高电位区内的基板中具有利用两道离子植入制作工艺形成的两个N型埋藏层(N-type burier layer，以下简称NBL)，且上述两个NBL为电性浮接(electrical floating)。上述两个NBL包括一深NBL和位于深NBL正上方的一浅NBL，深NBL的顶面距离半导体装置的磊晶层的顶面的距离大于浅NBL的顶面距离半导体装置的磊晶层的顶面的距离。另外，深NBL的掺杂浓度小于浅NBL的掺杂浓度至少一个数量级。由于本发明实施例的N型埋藏层结构由浅NBL和深NBL两者构成，可增加N型埋藏层整体的掺杂浓度，因而可使电阻降低且改善元件的闭锁效应(latch up performance)。由于本发明实施例的N型埋藏层结构具较低电阻，因而在不改变横向设计规则(laterial rule)的情况下(意即，不增加元件尺寸)改善高压元件的切换速度(switching speed(dV/dt))。并且，由浅NBL和深NBL两者构成的N型埋藏层结构可增加电性隔离能力，深NBL可有效改善高电位区中的垂直方向的击穿效应(例如从P型漂移掺杂区至其下方的P型基板的垂直方向击穿效应)。此外，形成浅NBL和深NBL两者的两道离子植入制作工艺的掺质剂量皆小于1x1014cm-2，不须使用高掺质剂量(例如大于1x1015cm-3)的离子植入制作工艺，因而影响最终形成的半导体装置的元件表面掺杂浓度。
虽然本发明已以实施例揭露于上，然其并非用以限定本发明，任何熟习此项技艺者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当以本发明权利要求范围所界定者为准。

Claims (10)

1.一种半导体装置，其特征在于，所述的半导体装置包括：
一基板，具有一第一导电类型，所述基板包括：
一高电位区；
一低电位区，其与所述高电位区彼此隔开；以及
一电位转换区和一隔离区，设于所述高电位区与所述低电位区之间，其中所述隔离区将所述电位转换区与所述高电位区彼此隔开；
一磊晶层，设于所述基板上，其中所述磊晶层具有一第二导电类型，且所述第一导电类型与所述第二导电类型不同；
一第二导电类型第一埋藏层，设置于所述高电位区中，其中所述第二导电类型第一埋藏层具有所述第二导电类型；
一第二导电类型第二埋藏层，设置于所述第二导电类型第一埋藏层的正上方，其中所述第二导电类型第二埋藏层具有所述第二导电类型，
其中所述第二导电类型第一埋藏层的一顶面与所述第二导电类型第二埋藏层的一顶面分别与所述磊晶层的一顶面相距不同距离，且其中所述第二导电类型第一埋藏层的掺质浓度小于所述第二导电类型第二埋藏层的掺质浓度；
所述的第二导电类型第一埋藏层具有一第一宽度，所述第二导电类型第二埋藏层具有一第二宽度，且所述第二宽度大于第一宽度。
2.如权利要求1所述的半导体装置，其特征在于，所述的第二导电类型第一埋藏层的掺质浓度小于所述第二导电类型第二埋藏层两者的掺质浓度一个数量级。
3.如权利要求1所述的半导体装置，其特征在于，所述的电位转换区的所述基板内不具有所述第二导电类型第一埋藏层。
4.如权利要求1所述的半导体装置，其特征在于，所述的第二导电类型第二埋藏层的一底面直接接触所述第二导电类型第一埋藏层的所述顶面。
5.如权利要求1所述的半导体装置，其特征在于，所述的第二导电类型第一埋藏层内具有一第一掺质，所述第二导电类型第二埋藏层内具有一第二掺质，且所述第一掺质不同于所述第二掺质。
6.如权利要求5所述的半导体装置，其特征在于，所述的第一掺质的原子量小于所述第二掺质的原子量。
7.一种半导体装置的制造方法，其特征在于，所述的方法包括下列步骤：
提供一基板，具有一第一导电类型，所述基板包括：
一高电位区；
一低电位区，其与所述高电位区彼此隔开；以及
一电位转换区和一隔离区，设于所述高电位区与所述低电位区之间，其中所述隔离区将所述电位转换区与所述高电位区彼此隔开；
进行一第一离子植入制作工艺，于所述高电位区中的所述基板内形成一第二导电类型第一埋藏层，其中所述第二导电类型第一埋藏层具有一第二导电类型，且所述第一导电类型与所述第二导电类型不同；
进行一第二离子植入制作工艺，于所述第二导电类型第一埋藏层的正上方形成一第二导电类型第二埋藏层，其中所述第二导电类型第二埋藏层具有所述第二导电类型；以及
进行一磊晶成长制作工艺，于所述基板上形成一磊晶层，其中所述磊晶层具有所述第二导电类型，其中形成所述磊晶层之后，所述第二导电类型第二埋藏层扩散延伸进入所述磊晶层中。
8.如权利要求7所述的半导体装置的制造方法，其特征在于，在进行所述第一离子植入制作工艺之后进行所述第二离子植入制作工艺。
9.如权利要求7所述的半导体装置的制造方法，其特征在于，进行所述第一离子植入制作工艺和进行所述第二离子植入制作工艺期间不会于所述电位转换区的所述基板内形成所述第二导电类型第一埋藏层。
10.如权利要求7所述的半导体装置的制造方法，其特征在于，第一离子植入制作工艺于所述高电位区中的所述基板内植入一第一掺质以形成所述第二导电类型第一埋藏层，所述第二离子植入制作工艺于所述第二导电类型第一埋藏层的正上方的所述基板内植入一第二掺质以形成所述第二导电类型第二埋藏层，且所述第一掺质不同于所述第二掺质。
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