JP2019145633A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2019145633A JP2019145633A JP2018027575A JP2018027575A JP2019145633A JP 2019145633 A JP2019145633 A JP 2019145633A JP 2018027575 A JP2018027575 A JP 2018027575A JP 2018027575 A JP2018027575 A JP 2018027575A JP 2019145633 A JP2019145633 A JP 2019145633A
- Authority
- JP
- Japan
- Prior art keywords
- impurity concentration
- trench
- semiconductor device
- region
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 139
- 239000012535 impurity Substances 0.000 claims abstract description 133
- 238000009826 distribution Methods 0.000 claims abstract description 79
- 230000007423 decrease Effects 0.000 claims description 7
- 230000015556 catabolic process Effects 0.000 abstract description 30
- 238000009413 insulation Methods 0.000 abstract 3
- 230000005684 electric field Effects 0.000 description 40
- 239000010410 layer Substances 0.000 description 37
- 238000010586 diagram Methods 0.000 description 24
- 230000000052 comparative effect Effects 0.000 description 14
- 239000000758 substrate Substances 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000002902 bimodal effect Effects 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
Abstract
Description
本実施形態に係る半導体装置は、第1の面と、第1の面と反対側の第2の面とを有し、第2の面側から第1の面側に向かう方向に不純物濃度分布を有する第1導電型の半導体層と、第1の面側から前記半導体層の中に設けられた第2導電型の第1半導体領域と、第1の面側から第1半導体領域の中に設けられた第1導電型の第2半導体領域と、第1の面側から半導体層の中に設けられた第1トレンチと、第1トレンチ内に、第1半導体領域と対向するように、第1絶縁膜を介して設けられた第1電極と、第1トレンチ内に第2絶縁膜を介して設けられた第2電極と、第1トレンチを囲うように、第1の面側から半導体層の中に設けられた第2トレンチと、第2トレンチ内に第3絶縁膜を介して設けられた第3電極と、を具備する。
本実施形態に係る半導体装置について図7を用いて説明する。
具体的には、上述したように、第2部分11dにおける不純物濃度が比較例の半導体層より高い。その結果、ドレイン電圧が増加し、不純物濃度が高い第2部分11dに空乏層が達した際にパンチスルー状態になることで、電界が比較例の半導体層より増加する。その結果、活性領域10aにおける耐圧の向上とオン抵抗の低減が図られる。
本実施形態に係る半導体装置について図9および図10を用いて説明する。
10a、40a 活性領域
10b、40b 終端領域
11 半導体層
11a、11b 第1、第2の面
11c〜11e 第1〜第3部分
12 pベース領域
13 n+ソース領域
14 第1トレンチ
15 ゲート絶縁膜
16 ゲート電極
17 第1フィールドプレート絶縁膜
18 第1フィールドプレート電極
19、41 第2トレンチ
20、42 第2フィールドプレート絶縁膜
21、43 第2フィールドプレート電極
22 半導体基板
23 層間絶縁膜
24 ソース電極
25 コンタクト孔
Claims (11)
- 第1の面と、前記第1の面と反対の側の第2の面とを有し、前記第2の面側から前記第1の面側に向かう方向に不純物濃度分布を有する第1導電型の半導体層と、
前記第1の面側から前記半導体層の中に設けられた第2導電型の第1半導体領域と、
前記第1の面側から前記第1半導体領域の中に設けられた第1導電型の第2半導体領域と、
前記第1の面側から前記半導体層の中に設けられた第1トレンチと、
前記第1トレンチ内に、前記第1半導体領域と対向するように、第1絶縁膜を介して設けられた第1電極と、
前記第1トレンチ内に第2絶縁膜を介して設けられた第2電極と、
前記第1トレンチを囲むように、前記第1の面側から前記半導体層の中に設けられた第2トレンチと、
前記第2トレンチ内に第3絶縁膜を介して設けられた第3電極と、
を具備する半導体装置。 - 前記半導体層は、前記第2の面側から前記第1の面側に向かう方向に、
第1不純物濃度を有する第1部分と、
第2不純物濃度を有する第2部分と、
第3不純物濃度を有する第3部分と、
を有する請求項1記載の半導体装置。 - 前記第2不純物濃度は前記第1不純物濃度および前記第3不純物濃度より高く、且つ前記第1不純物濃度および前記3第不純物濃度は実質的に等しい請求項2記載の半導体装置。
- 前記第2不純物濃度は前記第1不純物濃度より高く、且つ前記第3不純物濃度は前記第1不純物濃度より低い請求項2記載の半導体装置。
- 前記第2不純物濃度は前記第1不純物濃度に実質的に等しく、且つ前記第3不純物濃度は前記第1不純物濃度より低い請求項2記載の半導体装置。
- 前記第2不純物濃度は前記第1不純物濃度より低く、且つ前記第3不純物濃度より高い請求項2記載の半導体装置。
- 前記第2部分は、前記第1電極より前記第2の面側で、且つ前記第1トレンチの底部より前記第1の面側に設けられる請求項2乃至6記載の半導体装置。
- 前記第3部分は、前記第1電極より前記第2の面側で、且つ前記第2部分より前記第1の面側に設けられる請求項2乃至6記載の半導体装置。
- 前記半導体層は、前記第2の面側から前記第1の面側に向かう方向に不純物濃度が漸次低下する分布を有する請求項1記載の半導体装置。
- 前記第1トレンチは所定の間隔で複数配置されており、前記第1トレンチと前記第2トレンチとの距離は、前記所定の間隔と実質的に等しい請求項1乃至9記載の半導体装置。
- 前記第1トレンチと前記第2トレンチ、前記第2絶縁膜と前記第3絶縁膜、および前記第2電極と前記第3電極とは、それぞれ実質的に同じ構造を有する請求項1乃至9記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018027575A JP6873937B2 (ja) | 2018-02-20 | 2018-02-20 | 半導体装置 |
US16/120,109 US10763352B2 (en) | 2018-02-20 | 2018-08-31 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018027575A JP6873937B2 (ja) | 2018-02-20 | 2018-02-20 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2019145633A true JP2019145633A (ja) | 2019-08-29 |
JP6873937B2 JP6873937B2 (ja) | 2021-05-19 |
Family
ID=67618077
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018027575A Active JP6873937B2 (ja) | 2018-02-20 | 2018-02-20 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10763352B2 (ja) |
JP (1) | JP6873937B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2022081879A (ja) * | 2020-11-20 | 2022-06-01 | 住友不動産株式会社 | 木造住宅用耐力壁及び耐力壁の耐力を増大させる方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11158735B2 (en) | 2020-02-05 | 2021-10-26 | Infineon Technologies Austria Ag | Charge compensation MOSFET with graded epi profile and methods of manufacturing thereof |
KR20220048131A (ko) * | 2020-10-12 | 2022-04-19 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002083963A (ja) * | 2000-06-30 | 2002-03-22 | Toshiba Corp | 半導体素子 |
JP2003017696A (ja) * | 2001-06-29 | 2003-01-17 | Toshiba Corp | 半導体装置 |
JP2010232355A (ja) * | 2009-03-26 | 2010-10-14 | Toshiba Corp | 半導体装置 |
JP2013509720A (ja) * | 2009-10-28 | 2013-03-14 | ヴィシェイ−シリコニックス | トレンチ金属酸化物半導体電界効果トランジスタ |
JP2015056643A (ja) * | 2013-09-13 | 2015-03-23 | 株式会社東芝 | 半導体装置の製造方法 |
JP2016076731A (ja) * | 2009-11-02 | 2016-05-12 | 富士電機株式会社 | 半導体装置 |
JP2017055016A (ja) * | 2015-09-11 | 2017-03-16 | 株式会社東芝 | 半導体装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013069866A (ja) | 2011-09-22 | 2013-04-18 | Toshiba Corp | 半導体装置 |
JP2013069852A (ja) | 2011-09-22 | 2013-04-18 | Toshiba Corp | 半導体装置 |
US9614043B2 (en) | 2012-02-09 | 2017-04-04 | Vishay-Siliconix | MOSFET termination trench |
JP2014120656A (ja) | 2012-12-18 | 2014-06-30 | Toshiba Corp | 半導体装置 |
JP2015176900A (ja) | 2014-03-13 | 2015-10-05 | 株式会社東芝 | 半導体装置 |
US9673314B2 (en) * | 2015-07-08 | 2017-06-06 | Vishay-Siliconix | Semiconductor device with non-uniform trench oxide layer |
US9818828B2 (en) * | 2016-03-09 | 2017-11-14 | Polar Semiconductor, Llc | Termination trench structures for high-voltage split-gate MOS devices |
-
2018
- 2018-02-20 JP JP2018027575A patent/JP6873937B2/ja active Active
- 2018-08-31 US US16/120,109 patent/US10763352B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002083963A (ja) * | 2000-06-30 | 2002-03-22 | Toshiba Corp | 半導体素子 |
JP2003017696A (ja) * | 2001-06-29 | 2003-01-17 | Toshiba Corp | 半導体装置 |
JP2010232355A (ja) * | 2009-03-26 | 2010-10-14 | Toshiba Corp | 半導体装置 |
JP2013509720A (ja) * | 2009-10-28 | 2013-03-14 | ヴィシェイ−シリコニックス | トレンチ金属酸化物半導体電界効果トランジスタ |
JP2016076731A (ja) * | 2009-11-02 | 2016-05-12 | 富士電機株式会社 | 半導体装置 |
JP2015056643A (ja) * | 2013-09-13 | 2015-03-23 | 株式会社東芝 | 半導体装置の製造方法 |
JP2017055016A (ja) * | 2015-09-11 | 2017-03-16 | 株式会社東芝 | 半導体装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2022081879A (ja) * | 2020-11-20 | 2022-06-01 | 住友不動産株式会社 | 木造住宅用耐力壁及び耐力壁の耐力を増大させる方法 |
Also Published As
Publication number | Publication date |
---|---|
JP6873937B2 (ja) | 2021-05-19 |
US20190259871A1 (en) | 2019-08-22 |
US10763352B2 (en) | 2020-09-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6654221B2 (ja) | 絶縁ゲート型炭化珪素半導体装置及びその製造方法 | |
US11552172B2 (en) | Silicon carbide device with compensation layer and method of manufacturing | |
CN104247026B (zh) | 碳化硅半导体装置及其制造方法 | |
US8035158B2 (en) | Semiconductor device | |
JP6950290B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP5353190B2 (ja) | 半導体装置および半導体装置の製造方法 | |
US9064952B2 (en) | Semiconductor device | |
JP6918302B2 (ja) | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 | |
US20140209999A1 (en) | Semiconductor device | |
KR100731141B1 (ko) | 반도체소자 및 그의 제조방법 | |
JP2009004668A (ja) | 半導体装置 | |
KR20080100775A (ko) | 수퍼 정션 구조를 가지는 반도체 장치 및 그 제조 방법 | |
US10510834B2 (en) | High-voltage semiconductor device having a doped isolation region between a level shift region and a high voltage region | |
JP2010177373A (ja) | 半導体装置及び半導体装置の製造方法 | |
JP2005322700A (ja) | 半導体装置及びその製造方法 | |
JP2018006639A (ja) | 半導体装置及びその製造方法 | |
US20180366549A1 (en) | Semiconductor device and method of manufacturing a semiconductor device | |
US10763352B2 (en) | Semiconductor device | |
WO2017145548A1 (ja) | 化合物半導体装置およびその製造方法 | |
JP2008171891A (ja) | 半導体装置とその製造方法 | |
KR102100863B1 (ko) | SiC MOSFET 전력 반도체 소자 | |
US9825125B2 (en) | Silicon carbide semiconductor device and manufacturing method of silicon carbide semiconductor device | |
JP5037103B2 (ja) | 炭化珪素半導体装置 | |
US20230111246A1 (en) | Semiconductor device and method for manufacturing the same | |
JP2019033140A (ja) | 半導体装置および半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20191212 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20201117 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20201130 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20210125 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20210322 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20210421 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6873937 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |