TW201824368A - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 239000002019 doping agent Substances 0.000 claims abstract description 53
- 238000000034 method Methods 0.000 claims description 72
- 238000005468 ion implantation Methods 0.000 claims description 40
- 238000006243 chemical reaction Methods 0.000 claims description 31
- 238000002955 isolation Methods 0.000 claims description 29
- 239000007943 implant Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
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- 229910052698 phosphorus Inorganic materials 0.000 description 4
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- 238000009933 burial Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
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- 229910052710 silicon Inorganic materials 0.000 description 3
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- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
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- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
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- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 2
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- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
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- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
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- 238000011065 in-situ storage Methods 0.000 description 1
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Abstract
本發明實施例提供一種半導體裝置及其製造方法。半導體裝置包括基板,具有第一導電類型。磊晶層,設於基板上且具有第二導電類型。第二導電類型第一埋藏層,設置於基板的高電位區中,第二導電類型第一埋藏層具有第二導電類型。第二導電類型第二埋藏層,位於第二導電類型第一埋藏層的正上方,第二導電類型第二埋藏層具有第二導電類型。第二導電類型第一埋藏層的頂面與第二導電類型第二埋藏層的頂面分別與磊晶層的頂面相距不同距離。第二導電類型第一埋藏層的摻質濃度小於第二導電類型第二埋藏層的摻質濃度。
Description
本發明實施例係有關於一種半導體裝置及其製造方法,特別是有關於一種高壓半導體裝置及其製造方法。
高壓積體電路(HVIC)因具有符合成本效益且易相容於其它製程等優點,因而已廣泛應用於發光二極體(LED)、顯示器驅動積體電路元件、電源供應器、電力管理、通訊、車用電子的電源控制系統中。然而,習知的高壓積體電路會因為閉鎖效應(latch up)、低擊穿電壓、低元件切換速度及較大的元件面積等問題而無法進一步的改善。
因此,在此技術領域中,有需要一種高壓半導體裝置,以改善上述缺點。
本發明之一實施例係提供一種半導體裝置。上述半導體裝置包括一基板,具有一第一導電類型,上述基板包括:一高電位區;一低電位區,其與上述高電位區彼此隔開;以及一電位轉換區和一隔離區,設於上述高電位區與上述低電位區之間,其中上述隔離區將上述電位轉換區與上述高電位區彼此隔開;一磊晶層,設於上述基板上,其中上述磊晶層具有一第
二導電類型,且上述第一導電類型與上述第二導電類型不同;一第二導電類型第一埋藏層,設置於上述高電位區中,其中上述第二導電類型第一埋藏層具有上述第二導電類型;一第二導電類型第二埋藏層,設置於上述第二導電類型第一埋藏層的正上方,其中上述第二導電類型第二埋藏層具有上述第二導電類型,其中上述第二導電類型第一埋藏層的一頂面與上述第二導電類型第二埋藏層的一頂面分別與上述磊晶層的一頂面相距不同距離,且其中上述第二導電類型第一埋藏層的摻質濃度小於上述第二導電類型第二埋藏層的摻質濃度。
本發明之另一實施例係提供一種半導體裝置的製造方法。上述半導體裝置的製造方法包括提供一基板,具有一第一導電類型,上述基板包括:一高電位區;一低電位區,其與上述高電位區彼此隔開;以及一電位轉換區和一隔離區,設於上述高電位區與上述低電位區之間,其中上述隔離區將上述電位轉換區與上述高電位區彼此隔開;進行一第一離子植入製程,於上述高電位區中的上述基板內形成一第二導電類型第一埋藏層,其中上述第二導電類型第一埋藏層具有一第二導電類型,且上述第一導電類型與上述第二導電類型不同;進行一第二離子植入製程,於上述第二導電類型第一埋藏層的正上方形成一第二導電類型第二埋藏層,其中上述第二導電類型第二埋藏層具有上述第二導電類型;以及進行一磊晶成長製程,於上述基板上形成一磊晶層,其中上述磊晶層具有上述第二導電類型,其中形成上述磊晶層之後,上述第二導電類型第二埋藏層係擴散延伸進入上述磊晶層中。
500‧‧‧半導體裝置
200‧‧‧基板
202‧‧‧低電位區
204‧‧‧電位轉換區
206‧‧‧隔離區
208‧‧‧高電位區
210‧‧‧第二導電類型第一埋藏摻雜區
211、213、217、221‧‧‧頂面
212‧‧‧第二導電類型第一埋藏層
212A‧‧‧第一摻質
214‧‧‧第二導電類型第二埋藏層
214A‧‧‧第二摻質
215、216‧‧‧邊緣
220‧‧‧磊晶層
222‧‧‧高壓第一導電類型井區
224‧‧‧高壓第二導電類型井區
226‧‧‧第一導電類型井區
228‧‧‧第二導電類型漂移摻雜區
230‧‧‧第一導電類型漂移摻雜區
234‧‧‧第一導電類型接線摻雜區
236‧‧‧第二導電類型接線摻雜區
240‧‧‧隔絕結構
250‧‧‧閘極結構
260‧‧‧交界處
270‧‧‧橫向擴散金屬氧化物半導體
300、304‧‧‧遮罩圖案
302、306‧‧‧離子植入製程
W1‧‧‧第一寬度
W2‧‧‧第二寬度
D1、D2‧‧‧距離
第1~4圖顯示本發明一些實施例之半導體裝置之製程剖面示意圖。
為了讓本發明之目的、特徵、及優點能更明顯易懂,下文特舉實施例,並配合所附圖示,做詳細之說明。本發明說明書提供不同的實施例來說明本發明不同實施方式的技術特徵。其中,實施例中的各元件之配置係為說明之用,並非用以限制本發明。且實施例中圖式標號之部分重複,係為了簡化說明,並非意指不同實施例之間的關聯性。
本發明實施例係提供用於高壓積體電路(HVIC)的一種半導體裝置。上述於半導體裝置的高電位區內的基板中設置由不同道離子植入製程形成一N型深埋藏層(N-type burier layer)和一N型淺埋藏層,其中N型深埋藏層係設置於N型淺埋藏層的正下方,且上述N型深埋藏層的摻雜濃度係設計小於N型淺埋藏層的摻雜濃度。此處的「深」和「淺」意指埋藏層的頂面距離半導體裝置的一磊晶層的頂面的距離大小。舉例來說,N型深埋藏層的頂面與半導體裝置的磊晶層的頂面之間相距的距離大於N型淺埋藏層的頂面與半導體裝置的磊晶層的頂面之間相距的距離。並且,用於形成上述N型深埋藏層和N型淺埋藏層使用的兩道不同離子植入製程的摻質劑量皆小於1014cm-2,因而在形成濃度較濃的N型淺埋藏層時不會影響元件表面摻雜
輪廓(doping profile)。此外,上述N型深埋藏層和N型淺埋藏層可有效抑制高壓積體電路的高電位區(high side region)中的垂直方向的擊穿效應。
第1~4圖顯示本發明一些實施例之半導體裝置500之製程剖面示意圖。請參考第1圖,首先提供基板200,上述基板200係摻雜摻質以具有第一導電類型。舉例來說,當第一導電類型為P型時,上述基板200可為一P型基板。在本發明一些實施例中,基板200的摻雜濃度可為約1x1011-1x1015/cm3,因而基板200可視為一輕摻雜P型基板200。此處的「輕摻雜」意指摻雜濃度小於1x1015/cm3。在本發明一些實施例中,上述基板200可為矽基板。在本發明其他實施例中,可利用鍺化矽(SiGe)、塊狀半導體(bulk semiconductor)、應變半導體(strained semiconductor)、化合物半導體(compound semiconductor),或其他常用之半導體基板做為基板200。
如第1圖所示,基板200包括一低電位區(low side region)202、一高電位區(high side region)208、及設於與低電位區202和高電位區208之間的一電位轉換區(level shift region)204和一隔離區206。上述隔離區206位於電位轉換區204與高電位區208之間,以將電位轉換區204與高電位區208彼此隔開。在如第1圖所示的一些實施例中,上述低電位區202、電位轉換區204、隔離區206和高電位區208沿平行於基板200的一頂面211的一方向由左至右依序配置。
在本發明一些實施例中,上述低電位區202係用以提供低壓積體電路元件(操作電壓例如低於20V)形成於其上,
上述高電位區208係用以提供高壓積體電路元件(操作電壓例如大於等於600V)形成於其上。並且,上述電位轉換區204可包括橫向擴散金屬氧化物半導體(laterally diffused metal oxide semiconductor,以下簡稱LDMOS)元件形成於其上。而隔離區206係用以在橫向擴散金屬氧化物半導體之閘極設於關閉狀態時,電性隔離上述低電位區202和高電位區208。
上述電位轉換區204的LDMOS元件的源極可電性耦接至低電位區202中的低壓積體電路元件。並且,上述電位轉換區204的LDMOS元件的汲極可藉由跨越隔離區206的金屬內連線(圖未顯示)電性耦接至高電位區208中的高壓積體電路元件,當上述LDMOS元件之閘極係設於開通狀態時,可用以將低電位區202的低電壓位準轉換成高電位區208的高電壓位準。
請參考第2圖,可進行一微影製程,於基板200的頂面211上形成一遮罩圖案300,上述遮罩圖案300可暴露出部分高電位區208中的基板200,並定義出後續之第二導電類型第一埋藏層區210的形成區域。值得注意的是,遮罩圖案300並未暴露出低電位區202、電位轉換區204和隔離區206中的基板200。然後,以上述遮罩圖案300為罩幕,進行一離子植入製程302,於高電位區208中的基板200內植入第一摻質212A以形成一第二導電類型第一埋藏摻雜區210。之後,移除遮罩圖案300。上述第二導電類型第一埋藏摻雜區210具有一第二導電類型,且第二導電類型不同於第一導電類型。舉例來說,當第一導電類型為P型時,上述第二導電類型為N型,且第二導電類型第一埋
藏摻雜區210可視為一N型埋藏摻雜區210。
如第2圖所示,值得注意的是,上述離子植入製程302僅於高電位區208中的基板200內植入第一摻質212A以形成第二導電類型第一埋藏摻雜區210,但未同時於上述低電位區202、電位轉換區204、隔離區206內植入第一摻質212A以形成其他的第二導電類型埋藏摻雜區。上述第二導電類型第一埋藏摻雜區210完全位於高電位區208中。換句話說,上述第二導電類型第一埋藏摻雜區210的邊緣215完全位於高電位區208中。
在本發明一些實施例中,上述離子植入製程302使用的第一摻質212A可包括磷(P)。上述離子植入製程302使用的摻雜劑量範圍可為1x1011-5x1013/cm2,因此形成的上述第二導電類型第一埋藏層210之摻雜濃度範圍可為1x1015-5x1018/cm3。進行上述離子植入製程302之後,可進行一退火製程以活化第一摻質212A且使上述第二導電類型第一埋藏摻雜區210內之第一摻質212A分佈均勻。
接著,請參考第3圖,可進行另一微影製程,於基板200的頂面211上形成一遮罩圖案304,上述遮罩圖案304可暴露出部分高電位區208中的基板200,並定義出後續之第二導電類型第二埋藏層的形成區域。上述遮罩圖案304可完全暴露出第二導電類型第一埋藏摻雜區210。值得注意的是,遮罩圖案304並未暴露出低電位區202、電位轉換區204和隔離區206中的基板200。然後,以上述遮罩圖案304為罩幕,進行另一離子植入製程306,於高電位區208中的基板200內植入第二摻質214A,改變接近基板200的頂面211的部分第二導電類型第一埋藏摻
雜區210的摻質濃度,以將第2圖所示的第二導電類型第一埋藏摻雜區210轉變成一第二導電類型第一埋藏層212,並於上述第二導電類型第一埋藏層212的正上方形成一第二導電類型第二埋藏層214。之後,移除遮罩圖案304。上述第二導電類型第二埋藏層214具有第二導電類型。舉例來說,當第一導電類型為P型時,上述第二導電類型為N型,且上述第二導電類型第一埋藏層212和第二導電類型第二埋藏層214可分別視為N型埋藏層212和N型埋藏層214。在本發明一些實施例中,進行離子植入製程302和306之後形成的上述第二導電類型第一埋藏層212的頂面213低於基板200的頂面211。
如第3圖所示,值得注意的是,上述離子植入製程302僅於高電位區208中的基板200內植入第二摻質212A以形成第二導電類型第二埋藏層212,但未同時於上述低電位區202、電位轉換區204、隔離區206內植入第二摻質212A以形成其他的第二導電類型埋藏層。上述第二導電類型第一埋藏層212完全位於高電位區208中。換句話說,上述第二導電類型第一埋藏層212的邊緣215完全位於高電位區208中。
在第3圖所示之本發明實施例中,離子植入製程302使用的第一摻質212A和離子植入製程306使用的第二摻質214A可屬於相同的摻質族群(例如第VA族)。值得注意的是,離子植入製程302使用的第一摻質212A和離子植入製程306使用的第二摻質214A為不同的摻質。詳細來說,上述第一摻質212A的原子量小於第二摻質214A的原子量。另外,上述第一摻質212A的擴散係數(diffusivity)大於第二摻質214A的擴散係數。
舉例來說,當第一摻質212A為磷(P)時,第二摻質214A為砷(As)。
在第3圖所示之本發明實施例中,用以形成第二導電類型第二埋藏層214之離子植入製程306使用的摻雜劑量係設計大於用以形成第二導電類型第一埋藏摻雜210(如第2圖所示)之離子植入製程302使用的摻雜劑量。舉例來說,離子植入製程306使用之摻雜劑量範圍可為1x1013-1x1015/cm2,例如為5x1013/cm2。值得注意的是,進行兩道離子植入製程302和306之後形成的第二導電類型第二埋藏層214之摻雜濃度範圍可為1x1017-1x1020/cm3,而進行兩道離子植入製程302和306之後形成的第二導電類型第一埋藏層212之摻雜濃度範圍為1x1015-1x1018/cm3。換句話說,進行兩道離子植入製程302和306之後形成的第二導電類型第二埋藏層214之摻雜濃度大於進行兩道離子植入製程302和306之後形成的第二導電類型第一埋藏層212之摻雜濃度約一~二個數量級。
值得注意的是,在本發明一些實施例中,用以形成第二導電類型第一埋藏層212和第二導電類型第二埋藏層214兩者使用的兩道離子植入製程302和306的摻質劑量皆小於5x1018cm-3,因而不會影響最終形成的半導體裝置的元件表面摻雜濃度。
由於上述第二導電類型第一埋藏層212和第二導電類型第二埋藏層214兩者的摻質原子量不同。相較於第二導電類型第一埋藏層212,位於其下方的第二導電類型第一埋藏層212具有較輕的摻質,因而具有較大的擴散係數。因此,上
述第二導電類型第一埋藏層212的和第二導電類型第二埋藏層214兩者可設計具有不同的寬度。舉例來說,上述第二導電類型第一埋藏層212具有一第一寬度W1,第二導電類型第二埋藏層214具有一第二寬度W2,且第二寬度W2大於第一寬度W1。
進行如第3圖所示之上述離子植入製程306之後,可進行另一退火製程以活化第二摻質214A且使上述第二導電類型第二埋藏層214之摻雜濃度分佈均勻。在本發明一些實施例中,上述第二導電類型第二埋藏層214的底面與上述第二導電類型第一埋藏層212的頂面213直接接觸。且於進行如如第3圖所示之製程步驟之後,上述第二導電類型第二埋藏層214的的頂面實質上與基板200的頂面211共平面。
接著,如第4圖所示,進行一磊晶成長(epitaxial growth)製程,以於基板200的頂面211上全面性形成一磊晶層220。上述磊晶成長製程可包括例如金屬有機物化學氣相沉積法(MOCVD)、金屬有機物化學氣相磊晶法(MOVPE)、電漿增強型化學氣相沉積法(plasma-enhanced CVD)、遙控電漿化學氣相沉積法(RP-CVD)、分子束磊晶法(MBE)、氫化物氣相磊晶法(HVPE)、液相磊晶法(LPE)、氯化物氣相磊晶法(Cl-VPE)或類似的方法。在本發明一些實施例中,可於進行磊晶成長製程時,於反應氣體中加入磷化氫(phosphine)或砷化三氫(arsine)進行原位(in-situ)摻雜以形成上述第二導電類型磊晶層206。本發明一些實施例中,可先磊晶成長未摻雜之磊晶層(圖未顯示),之後再以磷離子或砷離子摻雜上述未摻雜之磊晶層以形成磊晶層220。
上述磊晶層220的材質可包括矽、鍺、矽與鍺、III-V族化合物或上述之組合。上述磊晶層220具有一第二導電類型,且第二導電類型不同於第一導電類型。舉例來說,當第一導電類型為P型時,上述第二導電類型為N型,且磊晶層220可視為一N型磊晶層220。在本發明一些實施例中,磊晶層220可具有例如磷(P)之摻質,且磊晶層220的厚度範圍可為2μm至8μm。
在進行上述磊晶成長製程以形成磊晶層220的期間,上述第二導電類型第二埋藏層214係擴散延伸進入磊晶層220中。意即形成磊晶層220之後,第二導電類型第二埋藏層214的一頂面217可位於基板200的頂面211上方。
如第4圖所示,第二導電類型第一埋藏層212的頂面213與第二導電類型第二埋藏層214的頂面217分別與磊晶層220的一頂面221相距不同距離。詳細來說,第二導電類型第一埋藏層212的頂面213與磊晶層220的頂面221相距一距離D1,第二導電類型第二埋藏層214的頂面217與磊晶層220的頂面221相距一距離D2,且距離D1大於距離D2。
接著,如第4圖所示,進行數道離子植入製程,以分別於低電位區202、電位轉換區204、隔離區206和高電位區208內的磊晶層220中植入不同的摻質,以於低電位區202、電位轉換區204和隔離區206內的磊晶層220中形成高壓第一導電類型井區222,且於高電位區208中的磊晶層220內形成一高壓第二導電類型井區224。舉例來說,當第一導電類型為P型時,上述第二導電類型為N型,上述高壓第一導電類型井區222可視為高壓P型井區(HVPW)222,且上述高壓第二導電類型井區224
可視為高壓N型井區(HVNW)224。在本發明一些實施例中,上述高壓第一導電類型井區222和高壓第二導電類型井區224的底面可位於磊晶層220內,且可對齊於基板200和磊晶層220的交界處260(位置同基板200的頂面211)。
接著,如第4圖所示,進行數道離子植入製程,以分別於低電位區202、電位轉換區204、隔離區206和高電位區208內的磊晶層220中植入不同的摻質,以於低電位區202和隔離區206內的磊晶層220中形成第一導電類型漂移摻雜區230,且於低電位區202、電位轉換區204和高電位區208中的磊晶層220內形成一第二導電類型漂移摻雜區228。舉例來說,當第一導電類型為P型時,上述第二導電類型為N型,上述第一導電類型漂移摻雜區230可視為P型漂移摻雜區(P-drift doped region)230,上述第二導電類型漂移摻雜區228可視為N型漂移摻雜區(N-drift doped region)228。
接著,如第4圖所示,進行一或多道離子植入製程,以分別於低電位區202和高電位區208內的磊晶層220中植入摻質,以於低電位區202和高電位區208內的磊晶層220中形成第一導電類型井區226。舉例來說,當第一導電類型為P型時,上述第一導電類型井區226可視為P型井區226。
在本發明一些實施例中,上述高壓第一導電類型井區222的摻雜濃度低於上述第一導電類型漂移摻雜區230的摻雜濃度,且上述第一導電類型漂移摻雜區230的摻雜濃度低於第一導電類型井區226的摻雜濃度。上述磊晶層220的摻雜濃度低於上述高壓第二導電類型井區224,上述高壓第二導電類
型井區224的的摻雜濃度低於上述第二導電類型漂移摻雜區228。
接著,如第4圖所示,可於磊晶層220的頂面221上形成一墊氧化層(圖未顯示)以及一墊氮化矽層(圖未顯示),之後蝕刻墊氧化層以及墊氮化矽層以定義出低電位區202、電位轉換區204、隔離區206和高電位區208中的多個主動區域。接著,可利用局部熱氧化法,於磊晶層220的頂面221上形成多個隔絕結構240。如第4圖所示,上述多個分別隔絕結構232覆蓋低電位區202、電位轉換區204和隔離區206中的基板200的部分頂面221。舉例來說,隔絕結構240定義出上述低電位區202中之接線摻雜區(pick-up doped region)的形成位置,電位轉換區204的LDMOS元件的閘極、源極摻雜區、汲極摻雜區的形成位置,以及高電位區208中之接線摻雜區的形成位置。
然後,如第4圖所示,於電位轉換區204內的磊晶層220的頂面221上形成一閘極結構250,上述閘極結構250覆蓋位於高壓第一導電類型井區222和第二導電類型漂移摻雜區228上的部分隔絕結構240,且覆蓋高壓第一導電類型井區222和其中一個第二導電類型漂移摻雜區228(低電位區202和閘極結構250之間)。上述閘極結構250藉由另一個隔絕結構240(閘極結構250和高電位區208之間)與其中另一個第二導電類型漂移摻雜區228相隔一距離。形成上述閘極結構250的方式包括進行例如化學氣相沉積法(CVD)或原子層沉積法(ALD)之一薄膜沉積製程,於磊晶層220的頂面221上順應性形成一閘極絕緣材料(圖未顯示)。接著,進行包括物理氣相沉積法(PVD)、化學氣
相沉積法(CVD)或原子層沉積法(ALD)或其他類似方式之一薄膜沉積製程,於上述閘極絕緣材料上全面性形成一閘極導電材料。然後,進行一圖案化製程,移除部分閘極導電材料和閘極絕緣材料,以形成上述閘極結構250。
接著,如第4圖所示,再進行數道離子植入製程,以分別於低電位區202、電位轉換區204和高電位區208內的磊晶層220中植入不同的摻質,以於低電位區202中的磊晶層220內的第一導電類型井區226上形成第一導電類型接線摻雜區(pick-up doped region)234,且於電位轉換區204和高電位區208中的磊晶層220內的不同的第二導電類型漂移摻雜區228上分別形成第二導電類型接線摻雜區236。舉例來說,當第一導電類型為P型時,第二導電類型為N型,上述第一導電類型接線摻雜區234可視為P型接線摻雜區234,上述第二導電類型接線摻雜區236可視為N型接線摻雜區236。
在本發明一些實施例中,上述第一導電類型接線摻雜區234的摻雜濃度大於第一導電類型井區226的摻雜濃度。上述第二導電類型接線摻雜區236的摻雜濃度大於第二導電類型漂移摻雜區228的摻雜濃度。
經過上述製程之後,於電位轉換區204中形成一LDMOS元件270。LDMOS元件270具有閘極結構250,源極摻雜區和汲極摻雜區。低電位區202和閘極結構250之間的上述第二導電類型漂移摻雜區228和第二導電類型接線摻雜區236做為LDMOS元件270的源極摻雜區,而閘極結構250和高電位區208之間的上述第二導電類型漂移摻雜區228和第二導電類型接線
摻雜區236做為LDMOS元件270的汲極摻雜區。並且,經過上述製程之後,可完成本發明一些實施例中的半導體裝置500。
本發明實施例的半導體裝置500係提供用於高壓積體電路的一種高壓半導體裝置。本發明實施例的半導體裝置500的高電位區內的基板中具有利用兩道離子植入製程形成的兩個N型埋藏層(N-type burier layer,以下簡稱NBL),且上述兩個NBL為電性浮接(electrical floating)。上述兩個NBL包括一深NBL和位於深NBL正上方的一淺NBL,深NBL的頂面距離半導體裝置的磊晶層的頂面的距離大於淺NBL的頂面距離半導體裝置的磊晶層的頂面的距離。另外,深NBL的摻雜濃度小於淺NBL的摻雜濃度至少一個數量級。由於本發明實施例的N型埋藏層結構由淺NBL和深NBL兩者構成,可增加N型埋藏層整體的摻雜濃度,因而可使電阻降低且改善元件的閉鎖效應(latch up performance)。由於本發明實施例的N型埋藏層結構具較低電阻,因而在不改變橫向設計規則(laterial rule)的情況下(意即,不增加元件尺寸)改善高壓元件的切換速度(switching speed(dV/dt))。並且,由淺NBL和深NBL兩者構成的N型埋藏層結構可增加電性隔離能力,深NBL可有效改善高電位區中的垂直方向的擊穿效應(例如從P型漂移摻雜區至其下方的P型基板的垂直方向擊穿效應)。此外,形成淺NBL和深NBL兩者的兩道離子植入製程的摻質劑量皆小於1x1014cm-2,不須使用高摻質劑量(例如大於1x1015cm-3)的離子植入製程,因而影響最終形成的半導體裝置的元件表面摻雜濃度。
雖然本發明已以實施例揭露於上,然其並非用以
限定本發明,任何熟習此項技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
Claims (11)
- 一種半導體裝置,包括:一基板,具有一第一導電類型,該基板包括:一高電位區;一低電位區,其與該高電位區彼此隔開;以及一電位轉換區和一隔離區,設於該高電位區與該低電位區之間,其中該隔離區將該電位轉換區與該高電位區彼此隔開;一磊晶層,設於該基板上,其中該磊晶層具有一第二導電類型,且該第一導電類型與該第二導電類型不同;一第二導電類型第一埋藏層,設置於該高電位區中,其中該第二導電類型第一埋藏層具有該第二導電類型;一第二導電類型第二埋藏層,設置於該第二導電類型第一埋藏層的正上方,其中該第二導電類型第二埋藏層具有該第二導電類型,其中該第二導電類型第一埋藏層的一頂面與該第二導電類型第二埋藏層的一頂面分別與該磊晶層的一頂面相距不同距離,且其中該第二導電類型第一埋藏層的摻質濃度小於該第二導電類型第二埋藏層的摻質濃度。
- 如申請專利範圍第1項所述之半導體裝置,其中該第二導電類型第一埋藏層的摻質濃度小於該第二導電類型第二埋藏層兩者的摻質濃度一個數量級。
- 如申請專利範圍第1項所述之半導體裝置,其中該電位轉換區的該基板內不具有該第二導電類型第一埋藏層。
- 如申請專利範圍第1項所述之半導體裝置,其中該第二導電類型第二埋藏層的一底面直接接觸該第二導電類型第一埋藏層的該頂面。
- 如申請專利範圍第1項所述之半導體裝置,其中該第二導電類型第一埋藏層具有一第一寬度,該第二導電類型第二埋藏層具有一第二寬度,且該第二寬度大於第一寬度。
- 如申請專利範圍第1項所述之半導體裝置,其中該第二導電類型第一埋藏層內具有一第一摻質,該第二導電類型第二埋藏層內具有一第二摻質,且該第一摻質不同於該第二摻質。
- 如申請專利範圍第6項所述之半導體裝置,其中該第一摻質的原子量小於該第二摻質的原子量。
- 一種半導體裝置的製造方法,包括下列步驟:提供一基板,具有一第一導電類型,該基板包括:一高電位區;一低電位區,其與該高電位區彼此隔開;以及一電位轉換區和一隔離區,設於該高電位區與該低電位區之間,其中該隔離區將該電位轉換區與該高電位區彼此隔開;進行一第一離子植入製程,於該高電位區中的該基板內形成一第二導電類型第一埋藏層,其中該第二導電類型第一埋藏層具有一第二導電類型,且該第一導電類型與該第二導電類型不同; 進行一第二離子植入製程,於該第二導電類型第一埋藏層的正上方形成一第二導電類型第二埋藏層,其中該第二導電類型第二埋藏層具有該第二導電類型;以及進行一磊晶成長製程,於該基板上形成一磊晶層,其中該磊晶層具有該第二導電類型,其中形成該磊晶層之後,該第二導電類型第二埋藏層係擴散延伸進入該磊晶層中。
- 如申請專利範圍第8項所述之半導體裝置的製造方法,其中於進行該第一離子植入製程之後進行該第二離子植入製程。
- 如申請專利範圍第8項所述之半導體裝置的製造方法,其中進行該第一離子植入製程和進行該第二離子植入製程期間不會於該電位轉換區的該基板內形成該第二導電類型第一埋藏層。
- 如申請專利範圍第8項所述之半導體裝置的製造方法,其中該第一離子植入製程於該高電位區中的該基板內植入一第一摻質以形成該第二導電類型第一埋藏層,該第二離子植入製程於該第二導電類型第一埋藏層的正上方的該基板內植入一第二摻質以形成該第二導電類型第二埋藏層,且該第一摻質不同於該第二摻質。
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TWI613712B (zh) | 2018-02-01 |
US10546944B2 (en) | 2020-01-28 |
CN108242468A (zh) | 2018-07-03 |
US20180182863A1 (en) | 2018-06-28 |
CN108242468B (zh) | 2020-07-03 |
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