TW201814886A - 帶有可控相位節點振鈴的開關電路 - Google Patents

帶有可控相位節點振鈴的開關電路 Download PDF

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TW201814886A
TW201814886A TW106135198A TW106135198A TW201814886A TW 201814886 A TW201814886 A TW 201814886A TW 106135198 A TW106135198 A TW 106135198A TW 106135198 A TW106135198 A TW 106135198A TW 201814886 A TW201814886 A TW 201814886A
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Taiwan
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trench
subset
body region
transistor
gate
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TW106135198A
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English (en)
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TWI648842B (zh
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潘繼
燮光 雷
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萬國半導體（澳門）股份有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本發明有關於一種開關電路，包括導電類型相同的一個第一金屬氧化物半導體(metal oxide semiconductor, MOS)電晶體和一個第二MOS電晶體，並聯在開關電路的第一端和第二端之間，第一和第二MOS電晶體具有各自的閘極端，耦合到控制端上，以接收控制訊號，接通或斷開第一和第二MOS電晶體。第一MOS電晶體的特徵在於第一反向閘極至汲極電容(Crss)，第二MOS電晶體的特徵在於第二Crss，第二Crss大於第一Crss。

Description

帶有可控相位節點振鈴的開關電路
本發明主要有關於整合電路，更確切的說是關於具有金屬-氧化物-半導體場效應電晶體(MOSFET)的整合電路元件。
微處理器和儲存設備等整合電路在每個元件上都含有多個MOSFET電晶體，提供配置邏輯設計和/或數據儲存所需的基本開關功能。在一個示例中，降壓變換器等直流到直流功率轉換器通常配置MOSFET作為其開關元件。尤其是降壓轉換器廣泛應用於將較高輸入電壓轉換成較低輸出電壓的行業。同步降壓轉換器包括一對開關元件，串聯耦合在輸入電壓源。開關元件通常為MOSFET。第1圖表示傳統的降壓轉換器，包括一個高端開關(HSFET)和一個低端開關(LSFET)。高端開關102耦合到電壓源(Vin)，低端開關104接地。通常包括一個電感器(L)和一個電容器(Cout)的輸出濾波器，汲極端這對開關102和104形成的結(即相位節點或開關節點)105，以便為負載提供輸出電壓。控制器110驅使開關，將輸出濾波器連接到電壓源或接地，以便將輸出電壓維持在預置水平。
同步絕緣區設計中的問題之一在於電壓過沖，以及相位節點處的振鈴。由於對較高性能元件的要求不斷提高，人們希望高端MOSFET的開關速度越來越快。開關速度越快，相位節點的電壓轉換越快。快速的電壓轉換可能導致低端開關無意中接通，導致轉換器失效，降低效率。另外，由於振鈴的大小是高端MOSFET的開關速度的函數，因此這可能會引起相位節點振鈴。相位節點電壓尖峰可能導致功率開關失效或不必要的壓力。
利用多種技術，控制相位節點振鈴。如第1圖所示，升壓電阻器RBOOT和高端閘極電阻器RGH已經包含在第1圖所示的同步降壓轉換器中，用於控制相位節點振鈴現象。確切地說，升壓電阻器RBOOT可以減緩高端MOSFET的接通，而不影響斷開。另外，高端閘極電阻器RGH與閘極串聯，可以增大高端MOSFET的接通和斷開時間，控制相位節點上升和下降的振鈴。另一個建議是在低端開關中整合肖特基二極管，以降低恢復電荷，從而避免在相位節點處出現電壓尖峰。有必要設計一種開關電路，可以適當地控制同步降壓轉換器的相位節點振鈴。
正是在這樣的背景下，提出了本發明的實施例。
本發明的目的在於提出一種帶有可控相位節點振鈴的開關電路，以改善現有技術中的一個或多個問題。
本發明的一個方面在於提出一種具有第一端、第二端和控制端的開關電路，包括：具有相同導電類型的一個第一金屬氧化物半導體(metal oxide semiconductor, MOS)電晶體和一個第二MOS電晶體，並聯在第一端和第二端之間，第一和第二MOS電晶體各自的閘極端耦合到控制端，以接收控制訊號，接通或斷開第一和第二MOS電晶體；其中第一MOS電晶體具有第一反向閘極至汲極電容(Crss)，第二MOS電晶體具有第二反向閘極至汲極電容Crss，其中第二MOS電晶體的Crss大於第一MOS電晶體的Crss。
其中，第一MOS電晶體具有第一電晶體區，第二MOS電晶體具有第二電晶體區，第二電晶體區是第一電晶體區的一小部分。
其中，第一MOS電晶體和第二MOS電晶體為分立的MOS電晶體。
其中，第一MOS電晶體和第二MOS電晶體形成在一個公共半導體基板的一個公共有源元件區中。
其中，第二MOS電晶體的第二電晶體區占公共有源元件區總面積的0.1%至15%之間。
其中，每個第一MOS電晶體和第二MOS電晶體都由一個或多個溝槽電晶體構成，一個或多個溝槽電晶體中的每個電晶體都具有一個形成在公共半導體基板上半導體層溝槽中的閘極端，一個形成在半導體層中的本體區以及一個形成在溝槽附近的源極區。
其中，第二MOS電晶體的一個或多個溝槽電晶體中的每個溝槽電晶體都包括一個溝槽和閘極，形成在半導體層中，且比第一MOS電晶體的一個或多個溝槽電晶體延伸到更深處。
其中，第一和第二MOS電晶體的一個或多個溝槽電晶體中的每個溝槽都形成到公共深度，半導體層中所形成的本體區的深度對於第一MOS電晶體來說大於第二MOS電晶體。
其中，開關電路為降壓轉換器的高端開關。
其中，降壓轉換器包括具有一個輸入端、一個輸出端和一個低端控制端的低端開關，其中第二端連接到輸入端。
本發明的另一個方面在於提出一種用於製備開關電路的方法，包括：在第一導電類型的半導體層中，製備一個溝槽電晶體晶胞陣列，溝槽電晶體晶胞由溝槽閘極結構限定，每個的閘極溝槽結構都包括一個形成在半導體層中的溝槽，以及一個形成在溝槽中的絕緣閘電極；在溝槽電晶體晶胞的第一子集中，製備與第一導電類型相反的第二導電類型的第一本體區，第一本體區和溝槽電晶體晶胞的第一子集的溝槽從第一本體區底部到第一子集中閘極溝槽底部的第一距離與第一反向閘極至汲極電容Crss有關；在溝槽電晶體晶胞的第二子集中，製備與第一導電類型相反的第二導電類型的第二本體區，第二本體區和溝槽電晶體晶胞的第二子集的溝槽從第二本體區底部到第二子集中閘極溝槽底部的第二距離與第二反向閘極至汲極電容Crss有關，其中第二距離大於第一距離；並且在溝槽電晶體晶胞的陣列中製備源極區。
其中，製備溝槽電晶體晶胞陣列包括在第二子集中製備閘極溝槽，使得第二子集中閘極溝槽底部的深度大於第一子集中閘極溝槽底部的深度，並且其中製備第一和第二本體區包括製備第一本體區，使得第一本體區底部與第二本體區底部的深度相同。
其中，在第二子集中製備閘極溝槽，使得第二子集中閘極溝槽底部的深度大於第一子集中閘極溝槽底部的深度，包括在第一和第二子集中將溝槽刻蝕到第一深度，用遮罩保護第一子集中的溝槽，同時保留第二子集中的溝槽不帶遮罩，將第二子集中的溝槽刻蝕到第二深度，第二深度比第一深度更深。
其中，在第二子集中製備閘極溝槽使得第二子集中閘極溝槽底部的深度大於第一子集中閘極溝槽底部的深度，包括利用第一溝槽遮罩，將第二子集中的溝槽刻蝕到特定深度，然後利用第二溝槽遮罩，刻蝕第一子集中的溝槽，同時保留第二子集中的溝槽不帶遮罩，將第二子集中的溝槽刻蝕到第二深度，第二深度比第一深度更深。
其中，製備溝槽電晶體晶胞的陣列包括在第一和第二子集中製備閘極溝槽到第一和第二子集中閘極溝槽底部的公共深度，其中製備第一和第二本體區包括製備第一本體區，使得第二本體區的底部深度大於第一本體區底部深度。
其中，製備第一本體區使得第二本體區底部深度大於第一本體區底部深度，包括利用第一注入製程，在第一注入能量下製備第一和第二本體區到第一深度，用遮罩保護第二本體區不被第二次注入，同時保留第一本體區不帶遮罩，在第一本體區中第二能量下進行第二次注入，第二能量大於第一能量。
其中，製備溝槽電晶體晶胞的陣列包括在第二子集中製備閘極溝槽，使得第二子集中閘極溝槽的底部深度大於第一子集中閘極溝槽的底部深度，其中製備第一和第二本體區包括製備第一本體區，使得第二本體區底部深度大於第一本體區底部深度。
閱讀以下詳細說明的實施例並參照各種圖式，本發明的這些特點和優勢對於本領域的具通常知識者來說，無疑將顯而易見。
本發明的各個方面提出了用開關電路替代傳統的低端MOSFET開關，允許同步降壓轉換器具有平滑的相位節點波形。本發明的各個方面包括一個具有主MOS電晶體和二級MOS電晶體並聯的開關電路。主MOS電晶體的特點是具有第一反向閘極至汲極電容Crss和第一閾值電壓。二級MOS電晶體的特點是具有第二Crss和第二閾值電壓。在一些實施例中，可以通過提高二級MOS電晶體的Crss，減少使用這種開關電路的同步降壓轉換器的相位節點電壓振鈴，從而使第二Crss大於第一Crss。在一些實施例中，通過降低二級MOS電晶體的閾值電壓，可以進一步減少相位節點電壓振鈴，從而使第二閾值電壓低於第一閾值電壓。在一些其他實施例中，通過增大二級MOS電晶體的Crss並降低二級MOS電晶體的閾值電壓，可以減少相位節點電壓振鈴，從而使第二Crss大於第一Crss，並且第二閾值電壓低於第一閾值電壓。
平滑同步降壓轉換器相位節點波形的一種方法是用主MOS電晶體和並聯的二級MOS電晶體代替傳統的單獨低端MOSFET，並聯的二級MOS電晶體與主MOS電晶體相比，具有較高的Crss。第2圖表示根據本發明的各個方面，開關電路200可以用作例如低端開關104，用在第1圖所示的降壓轉換器中。開關電路200具有第一端，例如汲極D，第二端，例如源極S，以及一個控制端，例如閘極G。開關電路200具有兩個MOSFET，一個具有常規Crss的主MOS電晶體210以及一個具有高Crss的二級MOS電晶體220，並聯在第一端D和第二端S之間。主MOS電晶體210和二級MOS電晶體220具有各自的閘極端，耦合到控制端G上，以接收控制訊號，接通或斷開主MOS電晶體210和二級MOS電晶體220。
主MOS電晶體210和二級MOS電晶體220的導電性相同。主MOS電晶體210和二級MOS電晶體220形成在公共半導體基板的公共有源元件區中。確切地說，每個主MOS電晶體210和二級MOS電晶體220都由一個或多個溝槽電晶體構成。每個溝槽電晶體都具有一個形成在公共半導體基板上半導體層中的溝槽中的閘極端，一個形成在半導體層中的本體區以及一個形成在溝槽附近的源極區。
主MOS電晶體210的區域為常規Crss區，二級MOS電晶體220的區域為高Crss區。高Crss區與常規Crss區的比例影響相位節點峰值電壓。區域比例越高，導致相位節點電壓越低，從而獲得平滑的相位節點波形。更可選擇，高Crss區中的Crss越高，實現減小相位節點峰值電壓所需效果的區域比例越小。可以根據相位節點峰值電壓所需的減小量，預定義該比例。作為示例，但不作為侷限，高Crss區可以占公共有源元件區總面積的0.1%到15%之間。
第3A圖表示一部分傳統的溝槽MOSFET的剖面示意圖。在本行業中眾所周知，Crss與本體區320的底部和閘極溝槽340的底部之間的深度基本成正比，如第3A圖所示。因此，提高Crss的一種方式是增大高Crss區中閘極溝槽340的溝槽深度。另一種方式是減小有源區的高Crss區中本體區320的深度。應注意的是，在一些實施例中，可以通過較深的閘極溝槽與高Crss區中較淺的本體區相結合，提高Crss。
我們希望，二級MOS電晶體220的區域應均勻分佈在主MOS電晶體210的區域。第3圖表示形成在半導體基板上開關電路200的示例佈局，包括主MOS電晶體210和二級MOS電晶體220，而沒有顯示出頂部源極金屬層。閘極溝槽與源極區呈平行條紋帶，沉積在帶有接觸開口的並聯閘極溝槽之間的基板上方，接觸開口通過源極區打開。二級MOS電晶體220的部分沿每個條紋MOS結構沉積，構成二級MOS電晶體220的條紋，其方向與閘極溝槽條紋方向垂直。更可選擇，選定特定閘極溝槽的整個長度，在閘極溝槽條紋的方向上，形成二級MOS電晶體220的條紋。
第一實施例
第4A至4J圖表示製備第2圖所示開關電路製備製程的剖面圖，二級MOS電晶體220的每個溝槽電晶體都有閘極溝槽，在半導體層中比主MOS電晶體210的溝槽電晶體的閘極溝槽更深處。
參見第4A圖，該製程使用第一導電類型的半導體基板410作為初始材料。在一些實施例中，基板410包括N-型外延層，在重摻雜N型(N+)矽晶圓上方。在基板410上使用一個遮罩412，含有開口，為主MOS電晶體210和二級MOS電晶體220的溝槽電晶體，限定多個閘極溝槽的位置。在第4B圖中，進行刻蝕製程，向下刻蝕下方基板410相應的部分，以形成多個閘極溝槽440。
利用另一個遮罩414，在常規Crss區中遮罩閘極溝槽440a(也就是對主MOS電晶體210的溝槽電晶體來說的閘極溝槽)，並且暴露出高Crss區中的閘極溝槽440b(也就是對二級MOS電晶體220的溝槽電晶體來說的閘極溝槽)。進行另一個刻蝕製程，使閘極溝槽440b更深，如第4C圖所示。然後，除去遮罩414，如第4C’ 圖所示。參見第4D至4J圖，如下所述進行後續處理。
在一個可選實施例中，如第4K至4N圖所示，通過修飾兩個刻蝕製程之間的遮罩，形成兩種不同深度的溝槽。確切地說，如第4K圖所示，在基板410上，使用具有第一組開口413的遮罩412。進行第一次刻蝕製程，如第4L圖所示，在基板中將閘極溝槽440b刻蝕到初始深度。然後，在遮罩412中形成額外開口413’，如第4M圖所示。更可選擇，除去遮罩412，形成具有開口的第二遮罩，對應原始開口413和額外開口413’。第二次刻蝕製程，通過額外開口413’刻蝕基板410，形成閘極溝槽440a，而第二次刻蝕製程更通過原始開口413刻蝕基板，以加深閘極溝槽440b。然後，除去遮罩412，參見第4D至4J圖，如下所述進行後續處理。
確切地說，形成各自深度的閘極溝槽440a、440b之後，除去遮罩，可以生長一個犧牲氧化層(圖中沒有表示出)，然後除去，以改善矽表面。參見第4D圖，沿閘極溝槽440a、440b的內表面，形成絕緣層(例如閘極氧化物)444。在帶有回刻的閘極氧化層(絕緣層444)上方，放置導電材料，形成閘極電極442。在一些實施例中，導電材料可以是原位摻雜或未摻雜的多晶矽。可以在溝槽上方，形成電介質層446，蓋住溝槽，並且在基板410上方，作為注入緩衝層。
參見第4E圖，進行全面本體注入，形成本體區420。摻雜離子的導電類型與基板410的摻雜導電類型相反。在一些實施例中，對於N-通道元件來說，摻雜離子可以是硼離子。在一些實施例中，對於P-通道來說，可以使用磷或砷離子。然後，利用熱激發摻雜原子，驅使摻雜物擴散，形成本體區420，如第4F圖所示。
參見第4G圖，進行源極注入和刻蝕，在基板410的頂面中形成源極區430。摻雜離子的導電類型與基板410的摻雜導電類型相同。在一些實施例中，對於N-通道元件來說，摻雜離子可以是砷離子。更可選擇，對於P-通道元件來說，可以注入硼離子。
然後，在基板410上方放置一個平面電介質層450，如第4H圖所示。在一些實施例中，通過低溫氧化製程，利用含有硼酸的矽玻璃材料(BPSG)，形成電介質層450。
然後，在電介質層450上使用接觸光致抗蝕劑(圖中沒有表示出)，在接觸溝槽的位置處具有一個開口的圖案。進行刻蝕製程，除去電介質層450的未覆蓋部分，通過源極區430，在本體區420中形成接觸溝槽460，如第4I圖所示。
放置金屬層470，填充接觸開口，互連所有的源極區，形成主MOS電晶體210和二級MOS電晶體220並聯。
第二實施例
第5A至5J圖表示對二級MOS電晶體220的每個溝槽電晶體製備本體區，與主MOS電晶體210的溝槽電晶體的本體區相比，深度更淺，第2圖所示開關電路的製備製程剖面圖。
參見第5A圖，該製程使用第一導電類型的半導體基板510作為初始材料。在一些實施例中，基板510包括一個N-型外延層，在重摻雜N型(N+)矽晶圓上方。在基板510上使用遮罩512，包括開口，為主MOS電晶體210和二級MOS電晶體220的溝槽電晶體，限定閘極溝槽的位置。如第5B圖所示，進行刻蝕製程，向下刻蝕下方的基板510的相應部分，形成多個閘極溝槽540。然後，除去遮罩512，如第5B’圖所示。
然後，生長一個犧牲氧化層(圖中沒有表示出)並除去，以改善矽表面。沿閘極溝槽540的內表面形成一個絕緣層(例如閘極氧化物)544。在帶有回刻的閘極氧化層(絕緣層544)上方，放置導電材料，形成閘極電極542。在一些實施例中，導電材料可以是原位摻雜的或未摻雜的多晶矽。在溝槽上方形成電介質層546，覆蓋溝槽，在基板510上方作為一個注入緩衝層，如第5C圖所示。
參見第5D圖，用較低能量進行第一全面本體注入，形成本體區520。摻雜離子的導電類型與基板510的摻雜類型相反。在一些實施例中，對於N-通道元件來說，摻雜離子可以是硼離子。在一些實施例中，對於P-通道元件來說，摻雜離子可以是磷或砷離子。在一些實施例中，注入到本體區中的摻雜離子劑量，例如硼離子可以注入到1e13cm-2 左右，能量約為100KeV。第一次低能本體注入之後，所選的本體區520a對應高Crss區(也就是對於二級MOS電晶體220的溝槽電晶體來說的本體區)，受注入遮罩522保護。在較高能量下進行另一次本體注入，如第5E圖所示，通過遮罩中的開口。換言之，在第二次本體注入中，摻雜離子僅注入到常規Crss區中的本體區520b中(也就是對於主MOS電晶體210的溝槽電晶體來說的本體區)。因此，與高Crss區中的本體區520a相比，本體區520b在基板510中較深處。在一些實施例中，到本體區520b中第二次本體注入的摻雜物(例如硼)離子劑量，例如約為8e12cm-2 左右，能量約為150KeV。利用熱激活摻雜原子，驅使摻雜物擴散，形成本體區520a和520b，如第5F圖所示。
參見第5G圖，進行源極注入，在基板510的頂面中形成源極區530。摻雜離子的導電類型與基板510的摻雜類型相同。在一些實施例中，對於N-通道元件來說，可以注入深離子。更可選擇，對於P-通道元件來說，可以注入硼離子。
然後，在基板510上方，放置一個平整的電介質層550，如第5H圖所示。在一些實施例中，通過低溫氧化製程，利用含有硼酸的矽玻璃(BPSG)材料，形成電介質層550。
在電介質層550上使用接觸光致抗蝕劑(圖中沒有表示出)，帶有在接觸溝槽位置處具有一個開口的圖案。利用刻蝕製程，除去電介質層550未被覆蓋的部分，通過本體區520a和520b中的源極區530，形成接觸溝槽560，如第5I圖所示。
然後，放置一個金屬層570，填充接觸開口，並互連所有的源極區，以形成主MOS電晶體210和二級MOS電晶體220並聯。
閾值電壓
通過用帶有較低開啟閾值電壓(Vth)的主MOS電晶體和並聯的二級MOS電晶體代替傳統的獨立MSOFET，使同步減壓轉換器的相位節點波形平滑的另一種方式。由於在低於相位節點電壓尖峰導致的閘極尖峰下的接通閾值電壓下，二級MOS電晶體接通，因此該方式可以保持很低的相位節點峰值振鈴。確切地說，當高端MOSFET接通時，低端FET中電流下降。VDS中的尖峰觸發足夠高的VGS尖峰，並用較低的接通閾值電壓接通二級MOS電晶體，從而降低相位節點尖峰的電壓。第6圖表示依據本發明的各個方面，開關600電路。開關電路600具有一個第一端D、一個第二端S和一個控制端G。開關電路600具有兩個MOSFET、一個具有常規Vth的主MOS電晶體610以及一個具有較低Vth並聯在第一端D和第二端S之間的二級MOS電晶體620。主MOS電晶體610和二級MOS電晶體620具有各自的閘極端耦合到控制端G上，以接收控制訊號，接通或斷開主MOS電晶體610和二級MOS電晶體620。
主MOS電晶體610和二級MOS電晶體620導電類型相同。主MOS電晶體610和二級MOS電晶體620形成在一個公共半導體基板的公共有源元件區中。確切地說，每個主MOS電晶體610和二級MOS電晶體620都由一個或多個溝槽電晶體構成。每個溝槽電晶體都有一個形成在公共半導體基板上半導體層溝槽中的閘極端，一個形成在半導體層中的本體區以及一個形成在溝槽附近的源極區。主MOS電晶體610的區域為常規Vth區，二級MOS電晶體620的區域為較低的Vth區。較低的Vth區和常規Vth區之比影響相位節點峰值電壓。第7圖所示波形，表示隨著更大比例的公共有源元件區總區域中的低Vth區，相位節點峰值振鈴變得更低。根據相位節點峰值電壓所需的減少量，可以預定義比例。作為示例，但不作為侷限，低Vth區占公共有源元件區總區域的5%至15%。二級MOS電晶體的Vth越低，實現減少相位節點振鈴所需效果，需要的區域比例越低。
關於第6圖所示開關電路的製備製程，進行兩次本體注入。確切地說，首先進行常規的全面本體注入，然後利用本體遮罩，進行第二次本體注入。本體遮罩覆蓋低Vth區，使得摻雜離子僅注入到第二次本體注入的常規Vth區。要注意的是，可以通過低注入能量降低閾值電壓，並且通過降低注入的劑量，可以進一步降低閾值電壓。在一些實施例中，注入到本體區中摻雜離子(例如硼離子)的劑量，例如在第一次本體注入中，從2e12cm-2 至2e13cm-2 之間，能量約為50KeV~1MeV，在第二次本體注入中，從2e12cm-2 至2e13cm-2 之間，能量約為80KeV~1MeV。製備製程的詳情可以參見2014年4月14日存檔的共同所有的美國專利申請號14/253,568，公開為美國專利申請公開2015/0295495，提出了一種具有並聯電晶體對(其中一個電晶體的閾值電壓低於另一個電晶體)的開關電路。美國專利申請公開2015/0295495的全文特此引用，以作參考。
如第8圖所示，這種類型的開關電路可用於降壓轉換器100，例如作為如第1圖所示的低端開關104。降壓轉換器包括例如帶有自身輸入(例如汲極)端D、輸出(例如源極)端S和低端控制端(例如閘極)G的高端開關102。低端開關的輸入連接到高端開關的第二(例如輸出)端。
儘管本發明關於某些較佳的版本已經做了詳細的敘述，但是仍可能存在各種不同的修正、變化和等效情況。因此，本發明的範圍不應由上述說明決定，與之相反，本發明的範圍應參照所附的申請專利範圍及其全部等效內容。任何可選件(無論首選與否)，都可與其他任何可選件(無論首選與否)組合。在以下申請專利範圍中，除非特別聲明，否則不定冠詞“一個”或“一種”都指下文內容中的一個或多個項目的數量。除非用“意思是”明確指出限定功能，否則所附的申請專利範圍並不應認為是意義加功能的侷限。
100‧‧‧降壓轉換器
102‧‧‧高端開關
104‧‧‧低端開關
105‧‧‧結
110‧‧‧控制器
200、600‧‧‧開關電路
210、610‧‧‧主MOS電晶體
220、620‧‧‧二級MOS電晶體
320、420、520、520a、520b‧‧‧本體區
340、440、440a、440b、540‧‧‧閘極溝槽
410、510‧‧‧基板
412、414、512、522‧‧‧遮罩
413‧‧‧開口
413’‧‧‧額外開口
430、530‧‧‧源極區
442、542‧‧‧閘極電極
444、544‧‧‧絕緣層
446、450、546、550‧‧‧電介質層
460、560‧‧‧接觸溝槽
470、570‧‧‧金屬層
第1圖表示一種傳統的降壓轉換器的電路圖。 第2圖表示依據本發明的各個方面，一種開關電路的電路圖。 第3A圖表示部分傳統的溝槽MOSFET的剖面示意圖。 第3圖表示第2圖所示的開關電路的示例佈局。 第4A圖至第4N圖表示在本發明的一個實施例中，用於製備第2圖所示開關電路的製備製程剖面圖。 第5A至5J圖表示在本發明的一個可選實施例中，用於第2圖所示開關電路的製備製程剖面圖。 第6圖表示依據本發明的各個方面，一種開關電路的電路圖。 第7圖表示第6圖所示開關電路的相位節點的波形。 第8圖表示依據本發明的各個方面，一種降壓轉換器的電路圖。

Claims (17)

  1. 一種具有第一端、第二端和控制端的開關電路，該開關電路包括： 具有相同導電類型的一第一金屬氧化物半導體電晶體和一第二金屬氧化物半導體電晶體，並聯在第一端和第二端之間，該第一金屬氧化物半導體電晶體和該第二金屬氧化物半導體電晶體各自的閘極端耦合到控制端，以接收控制訊號，接通或斷開該第一金屬氧化物半導體電晶體和該第二金屬氧化物半導體電晶體； 其中該第一金屬氧化物半導體電晶體具有第一反向閘極至汲極電容，該第二金屬氧化物半導體電晶體具有第二反向閘極至汲極電容，其中該第二金屬氧化物半導體電晶體的第二反向閘極至汲極電容大於該第一金屬氧化物半導體電晶體的第一反向閘極至汲極電容。
  2. 如申請專利範圍第1項所述之開關電路，其中該第一金屬氧化物半導體電晶體具有第一電晶體區，該第二金屬氧化物半導體電晶體具有第二電晶體區，第二電晶體區是第一電晶體區的一小部分。
  3. 如申請專利範圍第1項所述之開關電路，其中該第一金屬氧化物半導體電晶體和該第二金屬氧化物半導體電晶體為分立的金屬氧化物半導體電晶體。
  4. 如申請專利範圍第1項所述之開關電路，其中該第一金屬氧化物半導體電晶體和該第二金屬氧化物半導體電晶體形成在一公共半導體基板的一公共有源元件區中。
  5. 如申請專利範圍第4項所述之開關電路，其中該第二金屬氧化物半導體電晶體的第二電晶體區占公共有源元件區總面積的0.1%至15%之間。
  6. 如申請專利範圍第1項所述之開關電路，其中每個該第一金屬氧化物半導體電晶體和該第二金屬氧化物半導體電晶體都由一或多個溝槽電晶體構成，一或多個溝槽電晶體中的每個電晶體都具有一形成在公共半導體基板上半導體層溝槽中的閘極端，一形成在半導體層中的本體區以及一形成在溝槽附近的源極區。
  7. 如申請專利範圍第6項所述之開關電路，其中該第二金屬氧化物半導體電晶體的一或多個溝槽電晶體中的每個溝槽電晶體都包括一溝槽和閘極，形成在半導體層中，且比該第一金屬氧化物半導體電晶體的一或多個溝槽電晶體延伸到更深處。
  8. 如申請專利範圍第6項所述之開關電路，其中該第一金屬氧化物半導體電晶體和該第二金屬氧化物半導體電晶體的一或多個溝槽電晶體中的每個溝槽都形成到公共深度，半導體層中所形成的本體區的深度對於該第一金屬氧化物半導體電晶體來說大於該第二金屬氧化物半導體電晶體。
  9. 如申請專利範圍第1項所述之開關電路，其中該開關電路為降壓轉換器的高端開關。
  10. 如申請專利範圍第9項所述之開關電路，其中降壓轉換器包括具有一輸入端、一輸出端和一低端控制端的低端開關，其中第二端連接到輸入端。
  11. 一種用於製備開關電路的方法，其包括： 在第一導電類型的半導體層中，製備一溝槽電晶體晶胞陣列，溝槽電晶體晶胞由溝槽閘極結構限定，每個該閘極溝槽結構都包括一形成在半導體層中的溝槽，以及一形成在溝槽中的絕緣閘電極； 在溝槽電晶體晶胞的第一子集中，製備與第一導電類型相反的第二導電類型的第一本體區，第一本體區和溝槽電晶體晶胞的第一子集的溝槽從第一本體區底部到第一子集中閘極溝槽底部的第一距離與第一反向閘極至汲極電容有關； 在溝槽電晶體晶胞的第二子集中，製備與第一導電類型相反的第二導電類型的第二本體區，第二本體區和溝槽電晶體晶胞的第二子集的溝槽從第二本體區底部到第二子集中閘極溝槽底部的第二距離與第二反向閘極至汲極電容有關，其中第二距離大於第一距離；以及 在溝槽電晶體晶胞的陣列中製備源極區。
  12. 如申請專利範圍第11項所述之用於製備開關電路的方法，其中製備溝槽電晶體晶胞陣列包括在第二子集中製備閘極溝槽，使得第二子集中閘極溝槽底部的深度大於第一子集中閘極溝槽底部的深度，並且其中製備第一本體區和第二本體區包括製備第一本體區，使得第一本體區底部與第二本體區底部的深度相同。
  13. 如申請專利範圍第12項所述之用於製備開關電路的方法，其中在第二子集中製備閘極溝槽，使得第二子集中閘極溝槽底部的深度大於第一子集中閘極溝槽底部的深度，包括在第一子集和第二子集中將溝槽刻蝕到第一深度，用遮罩保護第一子集中的溝槽，同時保留第二子集中的溝槽不帶遮罩，將第二子集中的溝槽刻蝕到第二深度，第二深度比第一深度更深。
  14. 如申請專利範圍第12項所述之用於製備開關電路的方法，其中在第二子集中製備閘極溝槽使得第二子集中閘極溝槽底部的深度大於第一子集中閘極溝槽底部的深度，包括利用第一溝槽遮罩，將第二子集中的溝槽刻蝕到特定深度，然後利用第二溝槽遮罩，刻蝕第一子集中的溝槽，同時保留第二子集中的溝槽不帶遮罩，將第二子集中的溝槽刻蝕到第二深度，第二深度比第一深度更深。
  15. 如申請專利範圍第11項所述之用於製備開關電路的方法，其中製備溝槽電晶體晶胞的陣列包括在第一子集和第二子集中製備閘極溝槽到第一子集和第二子集中閘極溝槽底部的公共深度，其中製備第一本體區和第二本體區包括製備第一本體區，使得第二本體區的底部深度大於第一本體區底部深度。
  16. 如申請專利範圍第15項所述之用於製備開關電路的方法，其中製備第一本體區使得第二本體區底部深度大於第一本體區底部深度，包括利用第一注入製程，在第一注入能量下製備第一本體區和第二本體區到第一深度，用遮罩保護第二本體區不被第二次注入，同時保留第一本體區不帶遮罩，在第一本體區中第二能量下進行第二次注入，第二能量大於第一能量。
  17. 如申請專利範圍第11項所述之用於製備開關電路的方法，其中製備溝槽電晶體晶胞的陣列包括在第二子集中製備閘極溝槽，使得第二子集中閘極溝槽的底部深度大於第一子集中閘極溝槽的底部深度，其中製備第一本體區和第二本體區包括製備第一本體區，使得第二本體區底部深度大於第一本體區底部深度。
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