CN107959489A - 带有可控相位节点振铃的开关电路 - Google Patents

带有可控相位节点振铃的开关电路 Download PDF

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CN107959489A
CN107959489A CN201710913345.XA CN201710913345A CN107959489A CN 107959489 A CN107959489 A CN 107959489A CN 201710913345 A CN201710913345 A CN 201710913345A CN 107959489 A CN107959489 A CN 107959489A
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depth
mos transistor
subset
trench
groove
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CN107959489B (zh
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潘继
雷燮光
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Alpha and Omega Semiconductor Ltd
NATIONS SEMICONDUCTOR (CAYMAN) Ltd
Alpha and Omega Semiconductor Inc
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NATIONS SEMICONDUCTOR (CAYMAN) Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明涉及一种开关电路，包括导电类型相同的一个第一MOS晶体管和一个第二MOS晶体管，并联在开关电路的第一端和第二端之间，第一和第二MOS晶体管具有各自的栅极端，耦合到控制端上，以接收控制信号，接通或断开第一和第二MOS晶体管。第一MOS晶体管的特征在于第一反向栅极至漏极电容（Crss），第二MOS晶体管的特征在于第二Crss，第二Crss大于第一Crss。

Description

带有可控相位节点振铃的开关电路
技术领域
本发明主要涉及集成电路，更确切的说是关于具有金属-氧化物-半导体场效应晶体管（MOSFET）的集成电路器件。
背景技术
微处理器和存储设备等集成电路在每个器件上都含有多个MOSFET晶体管，提供配置逻辑设计和/或数据存储所需的基本开关功能。在一个示例中，降压变换器等直流到直流功率转换器通常配置MOSFET作为其开关器件。尤其是降压转换器广泛应用于将较高输入电压转换成较低输出电压的行业。同步降压转换器包括一对开关器件，串联耦合在输入电压源。开关器件通常为MOSFET。图1表示传统的降压转换器，包括一个高端开关（HSFET）和一个低端开关（LSFET）。高端开关102耦合到电压源（Vin），低端开关104接地。通常包括一个电感器（L）和一个电容器（Cout）的输出滤波器，漏极端这对开关102和104形成的结（即相位节点或开关节点）105，以便为负载提供输出电压。控制器110驱使开关，将输出滤波器连接到电压源或接地，以便将输出电压维持在预置水平。
同步绝缘区设计中的问题之一在于电压过冲，以及相位节点处的振铃。由于对较高性能器件的要求不断提高，人们希望高端MOSFET的开关速度越来越快。开关速度越快，相位节点的电压转换越快。快速的电压转换可能导致低端开关无意中接通，导致转换器失效，降低效率。另外，由于振铃的大小是高端MOSFET的开关速度的函数，因此这可能会引起相位节点振铃。相位节点电压尖峰可能导致功率开关失效或不必要的压力。
利用多种技术，控制相位节点振铃。如图1所示，升压电阻器RBOOT和高端栅极电阻器RGH已经包含在图1所示的同步降压转换器中，用于控制相位节点振铃现象。确切地说，升压电阻器RBOOT可以减缓高端MOSFET的接通，而不影响断开。另外，高端栅极电阻器RGH与栅极串联，可以增大高端MOSFET的接通和断开时间，控制相位节点上升和下降的振铃。另一个建议是在低端开关中集成肖特基二极管，以降低恢复电荷，从而避免在相位节点处出现电压尖峰。有必要设计一种开关电路，可以适当地控制同步降压转换器的相位节点振铃。
正是在这样的背景下，提出了本发明的实施例。
发明内容
本发明的目的在于提出一种带有可控相位节点振铃的开关电路，以改善现有技术中的一个或多个问题。
本发明的一个方面在于提出一种具有第一端、第二端和控制端的开关电路，包括：具有相同导电类型的一个第一MOS晶体管和一个第二MOS晶体管，并联在第一端和第二端之间，第一和第二MOS晶体管各自的栅极端耦合到控制端，以接收控制信号，接通或断开第一和第二MOS晶体管；其中第一MOS晶体管具有第一反向栅极至漏极电容Crss，第二MOS晶体管具有第二反向栅极至漏极电容Crss，其中第二MOS晶体管的Crss大于第一MOS晶体管的Crss。
其中，第一MOS晶体管具有第一晶体管区，第二MOS晶体管具有第二晶体管区，第二晶体管区是第一晶体管区的一小部分。
其中，第一MOS晶体管和第二MOS晶体管为分立的MOS晶体管。
其中，第一MOS晶体管和第二MOS晶体管形成在一个公共半导体衬底的一个公共有源器件区中。
其中，第二MOS晶体管的第二晶体管区占公共有源器件区总面积的0.1%至15%之间。
其中，每个第一MOS晶体管和第二MOS晶体管都由一个或多个沟槽晶体管构成，一个或多个沟槽晶体管中的每个晶体管都具有一个形成在公共半导体衬底上半导体层沟槽中的栅极端，一个形成在半导体层中的本体区以及一个形成在沟槽附近的源极区。
其中，第二MOS晶体管的一个或多个沟槽晶体管中的每个沟槽晶体管都包括一个沟槽和栅极，形成在半导体层中，且比第一MOS晶体管的一个或多个沟槽晶体管延伸到更深处。
其中，第一和第二MOS晶体管的一个或多个沟槽晶体管中的每个沟槽都形成到公共深度，半导体层中所形成的本体区的深度对于第一MOS晶体管来说大于第二MOS晶体管。
其中，开关电路为降压转换器的高端开关。
其中，降压转换器包括具有一个输入端、一个输出端和一个低端控制端的低端开关，其中第二端连接到输入端。
本发明的另一个方面在于提出一种用于制备开关电路的方法，包括：在第一导电类型的半导体层中，制备一个沟槽晶体管晶胞阵列，沟槽晶体管晶胞由沟槽栅极结构限定，每个所述的栅极沟槽结构都包括一个形成在半导体层中的沟槽，以及一个形成在沟槽中的绝缘栅电极；在沟槽晶体管晶胞的第一子集中，制备与第一导电类型相反的第二导电类型的第一本体区，第一本体区和沟槽晶体管晶胞的第一子集的沟槽从第一本体区底部到第一子集中栅极沟槽底部的第一距离与第一反向栅极至漏极电容Crss有关；在沟槽晶体管晶胞的第二子集中，制备与第一导电类型相反的第二导电类型的第二本体区，第二本体区和沟槽晶体管晶胞的第二子集的沟槽从第二本体区底部到第二子集中栅极沟槽底部的第二距离与第二反向栅极至漏极电容Crss有关，其中第二距离大于第一距离；并且在沟槽晶体管晶胞的阵列中制备源极区。
其中，制备沟槽晶体管晶胞阵列包括在第二子集中制备栅极沟槽，使得第二子集中栅极沟槽底部的深度大于第一子集中栅极沟槽底部的深度，并且其中制备第一和第二本体区包括制备第一本体区，使得第一本体区底部与第二本体区底部的深度相同。
其中，在第二子集中制备栅极沟槽，使得第二子集中栅极沟槽底部的深度大于第一子集中栅极沟槽底部的深度，包括在第一和第二子集中将沟槽刻蚀到第一深度，用掩膜保护第一子集中的沟槽，同时保留第二子集中的沟槽不带掩膜，将第二子集中的沟槽刻蚀到第二深度，第二深度比第一深度更深。
其中，在第二子集中制备栅极沟槽使得第二子集中栅极沟槽底部的深度大于第一子集中栅极沟槽底部的深度，包括利用第一沟槽掩膜，将第二子集中的沟槽刻蚀到特定深度，然后利用第二沟槽掩膜，刻蚀第一子集中的沟槽，同时保留第二子集中的沟槽不带掩膜，将第二子集中的沟槽刻蚀到第二深度，第二深度比第一深度更深。
其中，制备沟槽晶体管晶胞的阵列包括在第一和第二子集中制备栅极沟槽到第一和第二子集中栅极沟槽底部的公共深度，其中制备第一和第二本体区包括制备第一本体区，使得第二本体区的底部深度大于第一本体区底部深度。
其中，制备第一本体区使得第二本体区底部深度大于第一本体区底部深度，包括利用第一注入工艺，在第一注入能量下制备第一和第二本体区到第一深度，用掩膜保护第二本体区不被第二次注入，同时保留第一本体区不带掩膜，在第一本体区中第二能量下进行第二次注入，第二能量大于第一能量。
其中，制备沟槽晶体管晶胞的阵列包括在第二子集中制备栅极沟槽，使得第二子集中栅极沟槽的底部深度大于第一子集中栅极沟槽的底部深度，其中制备第一和第二本体区包括制备第一本体区，使得第二本体区底部深度大于第一本体区底部深度。
阅读以下详细说明的实施例并参照各种附图，本发明的这些特点和优势对于本领域的技术人员来说，无疑将显而易见。
附图说明
图1表示一种传统的降压转换器的电路图；
图2表示依据本发明的各个方面，一种开关电路的电路图；
图3A表示部分传统的沟槽MOSFET的剖面示意图；
图3表示图2所示的开关电路的示例布局；
图4A-4N表示在本发明的一个实施例中，用于制备图2所示开关电路的制备工艺剖面图；
图5A-5J表示在本发明的一个可选实施例中，用于图2所示开关电路的制备工艺剖面图；
图6表示依据本发明的各个方面，一种开关电路的电路图；
图7表示图6所示开关电路的相位节点的波形；
图8表示依据本发明的各个方面，一种降压转换器的电路图。
具体实施方式
本发明的各个方面提出了用开关电路替代传统的低端MOSFET开关，允许同步降压转换器具有平滑的相位节点波形。本发明的各个方面包括一个具有主MOS晶体管和二级MOS晶体管并联的开关电路。主MOS晶体管的特点是具有第一反向栅极至漏极电容Crss和第一阈值电压。二级MOS晶体管的特点是具有第二Crss和第二阈值电压。在一些实施例中，可以通过提高二级MOS晶体管的Crss，减少使用这种开关电路的同步降压转换器的相位节点电压振铃，从而使第二Crss大于第一Crss。在一些实施例中，通过降低二级MOS晶体管的阈值电压，可以进一步减少相位节点电压振铃，从而使第二阈值电压低于第一阈值电压。在一些其他实施例中，通过增大二级MOS晶体管的Crss并降低二级MOS晶体管的阈值电压，可以减少相位节点电压振铃，从而使第二Crss大于第一Crss，并且第二阈值电压低于第一阈值电压。
平滑同步降压转换器相位节点波形的一种方法是用主MOS晶体管和并联的二级MOS晶体管代替传统的单独低端MOSFET，并联的二级MOS晶体管与主MOS晶体管相比，具有较高的Crss。图2表示根据本发明的各个方面，开关电路200可以用作例如低端开关104，用在图1所示的降压转换器中。开关电路200具有第一端，例如漏极D，第二端，例如源极S，以及一个控制端，例如栅极G。开关电路200具有两个MOSFET，一个具有常规Crss的主MOS晶体管210以及一个具有高Crss的二级MOS晶体管220，并联在第一端D和第二端S之间。主MOS晶体管和二级MOS晶体管210和220具有各自的栅极端，耦合到控制端G上，以接收控制信号，接通或断开主MOS晶体管和二级MOS晶体管210、220。
主MOS晶体管210和二级MOS晶体管220的导电性相同。主MOS晶体管210和二级MOS晶体管220形成在公共半导体衬底的公共有源器件区中。确切地说，每个主MOS晶体管210和二级MOS晶体管220都由一个或多个沟槽晶体管构成。每个沟槽晶体管都具有一个形成在公共半导体衬底上半导体层中的沟槽中的栅极端，一个形成在半导体层中的本体区以及一个形成在沟槽附近的源极区。
主MOS晶体管210的区域为常规Crss区，二级MOS晶体管220的区域为高Crss区。高Crss区与常规Crss区的比例影响相位节点峰值电压。区域比例越高，导致相位节点电压月底，从而获得平滑的相位节点波形。还可选择，高Crss区中的Crss越高，实现减小相位节点峰值电压所需效果的区域比例越小。可以根据相位节点峰值电压所需的减小量，预定义该比例。作为示例，但不作为局限，高Crss区可以占公共有源器件区总面积的0.1%到15%之间。
图3A表示一部分传统的沟槽MOSFET的剖面示意图。在本行业中众所周知，Crss与本体区320的底部和栅极沟槽340的底部之间的深度基本成正比，如图3A所示。因此，提高Crss的一种方式是增大高Crss区中栅极沟槽340的沟槽深度。另一种方式是减小有源区的高Crss区中本体区320的深度。应注意的是，在一些实施例中，可以通过较深的栅极沟槽与高Crss区中较浅的本体区相结合，提高Crss。
我们希望，二级MOS晶体管220的区域应均匀分布在主MOS晶体管210的区域。图3表示形成在半导体衬底上开关电路200的示例布局，包括主MOS晶体管210和二级MOS晶体管220，而没有显示出顶部源极金属层。栅极沟槽与源极区呈平行条纹带，沉积在带有接触开口的并联栅极沟槽之间的衬底上方，接触开口通过源极区打开。二级MOS晶体管220的部分沿每个条纹MOS结构沉积，构成二级MOS晶体管220的条纹，其方向与栅极沟槽条纹方向垂直。还可选择，选定特定栅极沟槽的整个长度，在栅极沟槽条纹的方向上，形成二级MOS晶体管220的条纹。
第一实施例
图4A-4J表示制备图2所示开关电路制备工艺的剖面图，二级MOS晶体管220的每个沟槽晶体管都有栅极沟槽，在半导体层中比主MOS晶体管210的沟槽晶体管的栅极沟槽更深处。
参见图4A，该工艺使用第一导电类型的半导体衬底410作为初始材料。在一些实施例中，衬底410包括N-型外延层，在重掺杂N型（N+）硅晶圆上方。在衬底410上使用一个掩膜412，含有开口，为主MOS晶体管210和二级MOS晶体管220的沟槽晶体管，限定多个栅极沟槽的位置。在图4B中，进行刻蚀工艺，向下刻蚀下方衬底410相应的部分，以形成多个栅极沟槽440。
利用另一个掩膜414，在常规Crss区中掩膜栅极沟槽440a（也就是对主MOS晶体管210的沟槽晶体管来说的栅极沟槽），并且暴露出高Crss区中的栅极沟槽440b（也就是对二级MOS晶体管220的沟槽晶体管来说的栅极沟槽）。进行另一个刻蚀工艺，使栅极沟槽440b更深，如图4C所示。然后，除去掩膜414，如图4C’所示。参见图4D-4J，如下所述进行后续处理。
在一个可选实施例中，如图4K-4N所示，通过修饰两个刻蚀工艺之间的掩膜，形成两种不同深度的沟槽。确切地说，如图4K所示，在衬底410上，使用具有第一组开口413的掩膜412。进行第一次刻蚀工艺，如图4L所示，在衬底中将栅极沟槽440b刻蚀到初始深度。然后，在掩膜412中形成额外开口413’，如图4M所示。还可选择，除去掩膜412，形成具有开口的第二掩膜，对应原始开口413和额外开口413’。第二次刻蚀工艺，通过额外开口413’刻蚀衬底410，形成栅极沟槽440a，而第二次刻蚀工艺还通过原始开口413刻蚀衬底，以加深沟槽440b。然后，除去掩膜412，参见图4D-4J，如下所述进行后续处理。
确切地说，形成各自深度的沟槽440a、440b之后，除去掩膜，可以生长一个牺牲氧化层（图中没有表示出），然后除去，以改善硅表面。参见图4D，沿栅极沟槽440a和440b的内表面，形成绝缘层（例如栅极氧化物）444。在带有回刻的栅极氧化层444上方，放置导电材料，形成栅极电极442。在一些实施例中，导电材料可以是原位掺杂或未掺杂的多晶硅。可以在沟槽上方，形成电介质层446，盖住沟槽，并且在衬底410上方，作为注入缓冲层。
参见图4E，进行全面本体注入，形成本体区420。掺杂离子的导电类型与衬底410的掺杂导电类型相反。在一些实施例中，对于N-通道器件来说，掺杂离子可以是硼离子。在一些实施例中，对于P-通道来说，可以使用磷或砷离子。然后，利用热激发掺杂原子，驱使掺杂物扩散，形成本体区420，如图4F所示。
参见图4G，进行源极注入和刻蚀，在衬底410的顶面中形成源极区430。掺杂离子的导电类型与衬底410的掺杂导电类型相同。在一些实施例中，对于N-通道器件来说，掺杂离子可以是砷离子。还可选择，对于P-通道器件来说，可以注入硼离子。
然后，在衬底410上方放置一个平面电介质层450，如图4H所示。在一些实施例中，通过低温氧化工艺，利用含有硼酸的硅玻璃材料（BPSG），形成电介质层450。
然后，在电介质层450上使用接触光致抗蚀剂（图中没有表示出），在接触沟槽的位置处具有一个开口的图案。进行刻蚀工艺，除去电介质层450的未覆盖部分，通过源极区430，在本体区420中形成接触沟槽460，如图4I所示。
放置金属层470，填充接触开口，互连所有的源极区，形成主MOS晶体管210和二级MOS晶体管220并联。
第二实施例
图5A-5J表示对二级MOS晶体管220的每个沟槽晶体管制备本体区，与主MOS晶体管210的沟槽晶体管的本体区相比，深度更浅，图2所示开关电路的制备工艺剖面图。
参见图5A，该工艺使用第一导电类型的半导体衬底510作为初始材料。在一些实施例中，衬底510包括一个N-型外延层，在重掺杂N型（N+）硅晶圆上方。在衬底510上使用掩膜512，包括开口，为主MOS晶体管210和二级MOS晶体管220的沟槽晶体管，限定栅极沟槽的位置。如图5B所示，进行刻蚀工艺，向下刻蚀下方的衬底510的相应部分，形成多个栅极沟槽540。然后，除去掩膜512，如图5B’所示。
然后，生长一个牺牲氧化层（图中没有表示出）并除去，以改善硅表面。沿栅极沟槽540的内表面形成一个绝缘层（例如栅极氧化物）544。在带有回刻的栅极氧化层544上方，放置导电材料，形成栅极电极542。在一些实施例中，导电材料可以是原位掺杂的或未掺杂的多晶硅。在沟槽上方形成电介质层546，覆盖沟槽，在衬底510上方作为一个注入缓冲层，如图5C所示。
参见图5D，用较低能量进行第一全面本体注入，形成本体区520。掺杂离子的导电类型与衬底510的掺杂类型相反。在一些实施例中，对于N-通道器件来说，掺杂离子可以是硼离子。在一些实施例中，对于P-通道器件来说，掺杂离子可以是磷或砷离子。在一些实施例中，注入到本体区中的掺杂离子剂量，例如硼离子可以注入到1e13cm-2左右，能量约为100KeV。第一次低能本体注入之后，所选的本体区520a对应高Crss区（也就是对于二级MOS晶体管220的沟槽晶体管来说的本体区），受注入掩膜522保护。在较高能量下进行另一次本体注入，如图5E所示，通过掩膜中的开口。换言之，在第二次本体注入中，掺杂离子仅注入到常规Crss区中的本体区520b中（也就是对于主MOS晶体管210的沟槽晶体管来说的本体区）。因此，与高Crss区中的本体区520a相比，本体区520b在衬底510中较深处。在一些实施例中，到本体区520b中第二次本体注入的掺杂物（例如硼）离子剂量，例如约为8e12cm-2左右，能量约为150KeV。利用热激活掺杂原子，驱使掺杂物扩散，形成本体区520a和520b，如图5F所示。
参见图5G，进行源极注入，在衬底510的顶面中形成源极区530。掺杂离子的导电类型与衬底510的掺杂类型相同。在一些实施例中，对于N-通道器件来说，可以注入深离子。还可选择，对于P-通道器件来说，可以注入硼离子。
然后，在衬底510上方，放置一个平整的电介质层550，如图5H所示。在一些实施例中，通过低温氧化工艺，利用含有硼酸的硅玻璃（BPSG）材料，形成电介质层550。
在电介质层550上使用接触光致抗蚀剂（图中没有表示出），带有在接触沟槽位置处具有一个开口的图案。利用刻蚀工艺，除去电介质层550未被覆盖的部分，通过本体区520a和520b中的源极区530，形成接触沟槽560，如图5I所示。
然后，放置一个金属层570，填充接触开口，并互连所有的源极区，以形成主MOS晶体管210和MOS晶体管220并联。
阈值电压
通过用带有较低开启阈值电压（Vth）的主MOS晶体管和并联的二级MOS晶体管代替传统的独立MSOFET，使同步减压转换器的相位节点波形平滑的另一种方式。由于在低于相位节点电压尖峰导致的栅极尖峰下的接通阈值电压下，二级MOS晶体管接通，因此该方式可以保持很低的相位节点峰值振铃。确切地说，当高端MOSFET接通时，低端FET中电流下降。VDS中的尖峰触发足够高的VGS尖峰，并用较低的接通阈值电压接通二级MOS晶体管，从而降低相位节点尖峰的电压。图6表示依据本发明的各个方面，开关600电路。开关电路600具有一个第一端D、一个第二端S和一个控制端G。开关电路600具有两个MOSFET、一个具有常规Vth的主MOS晶体管610以及一个具有较低Vth并联在第一端D和第二端S之间的二级MOS晶体管620。主MOS晶体管610和二级MOS晶体管620具有各自的栅极端耦合到控制端G上，以接收控制信号，接通或断开主MOS晶体管610和二级MOS晶体管620。
主MOS晶体管610和二级MOS晶体管620导电类型相同。主MOS晶体管610和二级MOS晶体管620形成在一个公共半导体衬底的公共有源器件区中。确切地说，每个主MOS晶体管610和二级MOS晶体管620都由一个或多个沟槽晶体管构成。每个沟槽晶体管都有一个形成在公共半导体衬底上半导体层沟槽中的栅极端，一个形成在半导体层中的本体区以及一个形成在沟槽附近的源极区。主MOS晶体管610的区域为常规Vth区，二级MOS晶体管620的区域为较低的Vth区。较低的Vth区和常规Vth区之比影响相位节点峰值电压。图7所示波形，表示随着更大比例的公共有源器件区总区域中的低Vth区，相位节点峰值振铃变得更低。根据相位节点峰值电压所需的减少量，可以预定义比例。作为示例，但不作为局限，低Vth区占公共有源器件区总区域的5%至15%。二级MOS晶体管的Vth越低，实现减少相位节点振铃所需效果，需要的区域比例越低。
关于图6所示开关电路的制备工艺，进行两次本体注入。确切地说，首先进行常规的全面本体注入，然后利用本体掩膜，进行第二次本体注入。本体掩膜覆盖低Vth区，使得掺杂离子仅注入到第二次本体注入的常规Vth区。要注意的是，可以通过低注入能量降低阈值电压，并且通过降低注入的剂量，可以进一步降低阈值电压。在一些实施例中，注入到本体区中掺杂离子（例如硼离子）的剂量，例如在第一次本体注入中，从2e12cm-2至2e13cm-2之间，能量约为50KeV~1MeV，在第二次本体注入中，从2e12cm-2至2e13cm-2之间，能量约为80KeV~1MeV。制备工艺的详情可以参见2014年4月14日存档的共同所有的美国专利申请号14/253,568，公开为美国专利申请公开2015/0295495，提出了一种具有并联晶体管对（其中一个晶体管的阈值电压低于另一个晶体管）的开关电路。美国专利申请公开2015/0295495的全文特此引用，以作参考。
如图8所示，这种类型的开关电路可用于降压转换器，例如作为如图1所示的低端开关104。降压转换器包括例如带有自身输入（例如漏极）端D、输出（例如源极）端S和低端控制端（例如栅极）G的高端开关102。低端开关的输入连接到高端开关的第二（例如输出）端。
尽管本发明关于某些较佳的版本已经做了详细的叙述，但是仍可能存在各种不同的修正、变化和等效情况。因此，本发明的范围不应由上述说明决定，与之相反，本发明的范围应参照所附的权利要求书及其全部等效内容。任何可选件（无论首选与否），都可与其他任何可选件（无论首选与否）组合。在以下权利要求中，除非特别声明，否则不定冠词“一个” 或“一种”都指下文内容中的一个或多个项目的数量。除非用“意思是”明确指出限定功能，否则所附的权利要求书并不应认为是意义-加-功能的局限。

Claims (17)

1.一种具有第一端、第二端和控制端的开关电路，其特征在于，该开关电路包括：
具有相同导电类型的一个第一MOS晶体管和一个第二MOS晶体管，并联在第一端和第二端之间，第一和第二MOS晶体管各自的栅极端耦合到控制端，以接收控制信号，接通或断开第一和第二MOS晶体管；
其中第一MOS晶体管具有第一反向栅极至漏极电容Crss，第二MOS晶体管具有第二反向栅极至漏极电容Crss，其中第二MOS晶体管的Crss大于第一MOS晶体管的Crss。
2.如权利要求1所述的开关电路，其特征在于，第一MOS晶体管具有第一晶体管区，第二MOS晶体管具有第二晶体管区，第二晶体管区是第一晶体管区的一小部分。
3.如权利要求1所述的开关电路，其特征在于，第一MOS晶体管和第二MOS晶体管为分立的MOS晶体管。
4.如权利要求1所述的开关电路，其特征在于，第一MOS晶体管和第二MOS晶体管形成在一个公共半导体衬底的一个公共有源器件区中。
5.如权利要求4所述的开关电路，其特征在于，第二MOS晶体管的第二晶体管区占公共有源器件区总面积的0.1%至15%之间。
6.如权利要求1所述的开关电路，其特征在于，每个第一MOS晶体管和第二MOS晶体管都由一个或多个沟槽晶体管构成，一个或多个沟槽晶体管中的每个晶体管都具有一个形成在公共半导体衬底上半导体层沟槽中的栅极端，一个形成在半导体层中的本体区以及一个形成在沟槽附近的源极区。
7.如权利要求6所述的开关电路，其特征在于，第二MOS晶体管的一个或多个沟槽晶体管中的每个沟槽晶体管都包括一个沟槽和栅极，形成在半导体层中，且比第一MOS晶体管的一个或多个沟槽晶体管延伸到更深处。
8.如权利要求6所述的开关电路，其特征在于，第一和第二MOS晶体管的一个或多个沟槽晶体管中的每个沟槽都形成到公共深度，半导体层中所形成的本体区的深度对于第一MOS晶体管来说大于第二MOS晶体管。
9.如权利要求1所述的开关电路，其特征在于，开关电路为降压转换器的高端开关。
10.如权利要求9所述的开关电路，其特征在于，降压转换器包括具有一个输入端、一个输出端和一个低端控制端的低端开关，其中第二端连接到输入端。
11.一种用于制备开关电路的方法，其特征在于，包括：
在第一导电类型的半导体层中，制备一个沟槽晶体管晶胞阵列，沟槽晶体管晶胞由沟槽栅极结构限定，每个所述的栅极沟槽结构都包括一个形成在半导体层中的沟槽，以及一个形成在沟槽中的绝缘栅电极；
在沟槽晶体管晶胞的第一子集中，制备与第一导电类型相反的第二导电类型的第一本体区，第一本体区和沟槽晶体管晶胞的第一子集的沟槽从第一本体区底部到第一子集中栅极沟槽底部的第一距离与第一反向栅极至漏极电容Crss有关；
在沟槽晶体管晶胞的第二子集中，制备与第一导电类型相反的第二导电类型的第二本体区，第二本体区和沟槽晶体管晶胞的第二子集的沟槽从第二本体区底部到第二子集中栅极沟槽底部的第二距离与第二反向栅极至漏极电容Crss有关，其中第二距离大于第一距离；并且
在沟槽晶体管晶胞的阵列中制备源极区。
12.如权利要求11所述的方法，其特征在于，制备沟槽晶体管晶胞阵列包括在第二子集中制备栅极沟槽，使得第二子集中栅极沟槽底部的深度大于第一子集中栅极沟槽底部的深度，并且其中制备第一和第二本体区包括制备第一本体区，使得第一本体区底部与第二本体区底部的深度相同。
13.如权利要求12所述的方法，其特征在于，在第二子集中制备栅极沟槽，使得第二子集中栅极沟槽底部的深度大于第一子集中栅极沟槽底部的深度，包括在第一和第二子集中将沟槽刻蚀到第一深度，用掩膜保护第一子集中的沟槽，同时保留第二子集中的沟槽不带掩膜，将第二子集中的沟槽刻蚀到第二深度，第二深度比第一深度更深。
14.如权利要求12所述的方法，其特征在于，在第二子集中制备栅极沟槽使得第二子集中栅极沟槽底部的深度大于第一子集中栅极沟槽底部的深度，包括利用第一沟槽掩膜，将第二子集中的沟槽刻蚀到特定深度，然后利用第二沟槽掩膜，刻蚀第一子集中的沟槽，同时保留第二子集中的沟槽不带掩膜，将第二子集中的沟槽刻蚀到第二深度，第二深度比第一深度更深。
15.如权利要求11所述的方法，其特征在于，制备沟槽晶体管晶胞的阵列包括在第一和第二子集中制备栅极沟槽到第一和第二子集中栅极沟槽底部的公共深度，其中制备第一和第二本体区包括制备第一本体区，使得第二本体区的底部深度大于第一本体区底部深度。
16.如权利要求15所述的方法，其特征在于，制备第一本体区使得第二本体区底部深度大于第一本体区底部深度，包括利用第一注入工艺，在第一注入能量下制备第一和第二本体区到第一深度，用掩膜保护第二本体区不被第二次注入，同时保留第一本体区不带掩膜，在第一本体区中第二能量下进行第二次注入，第二能量大于第一能量。
17.如权利要求11所述的方法，其特征在于，制备沟槽晶体管晶胞的阵列包括在第二子集中制备栅极沟槽，使得第二子集中栅极沟槽的底部深度大于第一子集中栅极沟槽的底部深度，其中制备第一和第二本体区包括制备第一本体区，使得第二本体区底部深度大于第一本体区底部深度。
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