TW201733009A - 提升直接接合的接觸對準容限 - Google Patents

提升直接接合的接觸對準容限 Download PDF

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Publication number
TW201733009A
TW201733009A TW105141779A TW105141779A TW201733009A TW 201733009 A TW201733009 A TW 201733009A TW 105141779 A TW105141779 A TW 105141779A TW 105141779 A TW105141779 A TW 105141779A TW 201733009 A TW201733009 A TW 201733009A
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Taiwan
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contact
metal
bonding
contact feature
feature
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TW105141779A
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TWI696243B (zh
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保羅Ｍ 恩奎斯特
蓋烏斯 吉爾曼 方騰
賈維爾Ａ 狄拉克魯茲
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增普拓尼克斯公司
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Abstract

一種接合裝置結構包括：第一基板，其具有第一組傳導性接觸結構(較佳的是連接到一裝置或電路)，並且具有在第一基板上相鄰接觸結構的第一非金屬性區域；第二基板，其具有第二組傳導性接觸結構(較佳的是連接到一裝置或電路)，並且具有在第二基板上相鄰接觸結構的第二非金屬性區域；以及在第一組和第二組接觸結構之間的接觸接合介面，其是藉由將第一非金屬性區域接觸接合至第二非金屬性區域所形成。接觸結構包括在兩個基板上是非平行的長形接觸特徵(諸如個別線路或在格柵中連接的線路)，而在相交點接觸。因而，改善了對準容限同時使凹陷和寄生電容最小化。

Description

提升直接接合的接觸對準容限
本發明的技術領域是有關於直接晶圓接合，並且更具體地說是有關於要被用於半導體裝置和積體電路製造中的基板的接合和電性互連。
相關申請案的交互參照
本申請案請求於2015年12月18日所提交的美國臨時專利申請案第62/269,412號的權益，其整體內容基於一切目的在此處以引用的方式被併入。
隨著逼近了習知CMOS裝置的物理極限且對於高效能電子系統具有迫切需求，系統單晶片(SOC)變成半導體產業的一種自然解決方案。為了製備系統單晶片，在一晶片上需要各種不同的功能。雖然矽技術是處理大量裝置的主流技術，但是許多想要的電路及光電功能現今可從矽之外的材料製成的個別裝置和/或電路來有效獲得。因此，將非矽基元件與矽基元件整合的混合式系統有可能提供單獨採用純矽或純非矽元件所無法提供的獨特SOC功能。
一種異質性裝置整合的方法已經將不相似的材料異質磊晶 成長在矽上。至今為止，此異質磊晶成長已經在異質磊晶成長膜中產生高密度的瑕疵，其大部份是因為非矽膜與基板之間的晶格常數不匹配所導致。
另一種異質性裝置整合的途徑已經採用晶圓接合技術。然而，在升高溫度下具有不同熱膨脹係數的不相似材料的晶圓接合會導入會造成錯位產生、脫膠或裂痕的熱應力。因此，低溫接合是有需要的。如果不相似材料包括低分解溫度的材料或溫度敏感性裝置(舉例而言，諸如InP異質接合雙極性電晶體或具有超淺源極和汲極輪廓的經處理Si裝置)，則低溫接合對於不相似材料的接合亦很重要。
在含有不同材料的相同晶片上產生不同功能所需要的製程設計是困難並且難以進行最佳化。事實上，所產生的許多SOC晶片(特別是具有較大整合尺寸者)展現出低的良率。一種途徑已經藉由晶圓黏著劑接合和層轉移來互連經完全處理的IC。舉例而言，請參考Y.Hayashi、S.Wada、K.Kajiyana、K.Oyama、R.Koh、S.Takahashi以及T.Kunio的Symp.VLSI Tech.Dig.95(1990)的研討會文件及美國專利案5,563,084號，兩個參考文件的整體內容在此處以引用方式併入。然而，晶圓黏著劑接合通常在升高溫度下操作且受到熱應力、滲氣、氣泡形成以及黏著劑不穩定等困擾，導致製程的良率降低且隨時間經過有不良的可靠度。並且，黏著劑接合通常不是密封的。
晶圓直接接合是一種可使晶圓在室溫下接合而不用任何黏著劑之技術。室溫直接晶圓接合通常是密封的。其不像黏著劑接合一樣容易導入應力及非均質性。再者，如果低溫接合晶圓對可承受薄化製程，則當經接合對中的一晶圓被薄化至比特定材料組合的各自臨界值更小的厚度 時，可加以避免在後續熱處理步驟期間的層中產生錯位差排和經接合對的滑動或裂痕。舉例而言，請參考Q.-Y.Tong以及U.Gösele的Semiconductor Wafer Bonding：Science and Technology,John Wiley & Sons,New York,(1999)，該文件的整體內容在此處以引用方式併入。
再者，晶圓直接接合及層轉移是一種VLSI(超大型積體(Very Large Scale Integration))相容性、高可變性且可製造的技術，因而適於形成三維系統單晶片(3-D SOC)。可將3-D SOC途徑視為既有積體電路的整合以在晶片上形成系統。
再者，隨著整合複雜度的增高，整合製程以在低溫下且較佳的是在室溫下來堅固地聯合多樣電路導致產生較低或沒有額外應力及更可靠的電路的需求亦增高。
對於3D-SOC製備而言，被接合的晶圓或晶粒之間的金屬的低溫或室溫直接晶圓接合是有利的。此直接金屬接合可被使用以與在晶圓或晶粒之間非金屬的直接晶圓接合結合，以在當晶圓或晶粒被機械接合時在它們之間導致電性互連。同時的金屬和非金屬接合可消除後接合處理(如基板薄化、通孔蝕刻和互連金屬化)的需要，以達成經接合的晶圓或晶粒之間的電性互連。可使用極小的接合金屬墊，導致有極低的寄生阻抗且導致減少的功率及增加的頻寬容量。
金屬與乾淨表面的接合是為人熟知的現象。舉例而言，已經將熱壓縮導線接合施加至晶圓級接合。一般採用溫度、壓力及低硬度金屬，且通常會導致殘留應力。舉例而言，請參考M.A.Schmidt的Proc.IEEE,Vol.86,No.8,1575(1998)；Y.Li、R.W.Bower和I.Bencuya的Jpn.J.Appl.Phys.Vol. 37,L1068(1988)。在250至350℃下Pd金屬層塗覆的矽或III V化合物晶圓的直接接合已經被B.Aspar、E.Jalaguier、A.Mas、C.Locatelli、O.Rayssac、H.Moricean、S.Pocas、A.Papon、J.Michasud and M.Bruel在Electon.Lett.,35,12(1999)中提到。然而，實際上是形成及接合Pd2Si矽化物或Pd-III V合金，而非金屬Pd。已經在覆晶接合下利用超音波及壓縮性負載在室溫下達成Au及Al的接合，舉例而言，請參考M.Hizukuri、N.Watanabe and T.Asano的Jpn.J.Appl.Phys.Vol.40,3044(2001)。已經在具有低於3x10-8mbar的基底壓力(base pressure)的超高真空(ultrahigh vacuum，UHV)系統中實現晶圓級的室溫金屬接合。通常，使用離子氬濺鍍或快速原子束來清潔接合表面，接著將外部壓力施加至接合基板。舉例而言，請參考T.Suga的Proc.The 2nd Intl.Symposium on semiconductor wafer bonding,the Electrochemical Soc.Proc.Vol.93-29,p.71(1993)。亦已經利用在具有小於3x10-8mbar基底壓力的UHV系統中在4至40μbar的Ar壓力的薄膜濺鍍沉積之後的施力來達成具有薄形濺鍍的Ti、Pt及Au膜的兩個Si基板之間的室溫接合。舉例而言，請參考T.Shimatsu,R.H.Mollema,D.Monsma,E.G.Keim and J.C.Lodder的J.Vac.Sci.Technol.A 16(4),2125(1998)。
金屬特徵或接點和非金屬場區域的直接接合是揭露於美國專利號第7,485,968號及美國專利號第6,962,835號，其每一者的揭示內容在此處以引用的方式被清楚地併入。然而，要實現來自兩個基板的金屬特徵的對準並實現可靠的金屬接合同時又要直接接合外圍的非金屬區域會是有挑戰性的。
在一實施例中，接合結構被揭示。所述接合結構可包括：第一半導體元件，其包括傳導性第一接觸結構和相鄰所述第一接觸結構的非金屬性第一接合區域，所述第一接觸結構包括傳導性第一長形接觸特徵。所述接合結構亦可包括：第二半導體元件，其包括傳導性第二接觸結構和相鄰所述第二接觸結構的非金屬性第二接合區域，所述第二接觸結構包括傳導性第二接觸特徵。所述第一接合區域可與所述第二接合區域接觸並且直接接合。所述第一長形接觸特徵可被定向以與所述第二接觸特徵非平行並且在所述第一長形接觸特徵和所述第二接觸特徵之間的相交點處與所述第二接觸特徵直接接觸。
在另一實施例中，接合方法被揭示。所述接合方法可包括：提供第一半導體元件，其包括傳導性第一接觸結構和相鄰所述第一接觸結構的非金屬性第一接合區域，所述第一接觸結構包括傳導性第一長形接觸特徵。所述方法可包括：提供第二半導體元件，其包括傳導性第二接觸結構和相鄰所述第二接觸結構的非金屬性第二接合區域，所述第二接觸結構包括傳導性第二接觸特徵。所述方法可包括：定向並且組裝所述第一半導體元件和所述第二半導體元件，使得所述第一長形接觸特徵和所述第二接觸特徵是非平行的。所述方法可包括：直接接合所述第一接合區域與所述第二接合區域。所述方法可包括：在所述第一長形接觸特徵和所述第二接觸特徵之間的相交點處，直接接合所述第一長形接觸特徵和所述第二接觸特徵。
在又另一實施例中，接合結構被揭示。所述接合結構可包括：第一半導體元件，其包括傳導性第一接觸結構和相鄰所述第一接觸結 構的非金屬性第一接合區域，所述第一接觸結構包括由多個相交線路所組成的傳導性第一格柵圖案。所述接合結構可包括：第二半導體元件，其包括傳導性第二接觸結構和相鄰所述第二接觸結構的非金屬性第二接合區域，所述第二接觸結構包括由多個相交線路所組成的傳導性第二格柵圖案。所述第一接合區域可與所述第二接合區域接觸並且直接接合。所述第一格柵圖案可與所述第二格柵圖案相交並且直接接觸。
在另一實施例中，接合結構被揭示。所述接合結構可包括：第一半導體元件，其包括傳導性第一接觸結構和圍繞所述第一接觸結構的非金屬性第一接合區域。所述第一接觸結構可包括傳導性第一長形接觸特徵，所述第一長形接觸特徵包括重度摻雜的半導體材料。所述第一接合區域可包括輕度摻雜或未摻雜的半導體材料。所述接合結構可包括：第二半導體元件，其包括傳導性第二接觸結構和圍繞所述第二接觸結構的非金屬性第二接合區域，所述第二接觸結構包括傳導性第二接觸特徵。所述第一接合區域可與所述第二接合區域接觸並且直接接合。所述第一長形接觸特徵可與所述第二接觸特徵直接接觸並且直接接合。
在又另一實施例中，半導體元件被揭示。所述半導體元件可包括：基板，其包括一或多層非金屬性材料。所述半導體元件可包括：多個傳導跡線，其被嵌入在所述基板中，所述跡線橫向地延伸穿過所述基板以橫向地繞送電性訊號。所述半導體元件可包括：長形接觸特徵，其沿著所述多個跡線中的第一跡線延伸並且直接接觸所述第一跡線，所述接觸特徵在所述基板的頂部表面處暴露。
因此，本發明的一個目的是以單一接合步驟在晶圓和晶粒之 間取得機械和電性連接。
本發明的另一個目的是提供一種低溫或室溫接合方法，具有半導體電路的晶圓或晶粒之間的金屬性接合可藉此在無需使用外部壓力的環境下被形成。
本發明的額外一個目的是提供一種低溫或室溫接合方法，具有半導體電路的晶圓或晶粒之間的任何金屬層的金屬性接合可藉此藉由使金屬層覆蓋有金或銅或鈀的薄膜在無需使用外部壓力的環境下以晶圓級在室溫下被形成。
本發明的又另一個目的是提供一種在無需使用外部壓力的環境中的晶圓級室溫接合方法，金屬性和共價結合是藉此在室溫下被同時形成於包括半導體電路而有金屬和其他非金屬層共存的晶圓或晶粒的接合表面上。
本發明的另一個目的是提供一種室溫接合方法，具有不同熱膨脹係數的不同基板或不同基板上的不同材料可藉此被接合在一起而不會在不同基板或不同基板上的不同材料之間產生災難性應力。
本發明的又另一個目的是提供一種室溫接合方法，在基板之間的接合強度藉此接近基板的機械斷裂強度。
本發明的另一個目的是提供一種接合裝置結構，其包括被個別製作於分開的基板上且接合於共同基板的裝置。
本發明的又另一個目的是提供一種方法和一種裝置，藉此可靠的機械接合可在室溫下或在接近室溫下被形成且可靠的電性接觸可用簡單的低溫退火被後續地形成。
本發明的這些與其他的目的是藉由一種接合方法和一種裝置結構來達成，裝置結構包括：第一基板，其具有第一多個金屬性接合墊(較佳的是被連接到一裝置或電路)，並且具有在第一基板上相鄰金屬性接合墊的第一非金屬性區域；第二基板，其具有與第一多個金屬性接合墊對準或可與第一多個金屬性接合墊對準的第二多個金屬性接合墊(較佳的是被連接到一第二裝置或電路)，並且具有在第二基板上相鄰金屬性接合墊的第二非金屬性區域；以及接觸接合介面，其在第一組金屬性接合墊和第二組金屬性接合墊之間。
10‧‧‧晶圓
11‧‧‧表面
12‧‧‧墊
13‧‧‧晶圓
14‧‧‧表面
15‧‧‧墊
16‧‧‧接合面
17‧‧‧接合面
20‧‧‧晶圓
21‧‧‧墊
22‧‧‧晶圓
23‧‧‧墊
24‧‧‧間隙
25‧‧‧接合
30‧‧‧晶粒
31‧‧‧金屬墊
32‧‧‧表面
33‧‧‧互連
34‧‧‧層
35‧‧‧金屬墊
36‧‧‧通孔
37‧‧‧晶圓
38‧‧‧墊
39‧‧‧通孔
40‧‧‧金屬墊
41‧‧‧表面
50‧‧‧基板
51‧‧‧互連
52‧‧‧層
53‧‧‧晶粒
54‧‧‧接點
55‧‧‧層
56‧‧‧墊
57‧‧‧墊
58‧‧‧層
59‧‧‧接合
60‧‧‧基板
61‧‧‧基板
62‧‧‧凹陷
63‧‧‧凹陷
64‧‧‧墊
65‧‧‧墊
66‧‧‧空隙
67‧‧‧部分
70‧‧‧基板
71‧‧‧基板
72‧‧‧墊
73‧‧‧墊
74‧‧‧凹陷
75‧‧‧部分
100‧‧‧接合結構
100’‧‧‧接合結構
101‧‧‧半導體元件
101a‧‧‧半導體元件
101b‧‧‧半導體元件
102‧‧‧接觸結構
103a‧‧‧接觸特徵
103b‧‧‧接觸特徵
104‧‧‧相交點
105‧‧‧互連
106‧‧‧接合區域
106a‧‧‧接合區域
106b‧‧‧接合區域
115a‧‧‧凹陷
115b‧‧‧凹陷
120‧‧‧間隙
120a‧‧‧跡線
120b‧‧‧跡線
122‧‧‧區段
124‧‧‧連接件
125‧‧‧接點
130‧‧‧介面
在當結合附圖考慮時通過參照下列詳細描述可變得更為理解本發明所揭示的實施例及其許多附隨優點，將容易地獲得對其之更全面的瞭解，其中：
圖1A是一對未接合基板的示意圖，其具有經對準金屬接合墊。
圖1B是一對未接合基板的示意圖，其具有已接觸的經對準金屬接合墊。
圖1C是一對已接觸基板的示意圖，其在遠離金屬接合墊的非金屬區域中被接合。
圖1D是一對已接觸基板的示意圖，其在橫跨除了靠近金屬接合墊的小的未接合環形面積之外的非金屬區域被接合。
圖2A是說明在接合之前具有多個接合墊的接合基板的示意圖。
圖2B是在接合墊被接觸之後接合基板的示意圖。
圖2C是當非傳導性區域被接合時接合基板的示意圖。
圖2D是示出了以金屬墊厚度2h為函數的未接合環形面積的寬度W的曲線圖，金屬墊厚度2h如插圖中所示分開半導體晶粒。
圖3A是在表面平坦化之後半導體晶粒或晶圓的示意圖。
圖3B是半導體晶粒或晶圓的示意圖，其中第二金屬層被形成且平坦化以具有在金屬墊上所打開的接觸窗口。
圖3C是具有第二金屬層的第二半導體晶粒或晶圓的示意圖。
圖3D是由二個晶粒或晶圓所組成的經對準金屬接合的示意圖。
圖4A是示出在氧化物塗層中的嵌入金屬墊的基板部件的示意圖。
圖4B是具有相對應金屬接合墊的一對未接合基板的示意圖。
圖4C是示出藉由非金屬區域接觸及接合時所產生的力所接觸的相對應金屬接合墊的一對接合基板的示意圖。
圖4D是被接合至較大基板的一對較小基板的示意圖。
圖5A是在金屬墊之下具有可變形材料或空隙的實施例的示意圖。
圖5B是在金屬墊之下具有可變形材料的實施例的示意圖。
圖5C是兩個如圖5A中所示的裝置接合在一起的示意圖。
圖6A是在非金屬表面的直接晶圓接合之前具有暴露於兩個裝置上的表面的可迴焊金屬材料的實施例的示意圖。
圖6B是具有在非金屬表面的直接晶圓接合之後被密封的可迴焊金屬材料的實施例的示意圖。
圖6C是具有在非金屬表面的直接晶圓接合密封住可迴焊金屬之後被迴焊的可迴焊金屬的實施例的示意圖。
圖7A是具有在非金屬表面的直接晶圓接合之前暴露於兩個裝置上的表面的可迴焊金屬材料的實施例的示意圖。
圖7B是具有在非金屬表面的直接晶圓接合之後被密封的可迴銲金屬材料的實施例的示意圖。
圖7C是具有在非金屬表面的直接晶圓接合密封住可迴銲金屬之後迴銲的可迴銲金屬的實施例的示意圖。
圖8A是在第一半導體元件和第二半導體元件被組裝在一起之前的兩個元件的示意性側邊截面圖。
圖8B是在接合區域被直接接合在一起之後中間接合結構的示意性側邊截面圖。
圖8C是在接觸特徵被直接接合在一起之後接合結構的示意性側邊截面圖。
圖9A是根據一實施例的接合半導體結構中的傳導特徵的位置的示意性俯視圖。
圖9B是圖9A的接合半導體結構的示意性側邊截面圖。
圖10是根據另一實施例的接合半導體結構中傳導特徵的位 置的示意性俯視圖。
圖11A是具有與對應下方跡線連接的多個長形接觸特徵的第一半導體元件的示意性平面圖。
圖11B是第一半導體元件的示範性接觸特徵和相關聯的下方跡線以及第二半導體元件的接觸特徵的示意性平面圖，第二半導體元件的接觸特徵被對準以在交叉指向上與第一半導體元件的接觸特徵接觸。
圖11C是兩個接合半導體元件的示意性側邊截面圖，兩個接合半導體元件在兩個元件的交叉接觸特徵之間具有直接連接。
圖12A是根據各種其他實施例的具有四邊形輪廓的傳導性接觸結構的示意性俯視圖。
圖12B是根據另一實施例的具有四邊形輪廓的多邊形傳導性接觸結構的示意性俯視圖。
圖12C是根據各種實施例的具有五邊形輪廓的傳導性接觸結構的示意性俯視圖。
圖12D是根據另一實施例的具有五邊形輪廓的傳導性接觸結構的示意性俯視圖。
圖12E是根據各種實施例的具有六邊形輪廓的傳導性接觸結構的示意性俯視圖。
圖12F是根據另一實施例的具有六邊形輪廓的傳導性接觸結構的示意性俯視圖。
圖12G是根據各種實施例的具有圓形輪廓的傳導性接觸結構的示意性俯視圖。
圖12H是根據另一實施例的具有圓形輪廓的傳導性接觸結構的示意性俯視圖。
現在參考圖式，其中幾個圖中類似的參考數字代表類似或對應的部件，更特別地參考解釋了接合製程的第一實施例的圖1A至圖1D及圖2。在第一實施例中，當分開的晶圓上的金屬接觸區域一旦對準而被位於金屬性區域周邊的非金屬性區域經歷室溫化學接合所產生的本徵力量給予接觸壓力接合時，將產生直接金屬-金屬接合。本說明書全文所使用的化學接合是被定義為當一晶圓的表面上的表面接合與一相對晶圓的表面上的表面接合起反應時所形成的接合強度，以形成橫越表面元件的直接接合，諸如共價結合。化學接合展示出高接合強度，例如接近晶圓材料的斷裂強度，因此不同於(舉例而言)只有凡德瓦鍵結的狀況。下面討論所揭示的實施例的方法所達成的化學接合強度的範例。顯著的力在化學接合製程中被形成。這些力可足夠大以隨著化學接合傳播於相對非金屬性區域之間而增加金屬性區域的內部壓力。
圖1A示出二個晶圓10和13，其具有各自相對的晶圓表面11和14。晶圓表面可以是鈍元素的半導體表面，可以是包括相對少量天然氧化物的鈍元素的半導體表面，或可以是諸如氧化物塗覆的表面的絕緣體。在各種實施例中，晶圓表面可包括以下的至少一種：玻璃、矽上絕緣體、氮化矽、碳化矽、藍寶石、鍺、砷化鎵、氮化鎵、聚合物、磷化銦或任何其他合適的材料。為了產生平滑、活化的表面，表面可以是如同在美國專利第6,984,571、6,902,987和6,500,694號中所描述的而製備，其每一者 的內容在此以引用的方式將其整體併入。諸如研磨或拋光和極微蝕刻(very slightly etching，VSE)的技術可被加以使用。接合層可被沉積且研磨或拋光，並且被稍微地蝕刻。所得的表面是輔助性的並且具有平坦且平滑的化學接合表面，其化學接合表面的粗糙度是在5Å至15Å的範圍中，較佳的是不大於10Å，並且更佳的是不大於5Å。
每一個晶圓皆包括在表面11和14中的一組金屬性的墊12和15以及相鄰金屬性接合墊的非金屬性區域。金屬性接合墊的非平坦性及表面粗糙度可能大於化學接合表面的非平坦性及表面粗糙度。墊12和15可(直接地或間接地)電性連接至內部電路和/或直通矽晶穿孔(TSV)，並且可用來將電性連接繞送至預先製作在晶圓上的各自裝置和/或電路。墊較佳的是在表面處理之前被形成，並且VSE較佳的是在形成墊之後進行。如同圖1A中所示，在各別晶圓上的墊12和15被對準。圖1B示出將晶圓放置在一起以使各自的墊接觸的晶圓。在此階段，墊12和15是可分離的。在圖1C中，輕微的額外壓力被施加至晶圓以使半導體晶圓中的一或兩者彈性變形，導致晶圓上的一些非金屬面積之間的接觸。所示的接觸位置僅是一個範例，並且可在不同位置處發生接觸。另外，可在超過一個點處發生接觸。此接觸引發化學的晶圓到晶圓接合，並且該接合結構是被示於圖1D中。接合面(bonding seam)16是在引發化學接合之後擴張，以產生如圖1D中所示的接合面17。接合強度最初是薄弱的並且隨著接合進行而增加，如同在美國專利第6,984,571、6,902,987和6,500,694號中所解釋的，在此處以引用的方式將其完整併入。相對的非金屬性區域是在室溫或低溫下被化學接合。
更詳細而言，當包括金屬接合墊的晶圓表面在室溫下接觸時，相對晶圓表面中的接觸的非金屬部分開始在接觸點或多個接觸點處形成接合，並且晶圓之間的吸引性接合力隨著接觸化學接合面積增加而增加。在沒有金屬墊存在的情況下，晶圓將橫跨整個晶圓表面接合。金屬墊的存在(雖然阻礙相對晶圓之間的接合面)並未阻止化學的晶圓到晶圓接合。由於金屬接合墊的延伸性和延展性的關係，在非金屬區域中藉由化學的晶圓到晶圓接合所產生的壓力可產生一力，金屬墊上的非平坦和/或粗糙區域可藉此變形而導致金屬墊的平坦性和/或粗糙度受到改善以及金屬墊之間有緊密接觸。藉由化學接合所產生的壓力是足以免除讓這些金屬墊彼此緊密接觸所施加的外部壓力。由於在配對介面處的金屬原子的相互擴散(inter-diffusion)或自擴散(self-diffusion)的關係，可在緊密接觸的金屬墊之間形成強的金屬性接合，甚至是在室溫下。此擴散是被熱力驅動以減少表面自由能並且由於通常具有高的相互擴散和/或自擴散的金屬而被強化。這些高擴散係數是通常大部份由擴散期間未被金屬離子的運動所擾亂的活動自由電子氣體所決定的內聚能的結果。因此，在非金屬區域中的晶圓到晶圓的化學接合在兩個不同晶圓上的金屬墊之間產生電性連接的效果。影響此效果的幾何和機械限制因素是在下面被加以描述。
具有寬度W的在接合墊周圍的未接合面積將被產生，在其中兩個晶圓的非金屬表面是被防止接觸(見圖1D)。只要金屬膜的厚度不是太大，則兩個接合晶圓或晶粒之間的間隙可以被減少，而在每一個金屬墊周圍留下小的未接合面積。這是在圖2A至圖2C中說明，其中具有金屬墊21的晶圓20已準備好要被接合至具有墊23的晶圓22。橫向間隙24是 在相鄰的墊之間。金屬墊是被接觸(圖2B)，並且晶圓彈性變形以在間隙24中接合以形成接合25(圖2D)。注意到，圖2A至圖2C中的尺寸並不是按比例繪製的。
下面將示出計算以金屬膜厚度、晶圓或晶粒的機械性質、晶圓或晶粒厚度、接合能為函數的未接合面積的寬度的公式。圖2D是示出未接合面積的間隙高度2h和寬度W之間的關係的曲線圖。當晶圓的變形遵守楊氏模數E所給予的彈性常數並且晶圓各具有厚度tw時，根據薄板的小偏向的簡易理論，可藉由W>2tw的下列等式粗略地估計未接合面積的寬度W，其中成為一對的金屬接合墊在晶圓表面上面具有2h的高度： 其中E'由E/(1-ν2)提供，ν為泊松比(Poisson's ratio)。
已經建議，隨著h減少，其情況將大幅改變。舉例而言，請參考U.Goesele和Q.-Y.Tong的Proc.The 2nd Intl.Symposium on semiconductor wafer bonding,the Electrochemical Soc.Proc.Vol.93-29,p.71(1993)。如果等式(1)計算出的W導致數值低於Wcrit=2tw，且其對應於h<hcrit而且hcrit=5(tw γ/E')1/2，則預定會發生彈性機械不穩定性，導致具有與晶圓厚度tw無關的遠為較小的W的未接合面積，且其由下式求出： 其中k為1左右的無因次常數。實驗上，如圖2D中所示，如果h<300Å，則W遠小於等式(1)所預測者。本申請案的發明人的其他作品已經顯示，如果金屬接合墊對之間的間隔2R小於2W，則晶圓對可能未彼此接合。然而，當2R>2W時，金屬柱周圍的兩個未接合面積之間的表面將接合，並且金屬 柱將被接合且電性連接。
可以下式表示周遭面積的接合所產生而位於金屬接合對上的壓力P：P=(16E't w 3 h)/(3W 4) (3)
合併公式(3)與公式(1)或(2)，當W>2tw時，會獲得下式：P=8γ/3h (4)且當W<2tw時，會獲得下式：P=(16E'tw3)/(3k4h3) (5)
對於金屬墊具有500Å的高度h且接合能是300mJ/m2之經接合的矽晶圓，金屬接合墊上的壓縮性壓力約1.6x108dynes/cm2，亦即160大氣壓。因為此壓力對於金屬接合是夠高，所以不需要在接合期間施加任何外部壓力。當金屬高度h為300Å或更小時，可滿足W<2tw，且如果假設k=1，金屬對上的壓力是5000大氣壓左右。
在一範例中，具有小於300Å的厚度及1mm的分開距離的5mm直徑的Au接合墊是被沉積在氧化物塗覆的100mm矽晶圓上。因為Au接合墊形成於氧化物的表面上，所以其亦在氧化物的表面上方具有300Å的高度。然而，因為金屬可部份地埋設在氧化物或其他絕緣體中且h為金屬延伸於晶粒表面上面的高度，所以h可遠小於實際金屬厚度。已經發展出一種可相容且同時地清潔及活化金屬及氧化物表面的室溫接合技術。Au柱在儲存於空氣中一段取決於金屬厚度和接合能而定的時間長度(例如，60小時)之後是在不需要外部壓力的環境中以晶圓級的室溫接合來形成金屬接合。藉由將楔件插入經接合的介面之間使晶圓對被強迫分離時，Au或 Au/氧化物層自矽基板剝離，代表所形成之金屬至金屬的接合比氧化物表面上的Au墊或矽表面上的氧化物的黏附更強。如上面所述，由於降低表面自由能的配對介面上的金屬原子的相互擴散或自擴散的關係，一強力的金屬性的墊可在室溫下形成於親密接觸的金屬墊之間。金屬原子之間的相互擴散或自擴散係數隨著溫度呈指數性增加，藉以縮短儲存時間以達成完全的金屬性接合，可在室溫接合之後進行退火。Au柱之間的金屬性接合的較佳退火時間隨著溫度增高而縮短。對於此情況，100℃偏好採用5小時，150℃為1小時，250℃為5分鐘。由於非金屬的周遭面積的接合所產生的較高壓力的關係，較薄的金屬在接合時需要比較厚的金屬更低的溫度。隨著Au厚度(亦即，高度)增加，在室溫及升高溫度下形成金屬性接合的時間將變得較長。舉例而言，當Au墊的厚度h為600Å時，250℃需要5分鐘來形成金屬性接合，而在相同溫度下h=500Å則需要15分鐘。
在目前最新技術水平的積體電路的覆晶接合中，焊料球的間距約為1000μm。因此，經接合的金屬柱周圍的接近1000μm或更小的未接合面積寬度對於實際應用來說是夠小。可藉由此方法獲得比此量顯著更小的未接合面積寬度。舉例而言，實驗結果顯示，當h=200Å時，W為20μm，且當h=300Å時，W為30μm。因為h為在晶粒表面上面延伸的金屬高度，由於金屬可部份地埋設在氧化物或其他絕緣體中，所以h可遠小於實際金屬厚度，可容易地達成小於200Å的h。在此例中，金屬墊周圍的未接合環寬度可接近為零。上面所描述的金屬墊可由諸如但不限於濺鍍、蒸鍍、雷射燒蝕、化學氣相沉積以及該領域中習知此技術者所瞭解的其他技術等製程形成，其中將厚度控制在<100Å的範圍中是典型的。
圖3A至圖3C是根據第二實施例的製程的示意圖，兩個不同的經加工晶粒是藉此被接合。晶粒是被示出以具有平坦的但非均勻的層厚度，以展示出除了均勻且平坦的層厚度之外，所揭示的實施例亦可被使用在其他實例中。在該製程中(如圖3A中所示的)，一個別晶粒30(為了方便解釋，其僅示出晶粒30的氧化物層)具有金屬墊31。晶粒可以是包括半導體裝置的矽晶圓，並且電路具有SiO2的相對表面。表面32在CMP操作之後產生。
如在圖3B中所示的，通孔36已被形成且填充有金屬以與金屬墊31連接，金屬互連33被形成在晶圓30上以與在通孔36中的金屬連接，並且由SiO2組成而厚度t2的層34或其他絕緣材料是被形成在晶圓30上。寬度為W2的SiO2層的部分35已被移除以暴露金屬墊35。層34的表面是如同在美國專利第6,984,571、6,902,987和6,500,694號中所描述的而被處理，包括研磨或拋光和極微蝕刻。
在圖3C中，第二晶圓37具有如所示形成的墊38、填充有金屬的通孔39和互連40。互連40具有寬度w1和高度t1。晶圓37的表面41已如表面32被處理，如同上面所討論的。分開的晶粒30和37彼此對準並接觸，以產生圖3D中所示的接合結構。藉由下列關係式：t 1=t 2+δ 1且w 1=w 2+δ 2其中t1及δ1較佳的是所使用的沉積技術可能具有的最小厚度，而δ2應該是對應於2h=t1的情況之2W。相較於待接合的兩個晶粒上之h=t1，未接合面積寬度W顯著地降低。因此，在晶圓30和37上的墊之間產生互連。如果兩個晶粒上的t1小於臨界厚度hcrit，則不需要層34。
在室溫下兩個晶圓的初始接觸期間，金屬墊被對準，並且當間隙由於接合晶圓的表面形貌而足夠小且接合能γ是足夠高時，晶圓表面藉由彈性變形而彼此一致。直接接合發生於形成鄰接晶粒上的裝置或電路之間的金屬互連的經接觸材料之間及晶圓表面之間。在室溫下，接合開始形成於接觸上且接合強度增加以形成金屬性接合。
如同第一實施例，包括金屬墊33和40的晶圓表面32和41產生接觸，相對晶圓表面32和41的接觸的非金屬(例如，半導體或絕緣體)部分開始在接觸點處形成接合，且接合力隨著接觸接合面積增加而增加。在沒有突出的金屬墊33和40存在的情況下，晶圓將橫跨整個晶圓表面接合。突出的金屬墊30和40的存在(雖然阻礙了相對晶圓之間的接合面)並未阻止晶圓到晶圓接合。取而代之，非金屬區域中晶圓至晶圓的接觸所產生的壓力轉換成可藉以使金屬墊33和40接觸的力，甚至不需要任何外部壓力。
可在高或超高(UHV)真空條件之外的環境條件下進行本發明的方法。因此，該方法是一種低成本、量產的製造技術。因為直接金屬性接合只取決於分子間的吸引力，所以要被接合的金屬膜的尺寸是可變的且可縮放成極小的幾何形狀。
為了使半導體裝置有更好的熱管理及功率能力，直接金屬接合是較佳的。直接金屬接合可以用可縮放之遠為更小的接合墊來取代覆晶接合。進一步可能的是，可使用此金屬接合來實現新型的金屬基底裝置(半導體-金屬-半導體裝置)。舉例而言，請參考T.Shimatsu、R.H.Mollema、D.Monsma、E.G.Keim及J.C.Lodder的IEEE Tran.Magnet.33,3495(1997)。
再者，此製程可與VLSI技術相容。可在晶圓受到完全處理時執行直接金屬至金屬接合。因為幾乎所有金屬皆具有比諸如上述的那些半導體或絕緣體(例如矽或矽氧化物)還要顯著地更高的熱膨脹係數，所以直接金屬至金屬的接合亦可利用相對低溫或室溫的接合來最小化熱膨脹差異的影響。
在此處所描述的方法可局部地或橫越整個晶圓表面面積接合。該方法(但是不限於以下範例)接合了異質性表面，使得金屬/金屬、氧化物/氧化物、半導體/半導體、半導體/氧化物和/或金屬/氧化物區域可在室溫下接合於兩個晶圓之間。
本發明提供許多優點。舉例而言，晶圓接合和將組成的電性接觸電性互連的其他方法需要在晶圓接合之後薄化接合基板、通孔蝕刻及金屬沉積。在此處所描述的方法甚至在不需要此些後接合製程步驟的情況下允許電性互連，而免除了晶粒薄化所造成的機械性損傷。再者，深的通孔蝕刻的免除避免了階梯覆蓋(step coverage)的問題並且可使電性連接縮放至較小尺寸，導致較小覆蓋區的電性互連及在接合晶圓之間有減少的電性寄生。該方法是與其他標準半導體製程相容，且與VLSI相容。
因此，在此處所描述的方法是與3-D SOC(三維系統單晶片)製造相容。在接合晶粒之間使用插塞的金屬墊或互連的此種垂直金屬接合可顯著地簡化SOC製造製程並改善SOC速度-功率效能。在此處所描述的直接金屬至金屬接合是可縮放的，且可被施加至多晶粒堆疊的SOC。
除了產生足夠以形成金屬至金屬連接的力之外，該方法藉由金屬接合的金屬墊的無氧化物或接近無氧化物的表面而將有利於低電阻的 金屬接合。舉例而言，可由紫外光/臭氧和氮電漿來清理Au表面，而在表面上未留下氧化物。
在另一實施例中，接合金屬墊的表面(舉例而言由諸如Al或Cu的金屬所製成)是塗覆有抗氧化金屬，舉例而言諸如金(Au)或鉑(Pt)層。由於Au和Pt兩者皆為惰性金屬，將不會有氧化物形成在表面上。為了確保在Au和Pt與主要金屬之間有最小量的氧化物，濺鍍清理和蒸鍍沉積是被採用，較佳的是緊接在接合製程之前。
在第一實施例的修改例中，薄的金屬塗覆層可形成於金屬墊上且如上面所述地接合。舉例而言，Al墊上的一層薄到50Å的Au層在室溫下產生成功的金屬墊接合。因此，可使用諸如Au的金屬作為接合層，藉由前述方法使得幾乎所有金屬皆可被用於在室溫下直接接合。當絕緣體層被設置在經完全處理的晶圓上且接觸開口被形成於金屬墊上然後進行超過接觸窗口的深度100Å的厚度的金屬沉積時，金屬墊此時在氧化物層上面只延伸100Å，墊可彼此分離一段極小距離，譬如20μm。
除了Au或Pt之外，因為鈀(Pd)有良好的抗氧化性，所以已經在此處所描述的直接接合中使用Pd作為塗覆層。Pd在Pd上具有很高的表面擴散性，導致即使在室溫下仍有顯著的Pd質量流動，特別是如果藉由非金屬晶圓表面區域的接合而施加在金屬接合墊上的接觸的壓力亦然。兩個Pd接合層之間的自然氧化物(如果存在)將被機械式分散，而使得兩個接觸金屬接合墊之間的實體介面完全地覆蓋有Pd。
在第一實施例的另一修改例中，UV/臭氧清理使金屬接合墊的表面在UV光下暴露於高臭氧濃度，以移除碳氫化合物污染物。金屬接合 墊的表面上的殘留碳氫化合物劣化金屬接合，並且成為接合介面之間氣泡成形的成核位置(nucleation site)，導致接觸表面之間的滲氣。
實驗已經顯示UV/臭氧處理可防止介面氣泡成形。矽晶圓的HF浸漬將導致大部份由H終止的疏水性表面。疏水性矽晶圓以4.77g/m3的臭氧濃度結合來自兩個235W的UV燈的1850Å及2450Å UV照射在室溫下處理15分鐘，然後進行第二HF浸漬及接合。經接合的HF浸漬疏水性矽晶圓對在從300℃到700℃以各種溫度及15小時退火時不會產生介面氣泡，表示自晶圓表面有效地移除碳氫化合物。
對於Au及Pt而言，合適的是在接合之前使用UV/臭氧清理而在金屬表面上不形成金屬氧化物。對於可由臭氧氧化的其他金屬而言，金屬上具有Au的薄層可防止氧化，或者可舉例而言藉由在接合之前浸入NH4Oh中來移除氧化物。此外，利用惰性和/或含氮氣體的電漿處理(舉例而言，電漿腔室中利用諸如氮和氬的氣體的反應性離子蝕刻模式(RIE)的電漿處理)可清理金屬表面並且在室溫下增強接合能以用於金屬/金屬及氧化物/氧化物接合。再者，氧電漿可使被用以從諸如Au和Pt的金屬表面移除污染物。
雖然已經描述許多種表面製備處理和金屬/金屬及氧化物/氧化物及半導體/半導體的範例，但是仍可使用其他種表面和製備程序，其中在接觸之前充分地清理對應的金屬、絕緣體和半導體表面以免抑制室溫接合的形成。在Au保護或Au接合的情況下，製程是金屬和矽氧化物相容的。在氧化物表面的CMP和表面平坦化及平滑化之後，金屬接合墊如上面所描述而形成於接合晶圓上，經修改的RCA 1(H2O：H2O2：NH4OH=5：1：0.25)、 UV/臭氧區和電漿處理清理了金屬和氧化物兩者的表面而不會使接合表面粗糙。室溫標準29% NH4Oh的浸漬移除金屬表面上的粒子及氧化物(如果存在)，而不劣化矽氧化物表面。在旋轉乾燥且室溫接合及儲存之後，強的共價結合和金屬接合自發性地分別形成於氧化物層之間與金屬表面之間的接合介面。除了圖1A至圖1D中所示接近平坦性的接合結構之外，其他結構亦可使用在此處所描述的原理。舉例而言，圖4A至圖4C圖中示出第二實施例，其中包括金屬通孔互連的晶圓是被接合至較小的晶粒。圖4A描繪包括金屬互連51的基板50的放大圖。在圖4A中，金屬互連被嵌入矽氧化物層52中，諸如PECVD氧化物、熱氧化物或旋塗玻璃。互連51延伸在層52上面而到先前所述的高度。圖4A亦示出具有金屬接點54和矽氧化物層55的較小的晶粒53。
在將絕緣層58形成於具有諸如矽氧化物的材料的兩個晶粒上之後，標準通孔蝕刻及金屬充填、然後化學機械式拋光及表面處理被使用以製備用於接合的層58。圖4B描繪具有相對應的金屬接合墊56和57的一對相對晶圓。圖4C示出這些兩個相對基板的接觸和後續接合，而形成接合59。
在此處，如前面所述，非金屬區域的接合產生形成橫越晶粒的金屬至金屬互連所需要的力。如圖4C中所描繪，氧化物層的接合產生了金屬接合墊56和57的直接金屬至金屬接觸所需要的接合力。多個晶粒53可被製備且接合至晶粒60，如圖4D中所示。
在第一和第二實施例的金屬至金屬直接接合中，在晶粒表面上面延伸的接合金屬膜的厚度較佳的是薄的，以最小化金屬柱周圍的未接 合環形面積。再者，接合金屬墊的厚度可以縮放，且可製作及接合具有VLSI相容尺寸的金屬柱或墊。當金屬膜厚度低於特定數值時，未接合環形面積的寬度是顯著地降低，以使得在金屬柱之間的間隔可允許在金屬接合墊之間使用小的間隔(例如，<10μm)。
第三實施例可使在非金屬表面上面的金屬高度顯著地增加及/或在金屬附近的非接合面積顯著地降低，同時在分開的晶圓上所形成的金屬部分之間維持一可接受的電性連接。在此實施例中，形成電性接觸的金屬材料附近的材料變形被設計成起因於來自非金屬部分的晶圓至晶圓的化學接合的金屬表面處的壓力。此變形可導致在接合製程完成之後施加至金屬的壓力較小，但仍有適當的壓力以在金屬部分之間形成可接受的電性連接。此變形使得在金屬表面附近的間隙可顯著地降低或消除。
可變形材料在形成電性接觸的金屬材料附近的目的是可讓非金屬表面的化學接合所產生的壓力足夠以使金屬材料充分地凹入其各別表面中，以使得在金屬表面附近的間隙可以被顯著地減少或消除。一般而言，可變形材料包含非金屬部分，因為晶圓至晶圓的化學接合所產生的壓力通常是約為使典型金屬變形所需要的壓力的10000分之一或1%的1%。金屬至其各自表面中的凹陷可使得在非金屬表面上面的金屬表面的起始高度實質上高於在凹陷之後的起始高度。這顯著地增加了製備用於接合的晶圓所需要的金屬表面的容限且隨後增加了實施例的可製造性。變形亦顯著地減少或消除了金屬周圍的非接合區域，而顯著地增加可在給定區域中製作的連接數量且提高了經接合和互連的部件的接合強度。
變形可藉由將非金屬區包括在金屬表面底下來促進，如圖 5A中所解釋。具有基板55的晶粒包括被形成於層51上的金屬墊50，金屬墊50將要被接合至另一裝置上的對應層。藉由標準光微影、蝕刻以及沉積技術，區域53(其填充有諸如低K介電材料的可變形非金屬材料)形成於層52中。層53和區域53形成於層54上。可將任何數目的層形成於基板54上。再者，區域53可大幅加大或者層52可以由低K材料所形成，如圖5B中所示。
區域53亦可為包含真空或諸如空氣的壓縮性氣體的空隙，或者其可以是具有夠低壓縮性可藉由接合所產生的壓力讓金屬變形至區域中的可壓縮非氣態固體材料。可用與在化合物半導體積體電路製造中常見的金屬性空氣橋接類似的方式來形成空隙。此製造的其中一範例如下：1)在平坦、非金屬表面中蝕刻出凹陷，2)以如同光阻的可移除材料來充填凹陷，以使得可移除材料位於凹陷中但不位於凹陷外。這可以舉例而言藉由習知的光阻旋塗來進行，導致凹陷中有比凹陷之外更厚的光阻，接著進行足夠量的光阻的毯覆(未圖案化)蝕刻以移除凹陷之外的材料但不足夠以移除凹陷中的材料，3)圖案化出橫過凹陷但未完全覆蓋凹陷的金屬特徵，而留下凹陷的暴露部分，及4)藉由進接凹陷的暴露部分來移除凹陷中的移除材料。可壓縮性非氣態固體材料的範例是半導體製造中所使用的低K介電質。此區域的深度通常可接近或大於非金屬表面上面的金屬的所需要高度。圖5A的晶粒所要接合的另一晶粒亦可具有一區域，如同在被接合至墊50的金屬墊底下的對應位置上的區域53。這是在圖5C中被解釋，注意到圖5C僅是示意圖而未按比例繪製。在此處，墊50和56是由層51和57的接合所產生的壓縮力所接合。圖5C中的上方晶粒包括基板61，其具有形成 於空隙上方的墊56或層58中的低K材料區域59。層58形成於層59上。 並且，上方晶粒可具有許多層。
此實施例中，當晶圓接合時，金屬表面產生接觸且在化學接合製程期間相對於彼此發生變形。變形減緩了一些接合製程所施加的壓力，但仍有足夠的壓力以使金屬表面維持接觸且在兩個分開的晶圓上的兩金屬表面之間維持一可接受的最小接觸阻力。隨著金屬變形至金屬底下的區域中，接合表面得以在很靠近或緊鄰金屬的橫向環帶中接觸，導致非金屬表面之間有最大的接合面積。因此，可由所揭示的實施例形成與金屬接觸相鄰的1至10微米或更小的最小化學非接合區域。
可變形區域被設計成為具有最小寬度，以最大化可能的電性互連數量。可變形區域的寬度主要取決於金屬厚度及非金屬表面上面的金屬高度。這些參數大致由下列關係式決定。
應力=(2/3)×(金屬的楊氏模數)(1/1-金屬的泊松比)×(表面上方的金屬高度/區域的一半寬度)2及壓力=應力×4×金屬厚度×表面上方的金屬高度/(區域的一半寬度)2其中壓力是接合製程所產生。這些關係式可參考在Maissel and Glang,1983 Reissue,pp.12-24的“Handbook of Thin Film Technology”。
舉例而言，對於約0.1微米的金屬厚度、表面上的區域上面約0.1微米的金屬高度以及約1微米的區域寬度而言，接合期間所產生的壓力是大致上足夠以使金屬變形至區域中(假設可忽略區域的可壓縮性)。注意到，如果金屬不可變形，則此0.1微米的金屬高度將導致金屬周圍約1mm 的未接合環帶或環寬度。由於非金屬表面上面的金屬高度需要較少控制，因此實質上增加了可製造性。再者，非接合面積是實質上減少，而允許顯著地增加可製作的金屬至金屬接觸數量且導致化學接合能的增加。如果無法忽略掉區域的可壓縮性，則應依此降低金屬的厚度和/或應依此降低非金屬表面上面的金屬高度和/或應依此增加區域的寬度。注意到，所應增加的區域的寬度的百分比數值是小於所應減少的非金屬表面上面的金屬高度或金屬厚度的百分比數值。
第四實施例藉由仰賴低溫後接合迴焊退火以在經化學接合的晶圓之間形成可靠的電性互連，進一步鬆綁在第一、第二及第三實施例中所描述的金屬接觸附近的機械性設計拘限。參照圖6A至圖6C和圖7A至圖7C來提供此實施例的描述。
圖6A示出具有平坦表面的基板60和61。凹陷62和63分別形成於基板60和61中，並且金屬墊64和65分別形成於凹陷62和63中。平坦表面適於化學接合，如前面所描述。構成墊64和65的金屬或金屬的組合可以在低溫下迴焊。此金屬的範例是在160度C的融化溫度下迴焊的銦，並且此金屬的組合是在220度C的共晶融化溫度下迴焊的96.5%的錫及3.5%的銀。
在製備了圖6A中的表面以供直接化學接合並且將表面放置在一起之後，化學接合形成於平坦性表面之間。相較於實施例1及2，在金屬接觸鄰近處因為接觸凹陷而不具有間隙，但尚未作出可靠的電性互連。
在已經形成了圖6B中的化學接合之後，空隙66是藉由從兩個晶圓部份填充有金屬的凹陷來形成。此空隙不會阻礙晶圓表面的合併 以及形成與第一和第二實施例中的金屬接觸相似的化學接合。因此實現了最大化接合能的最大接合面積。在已經形成此高接合能化學接合之後，一低溫迴焊退火使凹陷中的金屬迴焊，導致來自相對晶圓的金屬一起產生濕潤並導致互連金屬結構具有高可靠度。部分67是藉由迴焊來形成，以連接墊64及65。此迴焊是藉由具有高尺寸比的凹陷的毛細作用及(舉例而言)如同晶圓在退火期間轉動的重力的組合來輔助。
在第五實施例中，類似於第四實施例，圖6A中的一個表面的金屬凹陷以金屬平台取代，以使得一晶圓上的平坦性表面上面的金屬平台的高度小於其他晶圓上的平坦性表面下面的金屬凹陷的深度，如第7A圖所示。基板70和71具有各別的金屬墊72和73。墊72形成於凹陷74中。在這種情況下，如第7B圖所示，在構成化學接合的平坦性表面放置成為產生接觸之後，金屬表面一般不會接觸。基板70和71的表面被製備以供直接化學接合且表面如同上述範例被放置在一起，並且在平坦性表面之間形成化學接合(圖7B)。在迴焊之後，以類似於第6C圖的方式將兩個不同晶圓上的金屬濕潤在一起，形成部分75，而產生第7C圖。
因此，在此處所描述的實施例提供許多優點且不同於先前的低溫晶圓接合技術。金屬至金屬的直接接合是自發性的且在室溫下不需要外力。在金屬柱上用於金屬至金屬接合所需要施加的壓力是藉由接合製程本身而非外力來產生。上面所描述的金屬至金屬的直接接合可在環境條件下進行並且實現下列作用：晶圓級或晶粒尺寸的接合，在室溫下形成的強力的金屬性Au-Au、Cu-Cu或金屬至金屬接合，以及可藉由~50Å的Au層覆蓋金屬在室溫下形成除了Au與Cu之外的金屬的強力金屬接合。因此， 可同時達成金屬/金屬、氧化物/氧化物以及金屬/氧化物的接合。金屬至金屬直接接合與標準VLSI加工相容，所以是一種具有可製造性的技術。金屬至金屬直接接合是與覆蓋有矽氧化物、矽或氮化矽的材料的接合相容。在各種實施例中，金屬至金屬的直接接合是與覆蓋有以下至少一種的材料之接合相容：玻璃、矽上絕緣體、氮化矽、碳化矽、藍寶石、鍺、砷化鎵、氮化鎵、聚合物、磷化銦或者任何其他合適的材料。
緊鄰金屬接合墊的非金屬區域的直接接合是有助於金屬至金屬直接接合。如先前所述，在這些區域中是直接接合在相對的金屬接合墊上產生合力。非金屬性區域的直接接合在空中(in air)共價結合了覆蓋有矽氧化物或其他絕緣體的晶圓，例如覆蓋有以下至少一者的晶圓：玻璃、矽上絕緣體、氮化矽、碳化矽、藍寶石、鍺、砷化鎵、氮化鎵、聚合物、磷化銦或者任何其他合適的材料。可使用其他材料，舉例而言，亦可在接合之前浸漬至氨溶液中的氟化的氧化物表面層。更一般而言，具有可由OH、NH或FH基團所終止的開放結構表面的任何材料以及多孔的低k材料在室溫下接觸時可形成共價結合。
可在純粹或摻雜狀態中使用諸如沉積、熱或化學氧化的任何方法所形成的矽氧化物及旋塗玻璃。
本發明的應用包括但不限於垂直整合用於3-D SOC、微墊封裝、低成本及高效能的覆晶接合置換、晶圓尺度封裝、熱管理及獨特的裝置結構(諸如金屬基底裝置)的經加工的積體電路。
圖8A是在第一半導體元件101a和第二半導體元件101b被組裝在一起之前的兩個元件101a和101b的示意性側邊截面圖。半導體元件 101a和101b可包括對應的非金屬性接合區域106a和106b以及具有接觸特徵103a和103b的傳導性接觸結構102。如圖8A中所示，接觸特徵103a和103b可被設置在接合表面106a和106b下面，以使得對應的凹陷115a和115b是被形成在半導體元件101a和101b中。接觸特徵103a和103b可以任何合適的方式被形成在凹陷115a和115b中。舉例而言，在一些實施例中，凹入的接觸特徵103a和103b可利用鑲嵌製程形成。在此些鑲嵌製程中，一或多個溝槽可(例如，藉由蝕刻)被形成在半導體元件101中，並且傳導材料可被提供於溝槽中。在場區(field region)上方的傳導材料可被拋光或是以其他方式移除，以形成圖8A中的凹入的接觸特徵103a和103b。
接觸特徵103a和103b可包括適用於下面所描述的圖9A至圖9B的實施例的任何材料。接合區域106a和106b以及接觸特徵103a和103b可包括適用於下面所描述的圖9A至圖9B的實施例的任何材料。如下面所解釋的，接合區域106a和106b可被製備以用於直接接合。舉例而言，如同關於圖9A至圖9B的實施例所解釋的，接合區域106a和106b可被拋光、被極細微地蝕刻和/或以想要的成分(諸如，氮)來終止。此外，如圖8A中所示，互連105(例如TSV)可將接觸特徵103b連接至半導體元件101b的外部，以提供到較大的電性系統的電性通信。再者，儘管未示出，但是在互連105和接觸特徵103a之間可能存在有額外的內部金屬化層。金屬化和/或互連105可在將兩個元件101a和101b接合在一起之前或之後形成。額外的細節可至少在美國專利第7,485,968號中被找到，在此處由於所有目的以引用的方式將其完整併入。
圖8B是在接合區域106a和106b被直接接合在一起之後的 中間接合結構100’的示意性側邊截面圖。當接合區域106a和106b被組裝為接觸時，接合區域106a和106b可被直接接合在一起，以形成化學接合(例如，共價結合)而不具有中間的黏著劑。如同上面所解釋的，直接接合可以在室溫下和/或在不施加外部壓力的情況下被進行。在接合區域106a和106b被直接接合在一起之後，在對應的接觸特徵103a和103b之間仍可能留有初始間隙120。應該理解的是，此間隙120亦可以在使接合區域106a和106b接觸之後被實現，即使是如同在圖7B中所示而在一側上的接觸突出亦然。
圖8C是在接觸特徵103a和103b被直接接合在一起之後的接合結構100的示意性側邊截面圖。在各種實施例中，舉例而言，半導體元件101a和101b可在直接接合非傳導性接合區域106a和106b之後被加熱。在各種實施例中，半導體元件101a和101可以在75℃至350℃的範圍中被加熱，或更具體地在100℃至250℃的範圍中被加熱。加熱半導體元件101a和101b可增加接觸特徵103a和103b的內部壓力並且可使它們擴張以填充間隙120。因此，在接觸特徵103a和103b被直接接合在一起之後，接點125可實質上填充在兩個半導體元件101a和101b之間的空隙。
如在圖8C中所示的，第一接合區域106a可沿著介面130被直接接合至第二接合區域106b。在第一接合區域106a和第二接合區域106b之間的介面130實質上延伸至第一接觸特徵103a和第二接觸特徵103b，亦即延伸至被直接接合的接點125。因此，如在圖8C中所示的，在接觸特徵103a和103b被接合在一起之後，在接觸特徵103a和103b之間以及在相鄰的接合區域106a和106b之間可能沒有間隙。不同於圖1A至圖5C的實施 例，元件可不顯示出圍繞接點125的塑性變形。
半導體元件101a和101b的接合區域106a和106b下面的距離可以小於20nm，並且較佳的是小於10nm。接合接著溫度升高可如同上面所述而增加接觸特徵103a和103b之間的內部壓力，並且可改善金屬接合、金屬接觸、金屬互連或接觸結構102之間的傳導性。在各自的接合區域106a和106b下面的接觸特徵103a和103b的微小距離可以是橫跨接觸結構102的範圍的平均距離。接觸結構102的形貌亦可包括相等、大於和小於平均距離的位置。接觸結構102的總高度變化(由最大高度和最小高度之間的差來給定)可以實質上大於均方根(RMS)變化。舉例而言，具有1nm的RMS的接觸結構可具有10nm的總高度變化。
因此，雖然接觸特徵103a和103b可稍微地在接合區域106a和106b下面，部分的接觸特徵103a和103b可延伸在接合區域106a和106b上面，而導致在接合非金屬的接合區域106a至非金屬的接合區域106b之後在接觸特徵103a和103b之間有機械連接。由於不完全的機械連接或是在接觸特徵103a和103b上的自然氧化物或其他汙染物的緣故，該機械連接可能不會導致在接觸特徵103a和103b之間的充分電性連接。隨後的溫度升高可改善金屬接合、金屬接觸、金屬互連和/或接觸結構103a和103b之間的傳導性。
替代而言，如果接觸特徵103a和103b的最高部分是在接合區域106a和106b下面並且在接合之後接觸特徵103a和103b之間沒有機械接觸，則溫度升高可導致接觸特徵103a和103b之間的機械連接和/或想要的電性互連。
替代而言，接觸特徵103a可以是在接合區域106a的表面下面並且接觸特徵103b可以是在接合區域106b上面，或者接觸特徵103a可以是在接合區域106a的表面上面並且接觸特徵103b可以是在接合區域106b下面。接觸特徵103a和103b在接合區域106a和106b下面的距離差異(或者反之亦然)可以是微小地正值。可替代地，接觸特徵103a和103b在接合區域106a和106b下面的距離差異可以是標稱地為零或略為負值，並且後接接溫度的增加可如上面所述地改善金屬接合、金屬接觸、金屬互連、接觸特徵103a和103b之間的傳導性。
接觸特徵103a和103b相對於元件101a和101b的接合區域106a和106b的高度或深度可以利用形成元件101a和101b的表面的拋光製程來控制，舉例而言利用化學機械式拋光(CMP)。CMP製程通常可具有多個製程變數，其包括但不限於拋光漿料的類型、漿料添加的速度、拋光墊、拋光墊旋轉速率以及拋光壓力。CMP製程可進一步取決於構成半導體元件101a和101b的特定非金屬和金屬、非金屬和金屬材料的相對拋光速率(較佳是相似的拋光速率，例如鎳和矽氧化物)、大小、接觸特徵103a和103b的間距和顆粒結構以及接合區域106a和106b的非平坦性。亦可使用替代性拋光技術，舉例而言無漿料拋光。
接觸特徵103a和103b相對於接合區域106a和106b的高度或深度亦可以由在半導體元件101a和101b的表面上的接觸特徵103a和103b周圍的材料的輕微乾蝕刻而控制，舉例而言，使用利用CF4和O2的混合物的電漿或反應性離子蝕刻，以用於包括特定材料的表面，例如矽氧化物、氮化矽或氮氧化矽，較佳的是使得表面粗糙度增加而將顯著降低該等表面 之間的接合能。替代而言，接觸特徵103a和103b的高度可藉由在接觸特徵103a和103b上形成非常薄的金屬層來控制。舉例而言，無電解電鍍一些金屬(例如金)可自限(self-limiting)出一非常薄的層，舉例而言約5到50nm。此方法可具有以非常薄的非氧化性金屬(舉例而言，鎳上的金)來終止氧化金屬的額外優點，以有助於形成電性連接。
因此，在接合順序內對於諸如圖1A至圖5C的實施例而言，相對基板的接觸結構之間的接觸可以發生在相對基板的接合區域之間的接觸之前或同時發生。對於諸如圖6A至圖8C的實施例而言，相對基板的接觸結構之間的接觸可以發生在相對基板的接合區域之間的接觸之後。
長形接觸特徵的範例
在一些配置中，可能會有挑戰性的是將一半導體元件的接觸墊與另一半導體元件的對應接觸墊對準。一些接觸墊(諸如圖1A至圖1D的金屬性的墊12和15)可具有相對小或小型的尺寸和形狀，其對傳統拾放工具要對準相應的接觸墊而言可能是困難的。舉例而言，許多拾放工具的對準能力是在2微米至10微米的範圍中，或在5微米至10微米的範圍中。具有在這些範圍之外或附近的主要尺寸的接觸墊可能難以使用傳統拾放工具來對準，並且可能需要更昴貴的對準設備和/或程序。
在一些配置中，可以提升接觸墊的總體尺寸以改善來自兩個經接合的半導體元件的相應的墊的對準。然而，提升接觸墊的尺寸可能會佔用在半導體元件上有價值的佔用配置(real estate)。再者，提升接觸墊的尺寸亦可能會增加寄生電容，從而增加功率消耗和/或減少半導體元件的頻寬。此外，較大的接觸墊亦可能會增加在各自半導體元件的經拋光表面上 的凹陷效應。所得的大的凹陷效應可能會導致非傳導性接合和/或傳導區域以非均勻的方式來接合。對於在此處所描述的金屬(或傳導性摻雜的半導體)和非金屬區域的直接接合而言，在基板表面之上的接點高度或在基板表面之下的接點深度可能是重要的。
據此，仍然持續的需要在對應的接觸墊之間提供經改善的對準精確度同時在接合期間保持相對地小的特徵尺寸。在此處所揭示的各種實施例中，第一半導體元件可包括傳導性第一接觸結構和相鄰第一接觸結構的非金屬性第一接合區域。第一接觸結構可包括傳導性第一長形接觸特徵。第二半導體元件可包括傳導性第二接觸結構和相鄰第二接觸結構的非金屬性第二接合區域。第二接觸結構可包括傳導性第二接觸特徵。第一接合區域可與第二接合區域接觸並且直接接合。第一長形接觸特徵可被定向以與第二接觸特徵非平行並且在第一長形接觸特徵和第二接觸特徵之間的相交點處與所述第二接觸特徵直接接觸。第二接觸特徵亦可包括長形接觸特徵。
因為接觸特徵中的至少一者是長形的，所以當兩個半導體元件被組裝在一起時可以容許較大的對準偏差。再者，長形接觸特徵的使用可允許使用相對小的特徵尺寸，諸如相對於較大的接觸區域有相對窄的線路。舉例而言，雖然為了有助於對準接觸特徵的長度可能遠大於寬度，但是長形接觸特徵的相對細的寬度也將顯著地減少由於在拋光期間的凹陷所造成的接觸高度或深度變化。再者，窄的特徵寬度將有利於在元件上有相對小的寄生電容和相對小的覆蓋區。
圖9A是根據一實施例的接合半導體結構100的示意性俯視 圖。圖9B是圖9A的接合半導體結構的示意性側邊截面圖。圖9A至圖9B的接合結構100可包括一對接合半導體元件101。為了便於說明，該對接合半導體元件101中僅有一者是示於圖9A。半導體元件101可包括晶圓、經部分處理的晶圓和/或經切割或部分切割的半導體裝置，諸如積體電路晶粒或微機電系統(MEMS)晶粒。每一個半導體元件101可包括傳導性接觸結構102和相鄰接觸結構102的非金屬性接合區域106。如圖9A至圖9B中所示，舉例而言，接合區域106可圍繞或被設置在接觸結構102周圍。傳導性接觸結構102可以包括任何合適的傳導性材料，包括(例如)金屬或傳導性摻雜的半導體材料。舉例而言，接觸結構102可以包括金、銅、鎢、鎳、銀、它們的合金或任何其它合適的材料。非金屬性接合區域106可以包括任何合適的非傳導性材料，包括(例如)半導體材料或絕緣材料(諸如，聚合物)。舉例而言，接合區域106可以包括以下中的至少一者：矽、氧化矽、氮化矽、玻璃、矽上絕緣體、碳化矽、藍寶石、鍺、砷化鎵、氮化鎵、聚合物、磷化銦或者任何其他合適的非金屬性的材料。
接觸結構102包括來自相對的或接合成對的半導體元件102的接觸特徵。第一半導體元件101的接觸結構102可包括第一長形接觸特徵103a，並且第二半導體元件的接觸結構102(未例示於圖9A)可包括第二長形接觸特徵103b。在圖9A至圖9B的實施例中，第一長形接觸特徵103a和第二長形接觸特徵103b可以是長度大於寬度的大致上直線形的元件。舉例而言，接觸特徵103a和103b的長度可以是寬度的至少兩倍、寬度的至少五倍或是寬度的至少十倍。長度是用以指出在接合平面(例如，兩個元件101直接接合所沿著的界面性平面)中每一個特徵的較長的維度，而寬度指出 在接合平面中較窄的維度。此外，應當理解的是，在其他實施例中長形接觸特徵可以不是直線形的。相對地，長形接觸特徵可以是彎曲的(例如)以使得在接合平面中接觸特徵所經過的路徑長度比在接合平面中的接觸特徵的寬度長。
第一半導體元件101的第一長形接觸特徵103a可以被設置在下方互連105(諸如直通矽晶穿孔(TSV))上方並且可以與下方互連105至少部分地對準。內部金屬化結構(未示出)可將互連105與第一半導體元件101的接觸結構102(例如，第一長形接觸結構103a)連接。舉例而言，內部金屬化結構或跡線可以在半導體元件101中被橫向地和/或垂直地設置，以在互連105和接觸結構102之間提供通信。再者，在一些實施例中，傳導性阻障結構(未示出)可以被提供在接觸結構102和互連105或中間的內部金屬化結構之間。舉例而言，在一些實施例中，傳導性阻障結構可以內襯鑲嵌結構的溝槽。額外的金屬化結構亦可以被提供在半導體元件101的表面處或附近，以橫向地繞送訊號跨越該元件的寬度。如圖9A中所示，互連105可以隔開一段互連間距p，並且可用以將接觸結構102電性連接至與較大的電子系統通信的外部引線。間距p可以是任何合適的距離，例如在0.1微米至500微米的範圍中、在0.1微米至100微米的範圍中、在0.1微米至50微米的範圍中、在1微米至50微米的範圍中或在10微米至50微米的範圍中。
為了接合兩個半導體元件，如上所解釋，半導體元件101可以相對於彼此定向，以使得相對的元件101中的一者的第一長形接觸特徵103a與相對的元件101中的另一者的第二長形接觸特徵103b非平行。兩 個半導體元件101可以被接在一起，以使得至少第一和第二非金屬性接合區域106是相接觸的。如同上面所解釋的，接合區域106的表面可被加以製備，以使得當兩個半導體元件101的接合區域106接觸時，非金屬性接合區域106彼此直接接合以形成化學接合而不具有中間的黏著劑。因此，被設置在第一接觸特徵103a的第一側上的非金屬性接合區域106的部分可以與被設置在第二接觸特徵103b的兩側上的非金屬性接合區域106的對應部分直接接合。
舉例而言，在各種實施例中，接合區域106可被拋光並且接著被極細微地蝕刻以產生平滑的接合表面。在各種實施例中，經蝕刻的表面可以用含氮的物質來終止，舉例而言藉由將經蝕刻的表面暴露於含氮的電漿(諸如氮氣)或將經蝕刻的表面浸漬於含氮的溶液中(諸如含氨的溶液)。在其他實施例中，其他鍵結物質(terminating species)可有助於非金屬性接合區域106a和106b的化學共價結合。在各種實施例中，接合區域106可以在室溫下直接接合在一起。接合區域106亦可在不需對半導體元件101施加外部壓力的情況下直接接合在一起。
第一長形接觸特徵103a和第二長形接觸特徵103b可以在接觸的相交點104處彼此相交。如同上面關於圖1A至圖8C所解釋的實施例，長形接觸特徵103a和103b可彼此直接接合，以在特徵103a和103b之間提供電性通信。舉例而言，在與圖1A至圖5C的實施例相似的實施例中，在接點突出的地方接點之間非金屬表面(例如，半導體或絕緣體)的接合產生可將來自相對半導體元件的接觸特徵103a和103b接合的內部壓力，其可利用或可不利用額外的熱。在與圖8A至圖8C的實施例相似的實施例中， 在接合區域106a和106b彼此直接接合之後，半導體元件101可以被加熱以使得長形接觸特徵103a和103b由於相對於外圍材料的熱膨脹係數(CTE)差異的緣故而朝彼此擴張，而產生使特徵103a和103b在相交點104處彼此直接接合的內部壓力。半導體元件101可以在75℃至350℃的範圍中被加熱，或更具體地說，在100℃至250℃的範圍中被加熱。
有利的是，提供至少一個長形接觸特徵103a和/或103b可以顯著地增加將傳導性接觸結構102直接接合在一起的對準容限。因為在接合平面中接觸特徵103a和/或103b中的至少一者由於路徑長度大於其寬度而是長形的，所以兩個半導體元件101可以有相對大的未對準，而仍然有利於在接觸特徵103a和103b之間的直接接合。舉例而言，在使用較小的或非長形的接觸特徵的接合結構中，習知拾放機械的對準容限可以是在1微米至5微米的範圍中，或是在1微米至10微米的範圍中。
相比之下，對於40微米的互連間距p而言，長形接觸特徵103a和103b的長度l可以是約20微米，或是互連間距p的約一半間距。因為每一個接觸特徵103a和103b的長度l相對於互連間距p而言是大的，所以拾放機械是更容易在兩個接觸特徵103a和103b之間實現重疊或相交，而導致較大的對準偏差容限。舉例而言，在40微米的互連間距的範例中，對準偏差容限(亦即，半導體元件101可相對於彼此橫向地未對準的程度)可以是在5微米至10微米的範圍中。
應該理解的是，在其他實施例中，可以使用其他合適的長度l。舉例而言，在圖9A至圖9B中所示的長形接觸特徵103a和103b的長度l可以是在0.05微米至500微米的範圍中、在0.05微米至100微米的範圍中、 在0.05微米至50微米的範圍中、在0.1微米至50微米的範圍中、在1微米至50微米的範圍中、在5微米至50微米的範圍中、在10微米至50微米的範圍中、在10微米至40微米的範圍中或在15微米至30微米的範圍中。接觸特徵103a和103b的寬度W可以是足夠小以減少寄生電容並且在半導體元件101上保持小的覆蓋區。舉例而言，接觸特徵103a的寬度可以是在0.01微米至10微米的範圍中、在0.01微米至5微米的範圍中、在0.1微米至10微米的範圍中、在0.1微米至5微米的範圍中、在0.5微米至5微米的範圍中、在0.5微米至4微米的範圍中、在1微米至5微米的範圍中、在1微米至3.5微米的範圍中或在1.5微米至3微米的範圍中。
雖然在圖9A至圖9B中所示的兩個接觸特徵103a和103b被說明且描述為直線形的接觸特徵，應該理解的是，在其他實施例中長形接觸特徵可反而包括彎曲的形狀。舉例而言，應該理解的是，第一半導體元件可包括彎曲的接觸特徵，並且第二半導體元件可包括直線形接觸特徵、經二維地圖案化的接觸特徵(例如格柵接觸特徵)、彎曲形的接觸特徵中的任一者。因此，對準偏差可被減少而將凹陷最小化(以及隨後接點高度/深度的不均勻性問題)，只要路徑長度(例如，不管是直線形路徑長度或彎曲形路徑長度)是比接觸特徵的寬度足夠地更長。額外的長形接觸特徵是在下面結合圖12A至圖12H來說明。
接觸特徵103a和103b可包括延伸在接合區域106上面的突出接點。舉例而言，接觸特徵103a和103b可包括與圖1A至圖1D的實施例中所示的金屬性的墊12和15類似的突出接點。在其他實施例中，接觸特徵103a和103b可包括凹陷接點，其中接觸特徵103a和103b是最初設置在 接合區域106之下並且在接合區域106直接接合在一起(例如與圖6A至圖6C和圖8A至圖8C中所示的類似)之後接觸。在另外的其他實施例中，接觸特徵103a或103b中的一者可包括突出接點，並且接觸特徵103a或103b中的另一者可包括凹陷接點(例如與圖7A至圖7C中所示的類似)。
圖10是根據另一實施例的接合半導體結構100的示意性俯視圖。除非另外說明，在圖10中所示的參考數字表示與圖9A至圖9B中所引用的構件大致上類似的構件。舉例而言，兩個接合半導體元件101每一者可包括對應的傳導性接觸結構102和相鄰接觸結構102所設置的非金屬性接合區域106。傳導性接觸結構102可包括長形接觸特徵103a和103b。然而，不同於圖9A至圖9B的實施例，在圖10的實施例中，接觸特徵103a和103b可包括經二維地圖案化的接觸特徵，例如界定二維的長形接觸特徵的圖案用以改善接合結構的對準的多個相交的傳導區段。相交的傳導區段可以是彎曲、直線形、多邊形、圓形、橢圓形。舉例而言，在圖10中，對應的正交格柵圖案可被設置在半導體元件101上。相比之下，圖12A至圖12H說明額外的實施例，其中長形接觸特徵103a和103b的圖案可界定有助於改善接合結構的旋轉對準的其他二維形狀。
圖10的接觸特徵103a和103b的格柵圖案可包括多個相交線路。雖然圖10的格柵圖案的相交線路被示為彼此垂直，但是在其他實施例中格柵圖案的相交線路可反而在非垂直的角度下被設置。再者，雖然在圖10中格柵圖案中的多個線路的每一者是直線形的，但是在其他實施例中格柵圖案中的線路可反而是彎曲的。舉例而言，請參考圖12A至圖12H的圖案。
格柵圖案的長度l可具有與圖9A至圖9B的實施例的線路相同的長度l。舉例而言，格柵圖案的長度l可以是在0.05微米至500微米的範圍中、在0.05微米至100微米的範圍中、在0.05微米至50微米的範圍中、在0.1微米至50微米的範圍中、在1微米至50微米的範圍中、在5微米至50微米的範圍中、在10微米至50微米的範圍中、在10微米至40微米的範圍中或在15微米至30微米的範圍中。接觸特徵103a和103b的格柵圖案中的每一個線路的寬度可以是足夠小以避免可能會妨礙橫跨半導體元件101之牢靠的金屬接合的凹陷問題。舉例而言，接觸特徵103a的格柵圖案中的多個線路的寬度可以是在0.01微米至10微米的範圍中、在0.01微米至5微米的範圍中、在0.1微米至10微米的範圍中、在0.1微米至5微米的範圍中、在0.5微米至5微米的範圍中、在0.5微米至4微米的範圍中、在1微米至5微米的範圍中、在1微米至3.5微米的範圍中或在1.5微米至3微米的範圍中。格柵圖案的相鄰線路之間的分開距離d可以是任何合適的距離，例如在0.01微米至100微米的範圍中、在0.01微米至50微米的範圍中、在0.1微米至50微米的範圍中、在0.5微米至50微米的範圍中、在0.5微米至10微米的範圍中、在0.5微米至5微米的範圍中或在1微米至5微米的範圍中。
有利的是，使用格柵圖案作為接觸特徵103a和103b可使相交區域104具有多個電性、直接接合的接點。因為格柵圖案包括多個相交線路，所以圖10的實施例可產生電性接點同時容許大量的對準偏差。再者，如與圖9A至圖9B的實施例對比，在格柵圖案內產生多個電性連接可允許較小的電流密度，其至少是因為有更大的接觸面積。舉例而言，在圖10的 實施例中，接點(例如接觸特徵103a和103b所直接接合的面積)的總表面積可以是在10μm2至30μm2的範圍中、或在5μm2至35μm2的範圍中、或更特別地在10μm2至25μm2的範圍中。每一個接點的電流是分佈於具有較大的總體接觸表面的較大量的連接，從而減少給定電流的電流密度。
在圖10中所示的格柵圖案包括m×n的單元陣列，其中m=n=4。然而應該理解的是，格柵圖案可包括任何數量的單元，並且m和n可以是偶數或奇數。舉例而言，在替代性格柵圖案中，m×n的單元陣列可包括奇數個單元，例如m=n=1,3,5等。在此些實施例中，使用奇數個單元可允許在給定對準偏差下有固定的交錯面積，以提供最小的接觸結構面積(舉例而言，當每一個單元的範圍接近對準精確度時)。格柵圖案的線路可以比格柵線路之間的間隔要窄，以幫助減少凹陷並提高非金屬性部分的接合能。可重複以構成格柵的單元的大小或範圍可以是接近用以對準並將接合表面放置在一起的(多個)對準工具的3 sigma對準精確度，以使得至少兩個連接點的面積是由在m=1時相對接合表面上的線路寬度的乘積所給定。在m=1時可增加連接點的數量。互連面積可以藉由增加連接點的數量或增加在格柵中線路的寬度而增加。
在習知接合配置中，分開的金屬性的層(例如鋁質墊)可在半導體元件的頂部表面附近處產生，以在兩個接合半導體元件101a和101b之間電性通信。再者，金屬性接觸墊可能是相對地大以接納在相對半導體元件上的對應接點或凸塊，其可能會增加寄生電容。在此些習知配置中，垂直連接(諸如通孔或TSV)可從接觸墊延伸至(多個)半導體元件中以與對應跡線連接而用於訊號繞送。因此，在此些配置中接觸墊是相對地大， 並且可能會使用多個跡線層以確保訊號是被適當地繞送。垂直連接佔據本來可用於橫向繞送的層。
圖11A至圖11C說明使用長形接觸特徵103a和103b以提供與對應的下方跡線120的電性通信，以供可靠地繞送電性訊號通過半導體元件101a和101b。特別是，圖11A是具有多個長形接觸特徵103a的第一半導體元件101a的示意性平面圖，多個長形接觸特徵103a與對應的下方跡線連接。圖11B是第一半導體元件101a的示範性接觸特徵103a和相關聯的下方跡線120a的示意性平面圖，亦示出被對準以在交叉指向上與第一半導體元件的接觸特徵接觸的第二半導體元件的接觸特徵。圖11C是兩個接合半導體元件101a和101b的示意性側邊截面圖，兩個接合半導體元件101a和101b在每一個元件101a和101b的交叉的接觸特徵103a和103b之間具有直接連接。
如圖11A中所示，第一半導體元件101a可包括多個接觸結構102，其包括在第一半導體元件101a的頂部表面處暴露的長形接觸特徵103a。如同圖8A至圖10的實施例，非金屬性接合區域106可被設置以相鄰或圍繞接觸特徵103a，並且非金屬性接合區域106可覆蓋跡線120a。每一個接觸特徵103a與被設置在接觸特徵103a之下的對應跡線120a電性連接並較佳的是從對應跡線120a延伸。因此，圖11A中所示的跡線120a可嵌入於半導體元件101a內而在接觸特徵103a之下。跡線120a可以彼此凸出(jog)或偏移以便能夠可靠地繞送每一個接觸特徵103a的跡線而不會有干擾。雖然為了方便說明圖11A將接觸特徵103a示為比下方跡線120a要寬，但是從以下圖11B和圖11C應該理解的是，事實上接觸特徵可具有與下方跡線120a 相同的寬度。舉例而言，在一些配置中，跡線120a的寬度和接觸特徵103a的寬度可以是在0.5微米至5微米的範圍中、在1微米至3微米的範圍中，例如約2微米。
如圖11B至圖11C中所示，範例性接觸特徵103a可被設置在範例性接觸特徵103a所連接的對應跡線120a的頂部上。長形接觸特徵103a可僅沿著跡線120a的部分延伸並且可選擇長度l和寬度w以確保第一半導體元件101a的接觸特徵103a與第二半導體元件101b的對應接觸特徵103b相交並接觸。第二半導體元件101b的接觸特徵103b是示於圖11B中，以便說明當被對準以接觸時它們的相對定向。
在圖11A至圖11C中所示的長形接觸特徵103a和103b的長度l可以是在0.05微米至500微米的範圍中、在0.05微米至100微米的範圍中、在0.05微米至50微米的範圍中、在0.1微米至50微米的範圍中、在1微米至50微米的範圍中、在5微米至50微米的範圍中、在10微米至50微米的範圍中、在10微米至40微米的範圍中或在15微米至30微米的範圍中。接觸特徵103a和103b的寬度W可以是足夠小以避免凹陷的問題、減少寄生電容以及在半導體元件101上保持小的覆蓋區。舉例而言，接觸特徵103a的寬度可以是在0.01微米至10微米的範圍中、在0.01微米至5微米的範圍中、在0.1微米至10微米的範圍中、在0.1微米至5微米的範圍中、在0.5微米至5微米的範圍中、在0.5微米至4微米的範圍中、在1微米至5微米的範圍中、在1微米至3.5微米的範圍中或在1.5微米至3微米的範圍中。接觸特徵的寬度可以是與它們所延伸的跡線102a的寬度相同、在±10%內，更特別地在±5%內。
如圖11C中所示，來自第一半導體元件101a的接觸特徵103a可在相交點區域104處與來自第二半導體元件101b的對應接觸特徵103b接觸並接合。在圖11C中所示的範例性接觸特徵103a可僅設置在與該接觸特徵103a相關的跡線120a上方並且跡線120a電性接觸。在相同的金屬化層(metallization level)內，與其他接觸特徵(未示出)相關的跡線120a可延伸以與所說明的接觸特徵103a相關的跡線120a大致上平行且不相交。類似地，第二半導體元件101b的範例性接觸特徵103b可延伸在僅與接觸特徵103b相關的跡線120b上方並且跡線120b電性接觸。如圖11C中所示，接觸特徵103b和其跡線120b可相對於接觸特徵103a和其跡線120a非平行地延伸(例如，大致上垂直)。雖然跡線120B在圖11C中被解釋為橫向地延伸(例如與跡線120a非平行)，但是在其他配置中，第二元件101b的接觸特徵103b可與其他類型的內部繞線特徵連接，包括垂直和/或水平的繞線特徵或在任何其他方向上延伸的繞線特徵。再者，在一些配置中，第一半導體元件101a的繞線特徵可以與第二半導體元件101b的繞線特徵不同。舉例而言，跡線120a可以僅在第一元件101a中形成，並且其他類型的繞線特徵可在第二元件101b中形成。
有利的是，在圖11A至圖11C中所說明的實施例可允許使用更小的接觸特徵，其可減少寄生電容同時提升接合結構的對準精確度。再者，接觸特徵103a和103b相對於對應跡線120a和120b的定位可允許有效地繞送電性訊號而不需要提供多個繞送和/或接觸層。由於所說明的接觸特徵103a從下方的横向跡線直接地延伸，金屬化層是完全用於橫向繞送而不需要單獨用於垂直連接(諸如通孔)的中間的層間介電質(intervening interlevel dielectric，ILD)。如同圖9A至圖10的實施例，半導體元件101a和101b可包括任何合適類型的半導體元件。舉例而言，在一實施例中，第一半導體元件101a可包括中介件並且第二半導體元件101b可包括整合式裝置晶粒。在其他實施例中，半導體元件101a和101b兩者皆可包括整合式裝置晶粒。
圖12A至圖12H是根據各種其他實施例的傳導性接觸結構102的示意性俯視圖。除非另外說明，在圖12A至圖12H中所示的參考數字表示與圖8A至圖11C中所引用的構件大致上類似的構件。舉例而言，半導體元件(未示出)可包括對應的傳導性接觸結構102和相鄰接觸結構102所設置的非金屬性接合區域106。傳導性接觸結構102可包括長形接觸特徵103a和103b。在圖12A至圖12H，僅示出與對應的半導體元件相關的一個接觸特徵103a。如同圖10的實施例，接觸特徵103a和103b可包括經二維地圖案化的接觸特徵，例如界定二維的長形接觸特徵的圖案用以改善接合結構的對準的多個相交的傳導區段。舉例而言，圖12A至圖12H中的接觸特徵103a可包括由繞著中心區域設置的長形區段所組成的接合結構。在圖12A至圖12H中所示的接觸特徵103a界定可有助於改善接合結構的旋轉對準的長徵接觸特徵的圖案。舉例而言，在圖12A至圖12H中，接觸結構102可包括旋轉對稱、或接近對稱的長形接觸特徵103a。因此，圖12A至圖12H中的長形接觸特徵103a可容許線性對準偏差，因為接觸結構102包括多個長形傳導區段。長形接觸特徵103A亦可容許旋轉對準偏差，因為兩個旋轉地未對準的接觸結構102中的向外延伸的區段122可在兩個經接合的半導體元件之間提供足夠的電性連接。
接觸結構102的圖案可以包括任何合適的形狀。舉例而言，如圖12A中所示，接觸結構102可以包括撓著中心區域C設置的多邊形邊界B(例如，四邊形、矩形或正方形邊界)，中心區域C可以在或可以不在接觸結構102的幾何中心。向外延伸的區段122可從中心區域C向外徑向延伸，以便減少轉動的和橫向的對準偏差。如同圖12A，圖12B的接觸結構102可以包括撓著中心區域C設置的多邊形邊界B。此外，多個橫向連接件124可以將向外延伸的區段122互連，其可進一步減少對準偏差。
圖12C至圖12D說明具有多邊形邊界B的接觸結構102，多邊形邊界B包括五邊形邊界。在圖12D中，橫向連接件124可以將向外延伸的區段122互連。圖12E至圖12F說明具有多邊形邊界B的接觸結構102，多邊形邊界B包括六邊形邊界。在圖12F中，橫向連接件124可以將向外延伸的區段122互連。雖然圖12A至圖12F描繪具有四邊形、五邊形和六邊形輪廓的多邊形邊界，但是應該理解的是可以使用任何合適的多邊形邊界。再者，如圖12G至圖12H中所示，接觸結構102亦可包括彎曲的接觸特徵103a，例如圓形或橢圓形邊界B。圖12F說明將向外延伸的區段120連接的橫向連接件124。
因此，在此處所揭示的長形接觸特徵103a和103b可以界定任何合適的圖案。有利的是，接觸特徵103a和103b可以改善橫向的和/或轉動的對準偏差，同時在直接接合的半導體元件之間提供電性互連。
有可能的是按照上面的教示對於本發明做出許多修改和變化。因此應該理解的是，在所附申請專利範圍的範疇內，可用與在此處所特別描述不同的方式實施本發明。
100‧‧‧接合結構
101‧‧‧半導體元件
102‧‧‧接觸結構
103a‧‧‧接觸特徵
103b‧‧‧接觸特徵
104‧‧‧相交點
105‧‧‧互連
106‧‧‧接合區域

Claims (20)

  1. 一種接合結構，其包括：第一半導體元件，其包括傳導性第一接觸結構和相鄰所述第一接觸結構的非金屬性第一接合區域，所述第一接觸結構包括傳導性第一長形接觸特徵；以及第二半導體元件，其包括傳導性第二接觸結構和相鄰所述第二接觸結構的非金屬性第二接合區域，所述第二接觸結構包括傳導性第二接觸特徵，其中所述第一接合區域與所述第二接合區域接觸並且直接接合，以及其中所述第一長形接觸特徵被定向以與所述第二接觸特徵非平行，並且在所述第一長形接觸特徵和所述第二接觸特徵之間的相交點處與所述第二接觸特徵直接接觸。
  2. 如申請專利範圍第1項所述的接合結構，其中所述第一長形接觸特徵在所述相交點處與所述第二接觸特徵直接接合。
  3. 如申請專利範圍第1項所述的接合結構，其中所述第二接觸特徵包括長形接觸特徵。
  4. 如申請專利範圍第3項所述的接合結構，其中所述第一長形接觸特徵的第一側上的氧化物與所述第二長形接觸特徵的第一側與第二側上的對應氧化物區域接合。
  5. 如申請專利範圍第1項所述的接合結構，其中所述第一接觸結構包括格柵圖案形式的多個線路。
  6. 如申請專利範圍第1項所述的接合結構，其中所述第一接觸結構界定了繞著中心區域設置的邊界和從所述中心區域向外延伸的多個傳導區 段。
  7. 如申請專利範圍第6項所述的接合結構，其進一步包括多個橫向連接件，其連接所述多個傳導區段。
  8. 如申請專利範圍第7項所述的接合結構，其中所述邊界包括多邊形或圓形圖案。
  9. 如申請專利範圍第1項所述的接合結構，其中所述第一長形接觸特徵具有長度與寬度，所述長度是所述寬度的至少兩倍。
  10. 如申請專利範圍第9項所述的接合結構，其中所述第一長形接觸特徵的所述長度是所述寬度的至少五倍。
  11. 如申請專利範圍第1項所述的接合結構，其中所述第一接觸結構和所述第二接觸結構中的至少一者包括金屬和傳導性摻雜的半導體材料中的至少一者。
  12. 如申請專利範圍第1項所述的接合結構，其進一步包括直通矽晶穿孔(TSV)，其被設置在所述第一半導體元件內而在所述第一長形接觸特徵和所述第二接觸特徵的所述相交點之下。
  13. 如申請專利範圍第12項所述的接合結構，其進一步括一或多個傳導跡線，其被設置在所述TSV和所述第一長形接觸特徵之間且電性連接所述TSV與所述第一長形接觸特徵。
  14. 如申請專利範圍第1項所述的接合結構，其中所述第一長形接觸特徵和所述第二接觸特徵中的至少一者是彎曲形的。
  15. 一種接合方法，其包括：提供第一半導體元件，其包括傳導性第一接觸結構和相鄰所述第一接 觸結構的非金屬性第一接合區域，所述第一接觸結構包括傳導性第一長形接觸特徵；提供第二半導體元件，其包括傳導性第二接觸結構和相鄰所述第二接觸結構的非金屬性第二接合區域，所述第二接觸結構包括傳導性第二接觸特徵；定向並且組裝所述第一半導體元件和所述第二半導體元件，使得所述第一長形接觸特徵和所述第二接觸特徵是非平行的；直接接合所述第一接合區域與所述第二接合區域；以及在所述第一長形接觸特徵和所述第二接觸特徵之間的相交點處，直接接合所述第一長形接觸特徵和所述第二接觸特徵。
  16. 如申請專利範圍第15項所述的方法，其中直接接合所述第一接合區域與所述第二接合區域包括在所述第一長形接觸特徵和所述第二接觸特徵之間留下初始間隙，並且加熱所述第一半導體元件和所述第二半導體元件以使所述第一長形接觸特徵直接接觸所述第二長形接觸特徵。
  17. 如申請專利範圍第15項所述的方法，其進一步包括在直接接觸之前，將所述第一長形接觸特徵直接形成在對應跡線上，所述跡線沿著所述第一長形接觸特徵的長度對準。
  18. 一種半導體元件，其包括：基板，其包括一或多層非金屬性材料；多個傳導跡線，其被嵌入在所述基板中，所述跡線橫向地延伸穿過所述基板以橫向地繞送電性訊號；以及長形接觸特徵，其沿著所述多個跡線中的第一跡線延伸並且直接接觸 所述第一跡線，所述接觸特徵在所述基板的頂部表面處暴露。
  19. 如申請專利範圍第18項所述的半導體元件，其中所述接觸特徵沿著所述第一跡線的長度的部分延伸。
  20. 如申請專利範圍第18項所述的半導體元件，其中所述長形接觸特徵覆蓋所述第一跡線的第一部分，並且其中絕緣材料覆蓋所述第一跡線的第二部分。
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