CN108369913A - 提升直接接合的接触对准容限 - Google Patents

提升直接接合的接触对准容限 Download PDF

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Publication number
CN108369913A
CN108369913A CN201680073087.2A CN201680073087A CN108369913A CN 108369913 A CN108369913 A CN 108369913A CN 201680073087 A CN201680073087 A CN 201680073087A CN 108369913 A CN108369913 A CN 108369913A
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China
Prior art keywords
contact
metal
elongated
feature
characteristic
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CN201680073087.2A
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Inventor
保罗·M·恩奎特斯
盖乌斯·吉尔曼·方腾·二世
贾维尔·A·狄拉克鲁兹
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Anglo Sai Bond Technology Co Ltd
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Anglo Sai Bond Technology Co Ltd
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Publication of CN108369913A publication Critical patent/CN108369913A/zh
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Abstract

一种接合装置结构包括：第一基板，其具有第一组传导性接触结构(较佳的是连接到一装置或电路)，并且具有在第一基板上相邻接触结构的第一非金属性区域；第二基板，其具有第二组传导性接触结构(较佳的是连接到一装置或电路)，并且具有在第二基板上相邻接触结构的第二非金属性区域；以及在第一组和第二组接触结构之间的接触接合接口，其是藉由将第一非金属性区域接触接合至第二非金属性区域所形成。接触结构包括在两个基板上是非平行的长形接触特征(诸如个别线路或在格栅中连接的线路)，而在相交点接触。因而，改善了对准容限同时使凹陷和寄生电容最小化。

Description

提升直接接合的接触对准容限
相关申请案的交互参照
本申请案请求于2015年12月18日所提交的美国临时专利申请案第62/269,412号的权益，其整体内容基于一切目的在此处以引用的方式被并入。
背景
技术领域
本发明的技术领域是有关于直接晶圆接合，并且更具体地说是有关于要被用于半导体装置和集成电路制造中的基板的接合和电性互连。
背景技术
随着逼近了习知CMOS装置的物理极限且对于高效能电子系统具有迫切需求，系统单芯片(SOC)变成半导体产业的一种自然解决方案。为了制备系统单芯片，在一芯片上需要各种不同的功能。虽然硅技术是处理大量装置的主流技术，但是许多想要的电路及光电功能现今可从硅之外的材料制成的个别装置和/或电路来有效获得。因此，将非硅基组件与硅基组件整合的混合式系统有可能提供单独采用纯硅或纯非硅组件所无法提供的独特SOC功能。
一种异质性装置整合的方法已经将不相似的材料异质磊晶成长在硅上。至今为止，此异质磊晶成长已经在异质磊晶成长膜中产生高密度的瑕疵，其大部份是因为非硅膜与基板之间的晶格常数不匹配所导致。
另一种异质性装置整合的途径已经采用晶圆接合技术。然而，在升高温度下具有不同热膨胀系数的不相似材料的晶圆接合会导入会造成错位产生、脱胶或裂痕的热应力。因此，低温接合是有需要的。如果不相似材料包括低分解温度的材料或温度敏感性装置(举例而言，诸如InP异质接合双极性晶体管或具有超浅源极和汲极轮廓的经处理Si装置)，则低温接合对于不相似材料的接合亦很重要。
在含有不同材料的相同芯片上产生不同功能所需要的制程设计是困难并且难以进行优化。事实上，所产生的许多SOC芯片(特别是具有较大整合尺寸者)展现出低的良率。一种途径已经藉由晶圆黏着剂接合和层转移来互连经完全处理的IC。举例而言，请参考Y.Hayashi、S.Wada、K.Kajiyana、K.Oyama、R.Koh、S.Takahashi以及T.Kunio的Symp.VLSITech.Dig.95(1990)的研讨会文件及美国专利案5,563,084号，两个参考文件的整体内容在此处以引用方式并入。然而，晶圆黏着剂接合通常在升高温度下操作且受到热应力、渗气、气泡形成以及黏着剂不稳定等困扰，导致制程的良率降低且随时间经过有不良的可靠度。并且，黏着剂接合通常不是密封的。
晶圆直接接合是一种可使晶圆在室温下接合而不用任何黏着剂的技术。室温直接晶圆接合通常是密封的。其不像黏着剂接合一样容易导入应力及非均质性。再者，如果低温接合晶圆对可承受薄化制程，则当经接合对中的一晶圆被薄化至比特定材料组合的各自临界值更小的厚度时，可加以避免在后续热处理步骤期间的层中产生错位差排和经接合对的滑动或裂痕。举例而言，请参考Q.-Y.Tong以及U.的Semiconductor WaferBonding:Science and Technology,John Wiley&Sons,New York,(1999)，该文件的整体内容在此处以引用方式并入。
再者，晶圆直接接合及层转移是一种VLSI(超大型集成(Very Large ScaleIntegration))兼容性、高可变性且可制造的技术，因而适于形成三维系统单芯片(3-DSOC)。可将3-D SOC途径视为既有集成电路的整合以在芯片上形成系统。
再者，随着整合复杂度的增高，整合制程以在低温下且较佳的是在室温下来坚固地联合多样电路导致产生较低或没有额外应力及更可靠的电路的需求亦增高。
对于3D-SOC制备而言，被接合的晶圆或晶粒之间的金属的低温或室温直接晶圆接合是有利的。此直接金属接合可被使用以与在晶圆或晶粒之间非金属的直接晶圆接合结合，以在当晶圆或晶粒被机械接合时在它们之间导致电性互连。同时的金属和非金属接合可消除后接合处理(如基板薄化、通孔蚀刻和互连金属化)的需要，以达成经接合的晶圆或晶粒之间的电性互连。可使用极小的接合金属垫，导致有极低的寄生阻抗且导致减少的功率及增加的带宽容量。
金属与干净表面的接合是为人熟知的现象。举例而言，已经将热压缩导线接合施加至晶圆级接合。一般采用温度、压力及低硬度金属，且通常会导致残留应力。举例而言，请参考M.A.Schmidt的Proc.IEEE,Vol.86,No.8,1575(1998)；Y.Li、R.W.Bower和I.Bencuya的Jpn.J.Appl.Phys.Vol.37,L1068(1988)。在250至350℃下Pd金属层涂覆的硅或III V化合物晶圆的直接接合已经被B.Aspar、E.Jalaguier、A.Mas、C.Locatelli、O.Rayssac、H.Moricean、S.Pocas、A.Papon、J.Michasud and M.Bruel在Electon.Lett.,35,12(1999)中提到。然而，实际上是形成及接合Pd2Si硅化物或Pd-III V合金，而非金属Pd。已经在覆晶接合下利用超音波及压缩性负载在室温下达成Au及Al的接合，举例而言，请参考M.Hizukuri、N.Watanabe and T.Asano的Jpn.J.Appl.Phys.Vol.40,3044(2001)。已经在具有低于3x10-8mbar的基底压力(base pressure)的超高真空(ultrahigh vacuum，UHV)系统中实现晶圆级的室温金属接合。通常，使用离子氩溅镀或快速原子束来清洁接合表面，接着将外部压力施加至接合基板。举例而言，请参考T.Suga的Proc.The 2nd Intl.Symposium onsemiconductor wafer bonding,the Electrochemical Soc.Proc.Vol.93-29,p.71(1993)。亦已经利用在具有小于3x10-8mbar基底压力的UHV系统中在4至40μbar的Ar压力的薄膜溅镀沉积之后的施力来达成具有薄形溅镀的Ti、Pt及Au膜的两个Si基板之间的室温接合。举例而言，请参考T.Shimatsu,R.H.Mollema,D.Monsma,E.G.Keim and J.C.Lodder的J.Vac.Sci.Technol.A 16(4),2125(1998)。
金属特征或接点和非金属场区域的直接接合是揭露于美国专利号第7,485,968号及美国专利号第6,962,835号，其每一者的揭示内容在此处以引用的方式被清楚地并入。然而，要实现来自两个基板的金属特征的对准并实现可靠的金属接合同时又要直接接合外围的非金属区域会是有挑战性的。
发明内容
在一实施例中，接合结构被揭示。所述接合结构可包括：第一半导体组件，其包括传导性第一接触结构和相邻所述第一接触结构的非金属性第一接合区域，所述第一接触结构包括传导性第一长形接触特征。所述接合结构亦可包括：第二半导体组件，其包括传导性第二接触结构和相邻所述第二接触结构的非金属性第二接合区域，所述第二接触结构包括传导性第二接触特征。所述第一接合区域可与所述第二接合区域接触并且直接接合。所述第一长形接触特征可被定向以与所述第二接触特征非平行并且在所述第一长形接触特征和所述第二接触特征之间的相交点处与所述第二接触特征直接接触。
在另一实施例中，接合方法被揭示。所述接合方法可包括：提供第一半导体组件，其包括传导性第一接触结构和相邻所述第一接触结构的非金属性第一接合区域，所述第一接触结构包括传导性第一长形接触特征。所述方法可包括：提供第二半导体组件，其包括传导性第二接触结构和相邻所述第二接触结构的非金属性第二接合区域，所述第二接触结构包括传导性第二接触特征。所述方法可包括：定向并且组装所述第一半导体组件和所述第二半导体组件，使得所述第一长形接触特征和所述第二接触特征是非平行的。所述方法可包括：直接接合所述第一接合区域与所述第二接合区域。所述方法可包括：在所述第一长形接触特征和所述第二接触特征之间的相交点处，直接接合所述第一长形接触特征和所述第二接触特征。
在又另一实施例中，接合结构被揭示。所述接合结构可包括：第一半导体组件，其包括传导性第一接触结构和相邻所述第一接触结构的非金属性第一接合区域，所述第一接触结构包括由多个相交线路所组成的传导性第一格栅图案。所述接合结构可包括：第二半导体组件，其包括传导性第二接触结构和相邻所述第二接触结构的非金属性第二接合区域，所述第二接触结构包括由多个相交线路所组成的传导性第二格栅图案。所述第一接合区域可与所述第二接合区域接触并且直接接合。所述第一格栅图案可与所述第二格栅图案相交并且直接接触。
在另一实施例中，接合结构被揭示。所述接合结构可包括：第一半导体组件，其包括传导性第一接触结构和围绕所述第一接触结构的非金属性第一接合区域。所述第一接触结构可包括传导性第一长形接触特征，所述第一长形接触特征包括重度掺杂的半导体材料。所述第一接合区域可包括轻度掺杂或未掺杂的半导体材料。所述接合结构可包括：第二半导体组件，其包括传导性第二接触结构和围绕所述第二接触结构的非金属性第二接合区域，所述第二接触结构包括传导性第二接触特征。所述第一接合区域可与所述第二接合区域接触并且直接接合。所述第一长形接触特征可与所述第二接触特征直接接触并且直接接合。
在又另一实施例中，半导体组件被揭示。所述半导体组件可包括：基板，其包括一或多层非金属性材料。所述半导体组件可包括：多个传导迹线，其被嵌入在所述基板中，所述迹线横向地延伸穿过所述基板以横向地绕送电性讯号。所述半导体组件可包括：长形接触特征，其沿着所述多个迹线中的第一迹线延伸并且直接接触所述第一迹线，所述接触特征在所述基板的顶部表面处暴露。
因此，本发明的一个目的是以单一接合步骤在晶圆和晶粒之间取得机械和电性连接。
本发明的另一个目的是提供一种低温或室温接合方法，具有半导体电路的晶圆或晶粒之间的金属性接合可藉此在无需使用外部压力的环境下被形成。
本发明的额外一个目的是提供一种低温或室温接合方法，具有半导体电路的晶圆或晶粒之间的任何金属层的金属性接合可藉此藉由使金属层覆盖有金或铜或钯的薄膜在无需使用外部压力的环境下以晶圆级在室温下被形成。
本发明的又另一个目的是提供一种在无需使用外部压力的环境中的晶圆级室温接合方法，金属性和共价结合是藉此在室温下被同时形成于包括半导体电路而有金属和其他非金属层共存的晶圆或晶粒的接合表面上。
本发明的另一个目的是提供一种室温接合方法，具有不同热膨胀系数的不同基板或不同基板上的不同材料可藉此被接合在一起而不会在不同基板或不同基板上的不同材料之间产生灾难性应力。
本发明的又另一个目的是提供一种室温接合方法，在基板之间的接合强度藉此接近基板的机械断裂强度。
本发明的另一个目的是提供一种接合装置结构，其包括被个别制作于分开的基板上且接合于共同基板的装置。
本发明的又另一个目的是提供一种方法和一种装置，藉此可靠的机械接合可在室温下或在接近室温下被形成且可靠的电性接触可用简单的低温退火被后续地形成。
本发明的这些与其他的目的是藉由一种接合方法和一种装置结构来达成，装置结构包括：第一基板，其具有第一多个金属性接合垫(较佳的是被连接到一装置或电路)，并且具有在第一基板上相邻金属性接合垫的第一非金属性区域；第二基板，其具有与第一多个金属性接合垫对准或可与第一多个金属性接合垫对准的第二多个金属性接合垫(较佳的是被连接到一第二装置或电路)，并且具有在第二基板上相邻金属性接合垫的第二非金属性区域；以及接触接合接口，其在第一组金属性接合垫和第二组金属性接合垫之间。
附图说明
在当结合附图考虑时通过参照下列详细描述可变得更为理解本发明所揭示的实施例及其许多附随优点，将容易地获得对其更全面的了解，其中：
图1A是一对未接合基板的示意图，其具有经对准金属接合垫。
图1B是一对未接合基板的示意图，其具有已接触的经对准金属接合垫。
图1C是一对已接触基板的示意图，其在远离金属接合垫的非金属区域中被接合。
图1D是一对已接触基板的示意图，其在横跨除了靠近金属接合垫的小的未接合环形面积之外的非金属区域被接合。
图2A是说明在接合之前具有多个接合垫的接合基板的示意图。
图2B是在接合垫被接触之后接合基板的示意图。
图2C是当非传导性区域被接合时接合基板的示意图。
图2D是示出了以金属垫厚度2h为函数的未接合环形面积的宽度W的曲线图，金属垫厚度2h如插图中所示分开半导体晶粒。
图3A是在表面平坦化之后半导体晶粒或晶圆的示意图。
图3B是半导体晶粒或晶圆的示意图，其中第二金属层被形成且平坦化以具有在金属垫上所打开的接触窗口。
图3C是具有第二金属层的第二半导体晶粒或晶圆的示意图。
图3D是由二个晶粒或晶圆所组成的经对准金属接合的示意图。
图4A是示出在氧化物涂层中的嵌入金属垫的基板部件的示意图。
图4B是具有相对应金属接合垫的一对未接合基板的示意图。
图4C是示出藉由非金属区域接触及接合时所产生的力所接触的相对应金属接合垫的一对接合基板的示意图。
图4D是被接合至较大基板的一对较小基板的示意图。
图5A是在金属垫之下具有可变形材料或空隙的实施例的示意图。
图5B是在金属垫之下具有可变形材料的实施例的示意图。
图5C是两个如图5A中所示的装置接合在一起的示意图。
图6A是在非金属表面的直接晶圆接合之前具有暴露于两个装置上的表面的可回焊金属材料的实施例的示意图。
图6B是具有在非金属表面的直接晶圆接合之后被密封的可回焊金属材料的实施例的示意图。
图6C是具有在非金属表面的直接晶圆接合密封住可回焊金属之后被回焊的可回焊金属的实施例的示意图。
图7A是具有在非金属表面的直接晶圆接合之前暴露于两个装置上的表面的可回焊金属材料的实施例的示意图。
图7B是具有在非金属表面的直接晶圆接合之后被密封的可回焊金属材料的实施例的示意图。
图7C是具有在非金属表面的直接晶圆接合密封住可回焊金属之后回焊的可回焊金属的实施例的示意图。
图8A是在第一半导体组件和第二半导体组件被组装在一起之前的两个组件的示意性侧边截面图。
图8B是在接合区域被直接接合在一起之后中间接合结构的示意性侧边截面图。
图8C是在接触特征被直接接合在一起之后接合结构的示意性侧边截面图。
图9A是根据一实施例的接合半导体结构中的传导特征的位置的示意性俯视图。
图9B是图9A的接合半导体结构的示意性侧边截面图。
图10是根据另一实施例的接合半导体结构中传导特征的位置的示意性俯视图。
图11A是具有与对应下方迹线连接的多个长形接触特征的第一半导体组件的示意性平面图。
图11B是第一半导体组件的示范性接触特征和相关联的下方迹线以及第二半导体组件的接触特征的示意性平面图，第二半导体组件的接触特征被对准以在交叉指向上与第一半导体组件的接触特征接触。
图11C是两个接合半导体组件的示意性侧边截面图，两个接合半导体组件在两个组件的交叉接触特征之间具有直接连接。
图12A是根据各种其他实施例的具有四边形轮廓的传导性接触结构的示意性俯视图。
图12B是根据另一实施例的具有四边形轮廓的多边形传导性接触结构的示意性俯视图。
图12C是根据各种实施例的具有五边形轮廓的传导性接触结构的示意性俯视图。
图12D是根据另一实施例的具有五边形轮廓的传导性接触结构的示意性俯视图。
图12E是根据各种实施例的具有六边形轮廓的传导性接触结构的示意性俯视图。
图12F是根据另一实施例的具有六边形轮廓的传导性接触结构的示意性俯视图。
图12G是根据各种实施例的具有圆形轮廓的传导性接触结构的示意性俯视图。
图12H是根据另一实施例的具有圆形轮廓的传导性接触结构的示意性俯视图。
具体实施方式
现在参考图式，其中几个图中类似的参考数字代表类似或对应的部件，更特别地参考解释了接合制程的第一实施例的图1A至图1D及图2。在第一实施例中，当分开的晶圆上的金属接触区域一旦对准而被位于金属性区域周边的非金属性区域经历室温化学接合所产生的本征力量给予接触压力接合时，将产生直接金属-金属接合。本说明书全文所使用的化学接合是被定义为当一晶圆的表面上的表面接合与一相对晶圆的表面上的表面接合起反应时所形成的接合强度，以形成横越表面组件的直接接合，诸如共价结合。化学接合展示出高接合强度，例如接近晶圆材料的断裂强度，因此不同于(举例而言)只有凡德瓦键结的状况。下面讨论所揭示的实施例的方法所达成的化学接合强度的范例。显著的力在化学接合制程中被形成。这些力可足够大以随着化学接合传播于相对非金属性区域之间而增加金属性区域的内部压力。
图1A示出二个晶圆10和13，其具有各自相对的晶圆表面11和14。晶圆表面可以是钝元素的半导体表面，可以是包括相对少量天然氧化物的钝元素的半导体表面，或可以是诸如氧化物涂覆的表面的绝缘体。在各种实施例中，晶圆表面可包括以下的至少一种：玻璃、硅上绝缘体、氮化硅、碳化硅、蓝宝石、锗、砷化镓、氮化镓、聚合物、磷化铟或任何其他合适的材料。为了产生平滑、活化的表面，表面可以是如同在美国专利第6,984,571、6,902,987和6,500,694号中所描述的而制备，其每一者的内容在此以引用的方式将其整体并入。诸如研磨或抛光和极微蚀刻(very slightly etching，VSE)的技术可被加以使用。接合层可被沉积且研磨或抛光，并且被稍微地蚀刻。所得的表面是辅助性的并且具有平坦且平滑的化学接合表面，其化学接合表面的粗糙度是在至的范围中，较佳的是不大于并且更佳的是不大于
每一个晶圆皆包括在表面11和14中的一组金属性的垫12和15以及相邻金属性接合垫的非金属性区域。金属性接合垫的非平坦性及表面粗糙度可能大于化学接合表面的非平坦性及表面粗糙度。垫12和15可(直接地或间接地)电性连接至内部电路和/或直通硅晶穿孔(TSV)，并且可用来将电性连接绕送至预先制作在晶圆上的各自装置和/或电路。垫较佳的是在表面处理之前被形成，并且VSE较佳的是在形成垫之后进行。如同图1A中所示，在各别晶圆上的垫12和15被对准。图1B示出将晶圆放置在一起以使各自的垫接触的晶圆。在此阶段，垫12和15是可分离的。在图1C中，轻微的额外压力被施加至晶圆以使半导体晶圆中的一或两者弹性变形，导致晶圆上的一些非金属面积之间的接触。所示的接触位置仅是一个范例，并且可在不同位置处发生接触。另外，可在超过一个点处发生接触。此接触引发化学的晶圆到晶圆接合，并且该接合结构是被示于图1D中。接合面(bonding seam)16是在引发化学接合之后扩张，以产生如图1D中所示的接合面17。接合强度最初是薄弱的并且随着接合进行而增加，如同在美国专利第6,984,571、6,902,987和6,500,694号中所解释的，在此处以引用的方式将其完整并入。相对的非金属性区域是在室温或低温下被化学接合。
更详细而言，当包括金属接合垫的晶圆表面在室温下接触时，相对晶圆表面中的接触的非金属部分开始在接触点或多个接触点处形成接合，并且晶圆之间的吸引性接合力随着接触化学接合面积增加而增加。在没有金属垫存在的情况下，晶圆将横跨整个晶圆表面接合。金属垫的存在(虽然阻碍相对晶圆之间的接合面)并未阻止化学的晶圆到晶圆接合。由于金属接合垫的延伸性和延展性的关系，在非金属区域中藉由化学的晶圆到晶圆接合所产生的压力可产生一力，金属垫上的非平坦和/或粗糙区域可藉此变形而导致金属垫的平坦性和/或粗糙度受到改善以及金属垫之间有紧密接触。藉由化学接合所产生的压力是足以免除让这些金属垫彼此紧密接触所施加的外部压力。由于在配对接口处的金属原子的相互扩散(inter-diffusion)或自扩散(self-diffusion)的关系，可在紧密接触的金属垫之间形成强的金属性接合，甚至是在室温下。此扩散是被热力驱动以减少表面自由能并且由于通常具有高的相互扩散和/或自扩散的金属而被强化。这些高扩散系数是通常大部份由扩散期间未被金属离子的运动所扰乱的活动自由电子气体所决定的内聚能的结果。因此，在非金属区域中的晶圆到晶圆的化学接合在两个不同晶圆上的金属垫之间产生电性连接的效果。影响此效果的几何和机械限制因素是在下面被加以描述。
具有宽度W的在接合垫周围的未接合面积将被产生，在其中两个晶圆的非金属表面是被防止接触(见图1D)。只要金属膜的厚度不是太大，则两个接合晶圆或晶粒之间的间隙可以被减少，而在每一个金属垫周围留下小的未接合面积。这是在图2A至图2C中说明，其中具有金属垫21的晶圆20已准备好要被接合至具有垫23的晶圆22。横向间隙24是在相邻的垫之间。金属垫是被接触(图2B)，并且晶圆弹性变形以在间隙24中接合以形成接合25(图2D)。注意到，图2A至图2C中的尺寸并不是按比例绘制的。
下面将示出计算以金属膜厚度、晶圆或晶粒的机械性质、晶圆或晶粒厚度、接合能为函数的未接合面积的宽度的公式。图2D是示出未接合面积的间隙高度2h和宽度W之间的关系的曲线图。当晶圆的变形遵守杨氏模数E所给予的弹性常数并且晶圆各具有厚度tw时，根据薄板的小偏向的简易理论，可藉由W>2tw的下列等式粗略地估计未接合面积的宽度W，其中成为一对的金属接合垫在晶圆表面上面具有2h的高度：
W＝[(2E'tw 3)/(3γ)]1/4h1/2 (1)
其中E'由E/(l-ν2)提供，ν为泊松比(Poisson's ratio)。
已经建议，随着h减少，其情况将大幅改变。举例而言，请参考U.Goesele和Q.-Y.Tong的Proc.The 2nd Intl.Symposium on semiconductor wafer bonding,theElectrochemical Soc.Proc.Vol.93-29,p.71(1993)。如果等式(1)计算出的W导致数值低于Wcrit＝2tw，且其对应于h<hcrit而且hcrit＝5(twγ/E')1/2，则预定会发生弹性机械不稳定性，导致具有与晶圆厚度tw无关的远为较小的W的未接合面积，且其由下式求出：
W≈kh (2)
其中k为1左右的无因次常数。实验上，如图2D中所示，如果则W远小于等式(1)所预测者。本申请案的发明人的其他作品已经显示，如果金属接合垫对之间的间隔2R小于2W，则晶圆对可能未彼此接合。然而，当2R>2W时，金属柱周围的两个未接合面积之间的表面将接合，并且金属柱将被接合且电性连接。
可以下式表示周遭面积的接合所产生而位于金属接合对上的压力P：
P＝(16E'tw 3h)/(3W4) (3)
合并公式(3)与公式(1)或(2)，当W>2tw时，会获得下式：
P＝8γ/3h (4)
且当W<2tw时，会获得下式：
P＝(16E'tw3)/(3k4h3) (5)
对于金属垫具有的高度h且接合能是300mJ/m2的经接合的硅晶圆，金属接合垫上的压缩性压力约1.6x108dynes/cm2，亦即160大气压。因为此压力对于金属接合是够高，所以不需要在接合期间施加任何外部压力。当金属高度h为或更小时，可满足W<2tw，且如果假设k＝1，金属对上的压力是5000大气压左右。
在一范例中，具有小于的厚度及1mm的分开距离的5mm直径的Au接合垫是被沉积在氧化物涂覆的100mm硅晶圆上。因为Au接合垫形成于氧化物的表面上，所以其亦在氧化物的表面上方具有的高度。然而，因为金属可部份地埋设在氧化物或其他绝缘体中且h为金属延伸于晶粒表面上面的高度，所以h可远小于实际金属厚度。已经发展出一种可兼容且同时地清洁及活化金属及氧化物表面的室温接合技术。Au柱在储存于空气中一段取决于金属厚度和接合能而定的时间长度(例如，60小时)之后是在不需要外部压力的环境中以晶圆级的室温接合来形成金属接合。藉由将楔件插入经接合的接口之间使晶圆对被强迫分离时，Au或Au/氧化物层自硅基板剥离，代表所形成的金属至金属的接合比氧化物表面上的Au垫或硅表面上的氧化物的黏附更强。如上面所述，由于降低表面自由能的配对接口上的金属原子的相互扩散或自扩散的关系，一强力的金属性的垫可在室温下形成于亲密接触的金属垫之间。金属原子之间的相互扩散或自扩散系数随着温度呈指数性增加，藉以缩短储存时间以达成完全的金属性接合，可在室温接合之后进行退火。Au柱之间的金属性接合的较佳退火时间随着温度增高而缩短。对于此情况，100℃偏好采用5小时，150℃为1小时，250℃为5分钟。由于非金属的周遭面积的接合所产生的较高压力的关系，较薄的金属在接合时需要比较厚的金属更低的温度。随着Au厚度(亦即，高度)增加，在室温及升高温度下形成金属性接合的时间将变得较长。举例而言，当Au垫的厚度h为时，250℃需要5分钟来形成金属性接合，而在相同温度下则需要15分钟。
在目前最新技术水平的集成电路的覆晶接合中，焊料球的间距约为1000μm。因此，经接合的金属柱周围的接近1000μm或更小的未接合面积宽度对于实际应用来说是够小。可藉由此方法获得比此量显著更小的未接合面积宽度。举例而言，实验结果显示，当时，W为20μm，且当时，W为30μm。因为h为在晶粒表面上面延伸的金属高度，由于金属可部份地埋设在氧化物或其他绝缘体中，所以h可远小于实际金属厚度，可容易地达成小于的h。在此例中，金属垫周围的未接合环宽度可接近为零。上面所描述的金属垫可由诸如但不限于溅镀、蒸镀、雷射烧蚀、化学气相沉积以及该领域中习知此技术者所了解的其他技术等制程形成，其中将厚度控制在的范围中是典型的。
图3A至图3C是根据第二实施例的制程的示意图，两个不同的经加工晶粒是藉此被接合。晶粒是被示出以具有平坦的但非均匀的层厚度，以展示出除了均匀且平坦的层厚度之外，所揭示的实施例亦可被使用在其他实例中。在该制程中(如图3A中所示的)，一个别晶粒30(为了方便解释，其仅示出晶粒30的氧化物层)具有金属垫31。晶粒可以是包括半导体装置的硅晶圆，并且电路具有SiO2的相对表面。表面32在CMP操作之后产生。
如在图3B中所示的，通孔36已被形成且填充有金属以与金属垫31连接，金属互连33被形成在晶圆30上以与在通孔36中的金属连接，并且由SiO2组成而厚度t2的层34或其他绝缘材料是被形成在晶圆30上。宽度为W2的SiO2层的部分35已被移除以暴露金属垫35。层34的表面是如同在美国专利第6,984,571、6,902,987和6,500,694号中所描述的而被处理，包括研磨或抛光和极微蚀刻。
在图3C中，第二晶圆37具有如所示形成的垫38、填充有金属的通孔39和互连40。互连40具有宽度w1和高度t1。晶圆37的表面41已如表面32被处理，如同上面所讨论的。分开的晶粒30和37彼此对准并接触，以产生图3D中所示的接合结构。藉由下列关系式：
t1＝t2+δ1且w1＝w2+δ2
其中t1及δ1较佳的是所使用的沉积技术可能具有的最小厚度，而δ2应该是对应于2h＝t1的情况的2W。相较于待接合的两个晶粒上的h＝t1，未接合面积宽度W显著地降低。因此，在晶圆30和37上的垫之间产生互连。如果两个晶粒上的t1小于临界厚度hcrit，则不需要层34。
在室温下两个晶圆的初始接触期间，金属垫被对准，并且当间隙由于接合晶圆的表面形貌而足够小且接合能γ是足够高时，晶圆表面藉由弹性变形而彼此一致。直接接合发生于形成邻接晶粒上的装置或电路之间的金属互连的经接触材料之间及晶圆表面之间。在室温下，接合开始形成于接触上且接合强度增加以形成金属性接合。
如同第一实施例，包括金属垫33和40的晶圆表面32和41产生接触，相对晶圆表面32和41的接触的非金属(例如，半导体或绝缘体)部分开始在接触点处形成接合，且接合力随着接触接合面积增加而增加。在没有突出的金属垫33和40存在的情况下，晶圆将横跨整个晶圆表面接合。突出的金属垫30和40的存在(虽然阻碍了相对晶圆之间的接合面)并未阻止晶圆到晶圆接合。取而代之，非金属区域中晶圆至晶圆的接触所产生的压力转换成可藉以使金属垫33和40接触的力，甚至不需要任何外部压力。
可在高或超高(UHV)真空条件之外的环境条件下进行本发明的方法。因此，该方法是一种低成本、量产的制造技术。因为直接金属性接合只取决于分子间的吸引力，所以要被接合的金属膜的尺寸是可变的且可缩放成极小的几何形状。
为了使半导体装置有更好的热管理及功率能力，直接金属接合是较佳的。直接金属接合可以用可缩放的远为更小的接合垫来取代覆晶接合。进一步可能的是，可使用此金属接合来实现新型的金属基底装置(半导体-金属-半导体装置)。举例而言，请参考T.Shimatsu、R.H.Mollema、D.Monsma、E.G.Keim及J.C.Lodder的IEEE Tran.Magnet.33,3495(1997)。
再者，此制程可与VLSI技术兼容。可在晶圆受到完全处理时执行直接金属至金属接合。因为几乎所有金属皆具有比诸如上述的那些半导体或绝缘体(例如硅或硅氧化物)还要显著地更高的热膨胀系数，所以直接金属至金属的接合亦可利用相对低温或室温的接合来最小化热膨胀差异的影响。
在此处所描述的方法可局部地或横越整个晶圆表面面积接合。该方法(但是不限于以下范例)接合了异质性表面，使得金属/金属、氧化物/氧化物、半导体/半导体、半导体/氧化物和/或金属/氧化物区域可在室温下接合于两个晶圆之间。
本发明提供许多优点。举例而言，晶圆接合和将组成的电性接触电性互连的其他方法需要在晶圆接合之后薄化接合基板、通孔蚀刻及金属沉积。在此处所描述的方法甚至在不需要此些后接合制程步骤的情况下允许电性互连，而免除了晶粒薄化所造成的机械性损伤。再者，深的通孔蚀刻的免除避免了阶梯覆盖(step coverage)的问题并且可使电性连接缩放至较小尺寸，导致较小覆盖区的电性互连及在接合晶圆之间有减少的电性寄生。该方法是与其他标准半导体制程兼容，且与VLSI兼容。
因此，在此处所描述的方法是与3-D SOC(三维系统单芯片)制造兼容。在接合晶粒之间使用插塞的金属垫或互连的此种垂直金属接合可显著地简化SOC制造制程并改善SOC速度-功率效能。在此处所描述的直接金属至金属接合是可缩放的，且可被施加至多晶粒堆栈的SOC。
除了产生足够以形成金属至金属连接的力之外，该方法藉由金属接合的金属垫的无氧化物或接近无氧化物的表面而将有利于低电阻的金属接合。举例而言，可由紫外光/臭氧和氮电浆来清理Au表面，而在表面上未留下氧化物。
在另一实施例中，接合金属垫的表面(举例而言由诸如Al或Cu的金属所制成)是涂覆有抗氧化金属，举例而言诸如金(Au)或铂(Pt)层。由于Au和Pt两者皆为惰性金属，将不会有氧化物形成在表面上。为了确保在Au和Pt与主要金属之间有最小量的氧化物，溅镀清理和蒸镀沉积是被采用，较佳的是紧接在接合制程之前。
在第一实施例的修改例中，薄的金属涂覆层可形成于金属垫上且如上面所述地接合。举例而言，Al垫上的一层薄到的Au层在室温下产生成功的金属垫接合。因此，可使用诸如Au的金属作为接合层，藉由前述方法使得几乎所有金属皆可被用于在室温下直接接合。当绝缘体层被设置在经完全处理的晶圆上且接触开口被形成于金属垫上然后进行超过接触窗口的深度的厚度的金属沉积时，金属垫此时在氧化物层上面只延伸垫可彼此分离一段极小距离，譬如20μm。
除了Au或Pt之外，因为钯(Pd)有良好的抗氧化性，所以已经在此处所描述的直接接合中使用Pd作为涂覆层。Pd在Pd上具有很高的表面扩散性，导致即使在室温下仍有显著的Pd质量流动，特别是如果藉由非金属晶圆表面区域的接合而施加在金属接合垫上的接触的压力亦然。两个Pd接合层之间的自然氧化物(如果存在)将被机械式分散，而使得两个接触金属接合垫之间的实体接口完全地覆盖有Pd。
在第一实施例的另一修改例中，UV/臭氧清理使金属接合垫的表面在UV光下暴露于高臭氧浓度，以移除碳氢化合物污染物。金属接合垫的表面上的残留碳氢化合物劣化金属接合，并且成为接合接口之间气泡成形的成核位置(nucleation site)，导致接触表面之间的渗气。
实验已经显示UV/臭氧处理可防止接口气泡成形。硅晶圆的HF浸渍将导致大部份由H终止的疏水性表面。疏水性硅晶圆以4.77g/m3的臭氧浓度结合来自两个235W的UV灯的及UV照射在室温下处理15分钟，然后进行第二HF浸渍及接合。经接合的HF浸渍疏水性硅晶圆对在从300℃到700℃以各种温度及15小时退火时不会产生接口气泡，表示自晶圆表面有效地移除碳氢化合物。
对于Au及Pt而言，合适的是在接合之前使用UV/臭氧清理而在金属表面上不形成金属氧化物。对于可由臭氧氧化的其他金属而言，金属上具有Au的薄层可防止氧化，或者可举例而言藉由在接合之前浸入NH4Oh中来移除氧化物。此外，利用惰性和/或含氮气体的电浆处理(举例而言，电浆腔室中利用诸如氮和氩的气体的反应性离子蚀刻模式(RIE)的电浆处理)可清理金属表面并且在室温下增强接合能以用于金属/金属及氧化物/氧化物接合。再者，氧电浆可使被用以从诸如Au和Pt的金属表面移除污染物。
虽然已经描述许多种表面制备处理和金属/金属及氧化物/氧化物及半导体/半导体的范例，但是仍可使用其他种表面和制备程序，其中在接触之前充分地清理对应的金属、绝缘体和半导体表面以免抑制室温接合的形成。在Au保护或Au接合的情况下，制程是金属和硅氧化物兼容的。在氧化物表面的CMP和表面平坦化及平滑化之后，金属接合垫如上面所描述而形成于接合晶圆上，经修改的RCA 1(H2O：H2O2：NH4OH＝5：1：0.25)、UV/臭氧区和电浆处理清理了金属和氧化物两者的表面而不会使接合表面粗糙。室温标准29％NH4Oh的浸渍移除金属表面上的粒子及氧化物(如果存在)，而不劣化硅氧化物表面。在旋转干燥且室温接合及储存之后，强的共价结合和金属接合自发性地分别形成于氧化物层之间与金属表面之间的接合接口。除了图1A至图1D中所示接近平坦性的接合结构之外，其他结构亦可使用在此处所描述的原理。举例而言，图4A至图4C图中示出第二实施例，其中包括金属通孔互连的晶圆是被接合至较小的晶粒。图4A描绘包括金属互连51的基板50的放大图。在图4A中，金属互连被嵌入硅氧化物层52中，诸如PECVD氧化物、热氧化物或旋涂玻璃。互连51延伸在层52上面而到先前所述的高度。图4A亦示出具有金属接点54和硅氧化物层55的较小的晶粒53。
在将绝缘层58形成于具有诸如硅氧化物的材料的两个晶粒上之后，标准通孔蚀刻及金属充填、然后化学机械式抛光及表面处理被使用以制备用于接合的层58。图4B描绘具有相对应的金属接合垫56和57的一对相对晶圆。图4C示出这些两个相对基板的接触和后续接合，而形成接合59。
在此处，如前面所述，非金属区域的接合产生形成横越晶粒的金属至金属互连所需要的力。如图4C中所描绘，氧化物层的接合产生了金属接合垫56和57的直接金属至金属接触所需要的接合力。多个晶粒53可被制备且接合至晶粒60，如图4D中所示。
在第一和第二实施例的金属至金属直接接合中，在晶粒表面上面延伸的接合金属膜的厚度较佳的是薄的，以最小化金属柱周围的未接合环形面积。再者，接合金属垫的厚度可以缩放，且可制作及接合具有VLSI兼容尺寸的金属柱或垫。当金属膜厚度低于特定数值时，未接合环形面积的宽度是显著地降低，以使得在金属柱之间的间隔可允许在金属接合垫之间使用小的间隔(例如，<10μm)。
第三实施例可使在非金属表面上面的金属高度显著地增加及/或在金属附近的非接合面积显著地降低，同时在分开的晶圆上所形成的金属部分之间维持一可接受的电性连接。在此实施例中，形成电性接触的金属材料附近的材料变形被设计成起因于来自非金属部分的晶圆至晶圆的化学接合的金属表面处的压力。此变形可导致在接合制程完成之后施加至金属的压力较小，但仍有适当的压力以在金属部分之间形成可接受的电性连接。此变形使得在金属表面附近的间隙可显著地降低或消除。
可变形材料在形成电性接触的金属材料附近的目的是可让非金属表面的化学接合所产生的压力足够以使金属材料充分地凹入其各别表面中，以使得在金属表面附近的间隙可以被显著地减少或消除。一般而言，可变形材料包含非金属部分，因为晶圆至晶圆的化学接合所产生的压力通常是约为使典型金属变形所需要的压力的10000分之一或1％的1％。金属至其各自表面中的凹陷可使得在非金属表面上面的金属表面的起始高度实质上高于在凹陷之后的起始高度。这显著地增加了制备用于接合的晶圆所需要的金属表面的容限且随后增加了实施例的可制造性。变形亦显著地减少或消除了金属周围的非接合区域，而显著地增加可在给定区域中制作的连接数量且提高了经接合和互连的部件的接合强度。
变形可藉由将非金属区包括在金属表面底下来促进，如图5A中所解释。具有基板55的晶粒包括被形成于层51上的金属垫50，金属垫50将要被接合至另一装置上的对应层。藉由标准光微影、蚀刻以及沉积技术，区域53(其填充有诸如低K介电材料的可变形非金属材料)形成于层52中。层53和区域53形成于层54上。可将任何数目的层形成于基板54上。再者，区域53可大幅加大或者层52可以由低K材料所形成，如图5B中所示。
区域53亦可为包含真空或诸如空气的压缩性气体的空隙，或者其可以是具有够低压缩性可藉由接合所产生的压力让金属变形至区域中的可压缩非气态固体材料。可用与在化合物半导体集成电路制造中常见的金属性空气桥接类似的方式来形成空隙。此制造的其中一范例如下：1)在平坦、非金属表面中蚀刻出凹陷，2)以如同光阻的可移除材料来充填凹陷，以使得可移除材料位于凹陷中但不位于凹陷外。这可以举例而言藉由习知的光阻旋涂来进行，导致凹陷中有比凹陷之外更厚的光阻，接着进行足够量的光阻的毯覆(未图案化)蚀刻以移除凹陷之外的材料但不足够以移除凹陷中的材料，3)图案化出横过凹陷但未完全覆盖凹陷的金属特征，而留下凹陷的暴露部分，及4)藉由进接凹陷的暴露部分来移除凹陷中的移除材料。可压缩性非气态固体材料的范例是半导体制造中所使用的低K介电质。此区域的深度通常可接近或大于非金属表面上面的金属的所需要高度。图5A的晶粒所要接合的另一晶粒亦可具有一区域，如同在被接合至垫50的金属垫底下的对应位置上的区域53。这是在图5C中被解释，注意到图5C仅是示意图而未按比例绘制。在此处，垫50和56是由层51和57的接合所产生的压缩力所接合。图5C中的上方晶粒包括基板61，其具有形成于空隙上方的垫56或层58中的低K材料区域59。层58形成于层59上。并且，上方晶粒可具有许多层。
此实施例中，当晶圆接合时，金属表面产生接触且在化学接合制程期间相对于彼此发生变形。变形减缓了一些接合制程所施加的压力，但仍有足够的压力以使金属表面维持接触且在两个分开的晶圆上的两金属表面之间维持一可接受的最小接触阻力。随着金属变形至金属底下的区域中，接合表面得以在很靠近或紧邻金属的横向环带中接触，导致非金属表面之间有最大的接合面积。因此，可由所揭示的实施例形成与金属接触相邻的1至10微米或更小的最小化学非接合区域。
可变形区域被设计成为具有最小宽度，以最大化可能的电性互连数量。可变形区域的宽度主要取决于金属厚度及非金属表面上面的金属高度。这些参数大致由下列关系式决定。
应力＝(2/3)×(金属的杨氏模数)(1/1-金属的泊松比)×
(表面上方的金属高度/区域的一半宽度)2
及
压力＝应力×4×金属厚度×表面上方的金属高度/(区域的一半宽度)2
其中压力是接合制程所产生。这些关系式可参考在Maissel and Glang,1983Reissue,pp.12-24的“Handbook of Thin Film Technology”。
举例而言，对于约0.1微米的金属厚度、表面上的区域上面约0.1微米的金属高度以及约1微米的区域宽度而言，接合期间所产生的压力是大致上足够以使金属变形至区域中(假设可忽略区域的可压缩性)。注意到，如果金属不可变形，则此0.1微米的金属高度将导致金属周围约1mm的未接合环带或环宽度。由于非金属表面上面的金属高度需要较少控制，因此实质上增加了可制造性。再者，非接合面积是实质上减少，而允许显著地增加可制作的金属至金属接触数量且导致化学接合能的增加。如果无法忽略掉区域的可压缩性，则应依此降低金属的厚度和/或应依此降低非金属表面上面的金属高度和/或应依此增加区域的宽度。注意到，所应增加的区域的宽度的百分比数值是小于所应减少的非金属表面上面的金属高度或金属厚度的百分比数值。
第四实施例藉由仰赖低温后接合回焊退火以在经化学接合的晶圆之间形成可靠的电性互连，进一步松绑在第一、第二及第三实施例中所描述的金属接触附近的机械性设计拘限。参照图6A至图6C和图7A至图7C来提供此实施例的描述。
图6A示出具有平坦表面的基板60和61。凹陷62和63分别形成于基板60和61中，并且金属垫64和65分别形成于凹陷62和63中。平坦表面适于化学接合，如前面所描述。构成垫64和65的金属或金属的组合可以在低温下回焊。此金属的范例是在160度C的融化温度下回焊的铟，并且此金属的组合是在220度C的共晶融化温度下回焊的96.5％的锡及3.5％的银。
在制备了图6A中的表面以供直接化学接合并且将表面放置在一起之后，化学接合形成于平坦性表面之间。相较于实施例1及2，在金属接触邻近处因为接触凹陷而不具有间隙，但尚未作出可靠的电性互连。
在已经形成了图6B中的化学接合之后，空隙66是藉由从两个晶圆部份填充有金属的凹陷来形成。此空隙不会阻碍晶圆表面的合并以及形成与第一和第二实施例中的金属接触相似的化学接合。因此实现了最大化接合能的最大接合面积。在已经形成此高接合能化学接合之后，一低温回焊退火使凹陷中的金属回焊，导致来自相对晶圆的金属一起产生湿润并导致互连金属结构具有高可靠度。部分67是藉由回焊来形成，以连接垫64及65。此回焊是藉由具有高尺寸比的凹陷的毛细作用及(举例而言)如同晶圆在退火期间转动的重力的组合来辅助。
在第五实施例中，类似于第四实施例，图6A中的一个表面的金属凹陷以金属平台取代，以使得一晶圆上的平坦性表面上面的金属平台的高度小于其他晶圆上的平坦性表面下面的金属凹陷的深度，如第7A图所示。基板70和71具有各别的金属垫72和73。垫72形成于凹陷74中。在这种情况下，如第7B图所示，在构成化学接合的平坦性表面放置成为产生接触之后，金属表面一般不会接触。基板70和71的表面被制备以供直接化学接合且表面如同上述范例被放置在一起，并且在平坦性表面之间形成化学接合(图7B)。在回焊之后，以类似于第6C图的方式将两个不同晶圆上的金属湿润在一起，形成部分75，而产生第7C图。
因此，在此处所描述的实施例提供许多优点且不同于先前的低温晶圆接合技术。金属至金属的直接接合是自发性的且在室温下不需要外力。在金属柱上用于金属至金属接合所需要施加的压力是藉由接合制程本身而非外力来产生。上面所描述的金属至金属的直接接合可在环境条件下进行并且实现下列作用：晶圆级或晶粒尺寸的接合，在室温下形成的强力的金属性Au-Au、Cu-Cu或金属至金属接合，以及可藉由的Au层覆盖金属在室温下形成除了Au与Cu之外的金属的强力金属接合。因此，可同时达成金属/金属、氧化物/氧化物以及金属/氧化物的接合。金属至金属直接接合与标准VLSI加工兼容，所以是一种具有可制造性的技术。金属至金属直接接合是与覆盖有硅氧化物、硅或氮化硅的材料的接合相容。在各种实施例中，金属至金属的直接接合是与覆盖有以下至少一种的材料的接合兼容：玻璃、硅上绝缘体、氮化硅、碳化硅、蓝宝石、锗、砷化镓、氮化镓、聚合物、磷化铟或者任何其他合适的材料。
紧邻金属接合垫的非金属区域的直接接合是有助于金属至金属直接接合。如先前所述，在这些区域中是直接接合在相对的金属接合垫上产生合力。非金属性区域的直接接合在空中(in air)共价结合了覆盖有硅氧化物或其他绝缘体的晶圆，例如覆盖有以下至少一者的晶圆：玻璃、硅上绝缘体、氮化硅、碳化硅、蓝宝石、锗、砷化镓、氮化镓、聚合物、磷化铟或者任何其他合适的材料。可使用其他材料，举例而言，亦可在接合之前浸渍至氨溶液中的氟化的氧化物表面层。更一般而言，具有可由OH、NH或FH基团所终止的开放结构表面的任何材料以及多孔的低k材料在室温下接触时可形成共价结合。
可在纯粹或掺杂状态中使用诸如沉积、热或化学氧化的任何方法所形成的硅氧化物及旋涂玻璃。
本发明的应用包括但不限于垂直整合用于3-D SOC、微垫封装、低成本及高效能的覆晶接合置换、晶圆尺度封装、热管理及独特的装置结构(诸如金属基底装置)的经加工的集成电路。
图8A是在第一半导体组件101a和第二半导体组件101b被组装在一起之前的两个组件101a和101b的示意性侧边截面图。半导体组件101a和101b可包括对应的非金属性接合区域106a和106b以及具有接触特征103a和103b的传导性接触结构102。如图8A中所示，接触特征103a和103b可被设置在接合表面106a和106b下面，以使得对应的凹陷115a和115b是被形成在半导体组件101a和101b中。接触特征103a和103b可以任何合适的方式被形成在凹陷115a和115b中。举例而言，在一些实施例中，凹入的接触特征103a和103b可利用镶嵌制程形成。在此些镶嵌制程中，一或多个沟槽可(例如，藉由蚀刻)被形成在半导体组件101中，并且传导材料可被提供于沟槽中。在场区(field region)上方的传导材料可被抛光或是以其他方式移除，以形成图8A中的凹入的接触特征103a和103b。
接触特征103a和103b可包括适用于下面所描述的图9A至图9B的实施例的任何材料。接合区域106a和106b以及接触特征103a和103b可包括适用于下面所描述的图9A至图9B的实施例的任何材料。如下面所解释的，接合区域106a和106b可被制备以用于直接接合。举例而言，如同关于图9A至图9B的实施例所解释的，接合区域106a和106b可被抛光、被极细微地蚀刻和/或以想要的成分(诸如，氮)来终止。此外，如图8A中所示，互连105(例如TSV)可将接触特征103b连接至半导体组件101b的外部，以提供到较大的电性系统的电性通信。再者，尽管未示出，但是在互连105和接触特征103a之间可能存在有额外的内部金属化层。金属化和/或互连105可在将两个组件101a和101b接合在一起之前或之后形成。额外的细节可至少在美国专利第7,485,968号中被找到，在此处由于所有目的以引用的方式将其完整并入。
图8B是在接合区域106a和106b被直接接合在一起之后的中间接合结构100’的示意性侧边截面图。当接合区域106a和106b被组装为接触时，接合区域106a和106b可被直接接合在一起，以形成化学接合(例如，共价结合)而不具有中间的黏着剂。如同上面所解释的，直接接合可以在室温下和/或在不施加外部压力的情况下被进行。在接合区域106a和106b被直接接合在一起之后，在对应的接触特征103a和103b之间仍可能留有初始间隙120。应该理解的是，此间隙120亦可以在使接合区域106a和106b接触之后被实现，即使是如同在图7B中所示而在一侧上的接触突出亦然。
图8C是在接触特征103a和103b被直接接合在一起之后的接合结构100的示意性侧边截面图。在各种实施例中，举例而言，半导体组件101a和101b可在直接接合非传导性接合区域106a和106b之后被加热。在各种实施例中，半导体组件101a和101可以在75℃至350℃的范围中被加热，或更具体地在100℃至250℃的范围中被加热。加热半导体组件101a和101b可增加接触特征103a和103b的内部压力并且可使它们扩张以填充间隙120。因此，在接触特征103a和103b被直接接合在一起之后，接点125可实质上填充在两个半导体组件101a和101b之间的空隙。
如在图8C中所示的，第一接合区域106a可沿着接口130被直接接合至第二接合区域106b。在第一接合区域106a和第二接合区域106b之间的接口130实质上延伸至第一接触特征103a和第二接触特征103b，亦即延伸至被直接接合的接点125。因此，如在图8C中所示的，在接触特征103a和103b被接合在一起之后，在接触特征103a和103b之间以及在相邻的接合区域106a和106b之间可能没有间隙。不同于图1A至图5C的实施例，组件可不显示出围绕接点125的塑性变形。
半导体组件101a和101b的接合区域106a和106b下面的距离可以小于20nm，并且较佳的是小于10nm。接合接着温度升高可如同上面所述而增加接触特征103a和103b之间的内部压力，并且可改善金属接合、金属接触、金属互连或接触结构102之间的传导性。在各自的接合区域106a和106b下面的接触特征103a和103b的微小距离可以是横跨接触结构102的范围的平均距离。接触结构102的形貌亦可包括相等、大于和小于平均距离的位置。接触结构102的总高度变化(由最大高度和最小高度之间的差来给定)可以实质上大于均方根(RMS)变化。举例而言，具有1nm的RMS的接触结构可具有10nm的总高度变化。
因此，虽然接触特征103a和103b可稍微地在接合区域106a和106b下面，部分的接触特征103a和103b可延伸在接合区域106a和106b上面，而导致在接合非金属的接合区域106a至非金属的接合区域106b之后在接触特征103a和103b之间有机械连接。由于不完全的机械连接或是在接触特征103a和103b上的自然氧化物或其他污染物的缘故，该机械连接可能不会导致在接触特征103a和103b之间的充分电性连接。随后的温度升高可改善金属接合、金属接触、金属互连和/或接触结构103a和103b之间的传导性。
替代而言，如果接触特征103a和103b的最高部分是在接合区域106a和106b下面并且在接合之后接触特征103a和103b之间没有机械接触，则温度升高可导致接触特征103a和103b之间的机械连接和/或想要的电性互连。
替代而言，接触特征103a可以是在接合区域106a的表面下面并且接触特征103b可以是在接合区域106b上面，或者接触特征103a可以是在接合区域106a的表面上面并且接触特征103b可以是在接合区域106b下面。接触特征103a和103b在接合区域106a和106b下面的距离差异(或者反之亦然)可以是微小地正值。可替代地，接触特征103a和103b在接合区域106a和106b下面的距离差异可以是标称地为零或略为负值，并且后接接温度的增加可如上面所述地改善金属接合、金属接触、金属互连、接触特征103a和103b之间的传导性。
接触特征103a和103b相对于组件101a和101b的接合区域106a和106b的高度或深度可以利用形成组件101a和101b的表面的抛光制程来控制，举例而言利用化学机械式抛光(CMP)。CMP制程通常可具有多个制程变量，其包括但不限于抛光浆料的类型、浆料添加的速度、抛光垫、抛光垫旋转速率以及抛光压力。CMP制程可进一步取决于构成半导体组件101a和101b的特定非金属和金属、非金属和金属材料的相对抛光速率(较佳是相似的抛光速率，例如镍和硅氧化物)、大小、接触特征103a和103b的间距和颗粒结构以及接合区域106a和106b的非平坦性。亦可使用替代性抛光技术，举例而言无浆料抛光。
接触特征103a和103b相对于接合区域106a和106b的高度或深度亦可以由在半导体组件101a和101b的表面上的接触特征103a和103b周围的材料的轻微干蚀刻而控制，举例而言，使用利用CF4和O2的混合物的电浆或反应性离子蚀刻，以用于包括特定材料的表面，例如硅氧化物、氮化硅或氮氧化硅，较佳的是使得表面粗糙度增加而将显著降低该等表面之间的接合能。替代而言，接触特征103a和103b的高度可藉由在接触特征103a和103b上形成非常薄的金属层来控制。举例而言，无电解电镀一些金属(例如金)可自限(self-limiting)出一非常薄的层，举例而言约5到50nm。此方法可具有以非常薄的非氧化性金属(举例而言，镍上的金)来终止氧化金属的额外优点，以有助于形成电性连接。
因此，在接合顺序内对于诸如图1A至图5C的实施例而言，相对基板的接触结构之间的接触可以发生在相对基板的接合区域之间的接触之前或同时发生。对于诸如图6A至图8C的实施例而言，相对基板的接触结构之间的接触可以发生在相对基板的接合区域之间的接触之后。
长形接触特征的范例
在一些配置中，可能会有挑战性的是将一半导体组件的接触垫与另一半导体组件的对应接触垫对准。一些接触垫(诸如图1A至图1D的金属性的垫12和15)可具有相对小或小型的尺寸和形状，其对传统拾放工具要对准相应的接触垫而言可能是困难的。举例而言，许多拾放工具的对准能力是在2微米至10微米的范围中，或在5微米至10微米的范围中。具有在这些范围之外或附近的主要尺寸的接触垫可能难以使用传统拾放工具来对准，并且可能需要更昴贵的对准设备和/或程序。
在一些配置中，可以提升接触垫的总体尺寸以改善来自两个经接合的半导体组件的相应的垫的对准。然而，提升接触垫的尺寸可能会占用在半导体组件上有价值的占用配置(real estate)。再者，提升接触垫的尺寸亦可能会增加寄生电容，从而增加功率消耗和/或减少半导体组件的带宽。此外，较大的接触垫亦可能会增加在各自半导体组件的经抛光表面上的凹陷效应。所得的大的凹陷效应可能会导致非传导性接合和/或传导区域以非均匀的方式来接合。对于在此处所描述的金属(或传导性掺杂的半导体)和非金属区域的直接接合而言，在基板表面之上的接点高度或在基板表面之下的接点深度可能是重要的。
据此，仍然持续的需要在对应的接触垫之间提供经改善的对准精确度同时在接合期间保持相对地小的特征尺寸。在此处所揭示的各种实施例中，第一半导体组件可包括传导性第一接触结构和相邻第一接触结构的非金属性第一接合区域。第一接触结构可包括传导性第一长形接触特征。第二半导体组件可包括传导性第二接触结构和相邻第二接触结构的非金属性第二接合区域。第二接触结构可包括传导性第二接触特征。第一接合区域可与第二接合区域接触并且直接接合。第一长形接触特征可被定向以与第二接触特征非平行并且在第一长形接触特征和第二接触特征之间的相交点处与所述第二接触特征直接接触。第二接触特征亦可包括长形接触特征。
因为接触特征中的至少一者是长形的，所以当两个半导体组件被组装在一起时可以容许较大的对准偏差。再者，长形接触特征的使用可允许使用相对小的特征尺寸，诸如相对于较大的接触区域有相对窄的线路。举例而言，虽然为了有助于对准接触特征的长度可能远大于宽度，但是长形接触特征的相对细的宽度也将显著地减少由于在抛光期间的凹陷所造成的接触高度或深度变化。再者，窄的特征宽度将有利于在组件上有相对小的寄生电容和相对小的覆盖区。
图9A是根据一实施例的接合半导体结构100的示意性俯视图。图9B是图9A的接合半导体结构的示意性侧边截面图。图9A至图9B的接合结构100可包括一对接合半导体组件101。为了便于说明，该对接合半导体组件101中仅有一者是示于图9A。半导体组件101可包括晶圆、经部分处理的晶圆和/或经切割或部分切割的半导体装置，诸如集成电路晶粒或微机电系统(MEMS)晶粒。每一个半导体组件101可包括传导性接触结构102和相邻接触结构102的非金属性接合区域106。如图9A至图9B中所示，举例而言，接合区域106可围绕或被设置在接触结构102周围。传导性接触结构102可以包括任何合适的传导性材料，包括(例如)金属或传导性掺杂的半导体材料。举例而言，接触结构102可以包括金、铜、钨、镍、银、它们的合金或任何其它合适的材料。非金属性接合区域106可以包括任何合适的非传导性材料，包括(例如)半导体材料或绝缘材料(诸如，聚合物)。举例而言，接合区域106可以包括以下中的至少一者：硅、氧化硅、氮化硅、玻璃、硅上绝缘体、碳化硅、蓝宝石、锗、砷化镓、氮化镓、聚合物、磷化铟或者任何其他合适的非金属性的材料。
接触结构102包括来自相对的或接合成对的半导体组件102的接触特征。第一半导体组件101的接触结构102可包括第一长形接触特征103a，并且第二半导体组件的接触结构102(未例示于图9A)可包括第二长形接触特征103b。在图9A至图9B的实施例中，第一长形接触特征103a和第二长形接触特征103b可以是长度大于宽度的大致上直线形的组件。举例而言，接触特征103a和103b的长度可以是宽度的至少两倍、宽度的至少五倍或是宽度的至少十倍。长度是用以指出在接合平面(例如，两个组件101直接接合所沿着的界面性平面)中每一个特征的较长的维度，而宽度指出在接合平面中较窄的维度。此外，应当理解的是，在其他实施例中长形接触特征可以不是直线形的。相对地，长形接触特征可以是弯曲的(例如)以使得在接合平面中接触特征所经过的路径长度比在接合平面中的接触特征的宽度长。
第一半导体组件101的第一长形接触特征103a可以被设置在下方互连105(诸如直通硅晶穿孔(TSV))上方并且可以与下方互连105至少部分地对准。内部金属化结构(未示出)可将互连105与第一半导体组件101的接触结构102(例如，第一长形接触结构103a)连接。举例而言，内部金属化结构或迹线可以在半导体组件101中被横向地和/或垂直地设置，以在互连105和接触结构102之间提供通信。再者，在一些实施例中，传导性阻障结构(未示出)可以被提供在接触结构102和互连105或中间的内部金属化结构之间。举例而言，在一些实施例中，传导性阻障结构可以内衬镶嵌结构的沟槽。额外的金属化结构亦可以被提供在半导体组件101的表面处或附近，以横向地绕送讯号跨越该组件的宽度。如图9A中所示，互连105可以隔开一段互连间距p，并且可用以将接触结构102电性连接至与较大的电子系统通信的外部引线。间距p可以是任何合适的距离，例如在0.1微米至500微米的范围中、在0.1微米至100微米的范围中、在0.1微米至50微米的范围中、在1微米至50微米的范围中或在10微米至50微米的范围中。
为了接合两个半导体组件，如上所解释，半导体组件101可以相对于彼此定向，以使得相对的组件101中的一者的第一长形接触特征103a与相对的组件101中的另一者的第二长形接触特征103b非平行。两个半导体组件101可以被接在一起，以使得至少第一和第二非金属性接合区域106是相接触的。如同上面所解释的，接合区域106的表面可被加以制备，以使得当两个半导体组件101的接合区域106接触时，非金属性接合区域106彼此直接接合以形成化学接合而不具有中间的黏着剂。因此，被设置在第一接触特征103a的第一侧上的非金属性接合区域106的部分可以与被设置在第二接触特征103b的两侧上的非金属性接合区域106的对应部分直接接合。
举例而言，在各种实施例中，接合区域106可被抛光并且接着被极细微地蚀刻以产生平滑的接合表面。在各种实施例中，经蚀刻的表面可以用含氮的物质来终止，举例而言藉由将经蚀刻的表面暴露于含氮的电浆(诸如氮气)或将经蚀刻的表面浸渍于含氮的溶液中(诸如含氨的溶液)。在其他实施例中，其他键结物质(terminating species)可有助于非金属性接合区域106a和106b的化学共价结合。在各种实施例中，接合区域106可以在室温下直接接合在一起。接合区域106亦可在不需对半导体组件101施加外部压力的情况下直接接合在一起。
第一长形接触特征103a和第二长形接触特征103b可以在接触的相交点104处彼此相交。如同上面关于图1A至图8C所解释的实施例，长形接触特征103a和103b可彼此直接接合，以在特征103a和103b之间提供电性通信。举例而言，在与图1A至图5C的实施例相似的实施例中，在接点突出的地方接点之间非金属表面(例如，半导体或绝缘体)的接合产生可将来自相对半导体组件的接触特征103a和103b接合的内部压力，其可利用或可不利用额外的热。在与图8A至图8C的实施例相似的实施例中，在接合区域106a和106b彼此直接接合之后，半导体组件101可以被加热以使得长形接触特征103a和103b由于相对于外围材料的热膨胀系数(CTE)差异的缘故而朝彼此扩张，而产生使特征103a和103b在相交点104处彼此直接接合的内部压力。半导体组件101可以在75℃至350℃的范围中被加热，或更具体地说，在100℃至250℃的范围中被加热。
有利的是，提供至少一个长形接触特征103a和/或103b可以显著地增加将传导性接触结构102直接接合在一起的对准容限。因为在接合平面中接触特征103a和/或103b中的至少一者由于路径长度大于其宽度而是长形的，所以两个半导体组件101可以有相对大的未对准，而仍然有利于在接触特征103a和103b之间的直接接合。举例而言，在使用较小的或非长形的接触特征的接合结构中，习知拾放机械的对准容限可以是在1微米至5微米的范围中，或是在1微米至10微米的范围中。
相比之下，对于40微米的互连间距p而言，长形接触特征103a和103b的长度l可以是约20微米，或是互连间距p的约一半间距。因为每一个接触特征103a和103b的长度l相对于互连间距p而言是大的，所以拾放机械是更容易在两个接触特征103a和103b之间实现重叠或相交，而导致较大的对准偏差容限。举例而言，在40微米的互连间距的范例中，对准偏差容限(亦即，半导体组件101可相对于彼此横向地未对准的程度)可以是在5微米至10微米的范围中。
应该理解的是，在其他实施例中，可以使用其他合适的长度l。举例而言，在图9A至图9B中所示的长形接触特征103a和103b的长度l可以是在0.05微米至500微米的范围中、在0.05微米至100微米的范围中、在0.05微米至50微米的范围中、在0.1微米至50微米的范围中、在1微米至50微米的范围中、在5微米至50微米的范围中、在10微米至50微米的范围中、在10微米至40微米的范围中或在15微米至30微米的范围中。接触特征103a和103b的宽度W可以是足够小以减少寄生电容并且在半导体组件101上保持小的覆盖区。举例而言，接触特征103a的宽度可以是在0.01微米至10微米的范围中、在0.01微米至5微米的范围中、在0.1微米至10微米的范围中、在0.1微米至5微米的范围中、在0.5微米至5微米的范围中、在0.5微米至4微米的范围中、在1微米至5微米的范围中、在1微米至3.5微米的范围中或在1.5微米至3微米的范围中。
虽然在图9A至图9B中所示的两个接触特征103a和103b被说明且描述为直线形的接触特征，应该理解的是，在其他实施例中长形接触特征可反而包括弯曲的形状。举例而言，应该理解的是，第一半导体组件可包括弯曲的接触特征，并且第二半导体组件可包括直线形接触特征、经二维地图案化的接触特征(例如格栅接触特征)、弯曲形的接触特征中的任一者。因此，对准偏差可被减少而将凹陷最小化(以及随后接点高度/深度的不均匀性问题)，只要路径长度(例如，不管是直线形路径长度或弯曲形路径长度)是比接触特征的宽度足够地更长。额外的长形接触特征是在下面结合图12A至图12H来说明。
接触特征103a和103b可包括延伸在接合区域106上面的突出接点。举例而言，接触特征103a和103b可包括与图1A至图1D的实施例中所示的金属性的垫12和15类似的突出接点。在其他实施例中，接触特征103a和103b可包括凹陷接点，其中接触特征103a和103b是最初设置在接合区域106之下并且在接合区域106直接接合在一起(例如与图6A至图6C和图8A至图8C中所示的类似)之后接触。在另外的其他实施例中，接触特征103a或103b中的一者可包括突出接点，并且接触特征103a或103b中的另一者可包括凹陷接点(例如与图7A至图7C中所示的类似)。
图10是根据另一实施例的接合半导体结构100的示意性俯视图。除非另外说明，在图10中所示的参考数字表示与图9A至图9B中所引用的构件大致上类似的构件。举例而言，两个接合半导体组件101每一者可包括对应的传导性接触结构102和相邻接触结构102所设置的非金属性接合区域106。传导性接触结构102可包括长形接触特征103a和103b。然而，不同于图9A至图9B的实施例，在图10的实施例中，接触特征103a和103b可包括经二维地图案化的接触特征，例如界定二维的长形接触特征的图案用以改善接合结构的对准的多个相交的传导区段。相交的传导区段可以是弯曲、直线形、多边形、圆形、椭圆形。举例而言，在图10中，对应的正交格栅图案可被设置在半导体组件101上。相比之下，图12A至图12H说明额外的实施例，其中长形接触特征103a和103b的图案可界定有助于改善接合结构的旋转对准的其他二维形状。
图10的接触特征103a和103b的格栅图案可包括多个相交线路。虽然图10的格栅图案的相交线路被示为彼此垂直，但是在其他实施例中格栅图案的相交线路可反而在非垂直的角度下被设置。再者，虽然在图10中格栅图案中的多个线路的每一者是直线形的，但是在其他实施例中格栅图案中的线路可反而是弯曲的。举例而言，请参考图12A至图12H的图案。
格栅图案的长度l可具有与图9A至图9B的实施例的线路相同的长度l。举例而言，格栅图案的长度l可以是在0.05微米至500微米的范围中、在0.05微米至100微米的范围中、在0.05微米至50微米的范围中、在0.1微米至50微米的范围中、在1微米至50微米的范围中、在5微米至50微米的范围中、在10微米至50微米的范围中、在10微米至40微米的范围中或在15微米至30微米的范围中。接触特征103a和103b的格栅图案中的每一个线路的宽度可以是足够小以避免可能会妨碍横跨半导体组件101的牢靠的金属接合的凹陷问题。举例而言，接触特征103a的格栅图案中的多个线路的宽度可以是在0.01微米至10微米的范围中、在0.01微米至5微米的范围中、在0.1微米至10微米的范围中、在0.1微米至5微米的范围中、在0.5微米至5微米的范围中、在0.5微米至4微米的范围中、在1微米至5微米的范围中、在1微米至3.5微米的范围中或在1.5微米至3微米的范围中。格栅图案的相邻线路之间的分开距离d可以是任何合适的距离，例如在0.01微米至100微米的范围中、在0.01微米至50微米的范围中、在0.1微米至50微米的范围中、在0.5微米至50微米的范围中、在0.5微米至10微米的范围中、在0.5微米至5微米的范围中或在1微米至5微米的范围中。
有利的是，使用格栅图案作为接触特征103a和103b可使相交区域104具有多个电性、直接接合的接点。因为格栅图案包括多个相交线路，所以图10的实施例可产生电性接点同时容许大量的对准偏差。再者，如与图9A至图9B的实施例对比，在格栅图案内产生多个电性连接可允许较小的电流密度，其至少是因为有更大的接触面积。举例而言，在图10的实施例中，接点(例如接触特征103a和103b所直接接合的面积)的总表面积可以是在10μm2至30μm2的范围中、或在5μm2至35μm2的范围中、或更特别地在10μm2至25μm2的范围中。每一个接点的电流是分布于具有较大的总体接触表面的较大量的连接，从而减少给定电流的电流密度。
在图10中所示的格栅图案包括m×n的单元数组，其中m＝n＝4。然而应该理解的是，格栅图案可包括任何数量的单元，并且m和n可以是偶数或奇数。举例而言，在替代性格栅图案中，m×n的单元数组可包括奇数个单元，例如m＝n＝1,3,5等。在此些实施例中，使用奇数个单元可允许在给定对准偏差下有固定的交错面积，以提供最小的接触结构面积(举例而言，当每一个单元的范围接近对准精确度时)。格栅图案的线路可以比格栅线路之间的间隔要窄，以帮助减少凹陷并提高非金属性部分的接合能。可重复以构成格栅的单元的大小或范围可以是接近用以对准并将接合表面放置在一起的(多个)对准工具的3sigma对准精确度，以使得至少两个连接点的面积是由在m＝1时相对接合表面上的线路宽度的乘积所给定。在m＝1时可增加连接点的数量。互连面积可以藉由增加连接点的数量或增加在格栅中线路的宽度而增加。
在习知接合配置中，分开的金属性的层(例如铝质垫)可在半导体组件的顶部表面附近处产生，以在两个接合半导体组件101a和101b之间电性通信。再者，金属性接触垫可能是相对地大以接纳在相对半导体组件上的对应接点或凸块，其可能会增加寄生电容。在此些习知配置中，垂直连接(诸如通孔或TSV)可从接触垫延伸至(多个)半导体组件中以与对应迹线连接而用于讯号绕送。因此，在此些配置中接触垫是相对地大，并且可能会使用多个迹线层以确保讯号是被适当地绕送。垂直连接占据本来可用于横向绕送的层。
图11A至图11C说明使用长形接触特征103a和103b以提供与对应的下方迹线120的电性通信，以供可靠地绕送电性讯号通过半导体组件101a和101b。特别是，图11A是具有多个长形接触特征103a的第一半导体组件101a的示意性平面图，多个长形接触特征103a与对应的下方迹线连接。图11B是第一半导体组件101a的示范性接触特征103a和相关联的下方迹线120a的示意性平面图，亦示出被对准以在交叉指向上与第一半导体组件的接触特征接触的第二半导体组件的接触特征。图11C是两个接合半导体组件101a和101b的示意性侧边截面图，两个接合半导体组件101a和101b在每一个组件101a和101b的交叉的接触特征103a和103b之间具有直接连接。
如图11A中所示，第一半导体组件101a可包括多个接触结构102，其包括在第一半导体组件101a的顶部表面处暴露的长形接触特征103a。如同图8A至图10的实施例，非金属性接合区域106可被设置以相邻或围绕接触特征103a，并且非金属性接合区域106可覆盖迹线120a。每一个接触特征103a与被设置在接触特征103a之下的对应迹线120a电性连接并较佳的是从对应迹线120a延伸。因此，图11A中所示的迹线120a可嵌入于半导体组件101a内而在接触特征103a之下。迹线120a可以彼此凸出(jog)或偏移以便能够可靠地绕送每一个接触特征103a的迹线而不会有干扰。虽然为了方便说明图11A将接触特征103a示为比下方迹线120a要宽，但是从以下图11B和图11C应该理解的是，事实上接触特征可具有与下方迹线120a相同的宽度。举例而言，在一些配置中，迹线120a的宽度和接触特征103a的宽度可以是在0.5微米至5微米的范围中、在1微米至3微米的范围中，例如约2微米。
如图11B至图11C中所示，范例性接触特征103a可被设置在范例性接触特征103a所连接的对应迹线120a的顶部上。长形接触特征103a可仅沿着迹线120a的部分延伸并且可选择长度l和宽度w以确保第一半导体组件101a的接触特征103a与第二半导体组件101b的对应接触特征103b相交并接触。第二半导体组件101b的接触特征103b是示于图11B中，以便说明当被对准以接触时它们的相对定向。
在图11A至图11C中所示的长形接触特征103a和103b的长度l可以是在0.05微米至500微米的范围中、在0.05微米至100微米的范围中、在0.05微米至50微米的范围中、在0.1微米至50微米的范围中、在1微米至50微米的范围中、在5微米至50微米的范围中、在10微米至50微米的范围中、在10微米至40微米的范围中或在15微米至30微米的范围中。接触特征103a和103b的宽度W可以是足够小以避免凹陷的问题、减少寄生电容以及在半导体组件101上保持小的覆盖区。举例而言，接触特征103a的宽度可以是在0.01微米至10微米的范围中、在0.01微米至5微米的范围中、在0.1微米至10微米的范围中、在0.1微米至5微米的范围中、在0.5微米至5微米的范围中、在0.5微米至4微米的范围中、在1微米至5微米的范围中、在1微米至3.5微米的范围中或在1.5微米至3微米的范围中。接触特征的宽度可以是与它们所延伸的迹线102a的宽度相同、在±10％内，更特别地在±5％内。
如图11C中所示，来自第一半导体组件101a的接触特征103a可在相交点区域104处与来自第二半导体组件101b的对应接触特征103b接触并接合。在图11C中所示的范例性接触特征103a可仅设置在与该接触特征103a相关的迹线120a上方并且迹线120a电性接触。在相同的金属化层(metallization level)内，与其他接触特征(未示出)相关的迹线120a可延伸以与所说明的接触特征103a相关的迹线120a大致上平行且不相交。类似地，第二半导体组件101b的范例性接触特征103b可延伸在仅与接触特征103b相关的迹线120b上方并且迹线120b电性接触。如图11C中所示，接触特征103b和其迹线120b可相对于接触特征103a和其迹线120a非平行地延伸(例如，大致上垂直)。虽然迹线120B在图11C中被解释为横向地延伸(例如与迹线120a非平行)，但是在其他配置中，第二组件101b的接触特征103b可与其他类型的内部绕线特征连接，包括垂直和/或水平的绕线特征或在任何其他方向上延伸的绕线特征。再者，在一些配置中，第一半导体组件101a的绕线特征可以与第二半导体组件101b的绕线特征不同。举例而言，迹线120a可以仅在第一组件101a中形成，并且其他类型的绕线特征可在第二组件101b中形成。
有利的是，在图11A至图11C中所说明的实施例可允许使用更小的接触特征，其可减少寄生电容同时提升接合结构的对准精确度。再者，接触特征103a和103b相对于对应迹线120a和120b的定位可允许有效地绕送电性讯号而不需要提供多个绕送和/或接触层。由于所说明的接触特征103a从下方的横向迹线直接地延伸，金属化层是完全用于横向绕送而不需要单独用于垂直连接(诸如通孔)的中间的层间介电质(intervening interleveldielectric，ILD)。如同图9A至图10的实施例，半导体组件101a和101b可包括任何合适类型的半导体组件。举例而言，在一实施例中，第一半导体组件101a可包括中介件并且第二半导体组件101b可包括整合式装置晶粒。在其他实施例中，半导体组件101a和101b两者皆可包括整合式装置晶粒。
图12A至图12H是根据各种其他实施例的传导性接触结构102的示意性俯视图。除非另外说明，在图12A至图12H中所示的参考数字表示与图8A至图11C中所引用的构件大致上类似的构件。举例而言，半导体组件(未示出)可包括对应的传导性接触结构102和相邻接触结构102所设置的非金属性接合区域106。传导性接触结构102可包括长形接触特征103a和103b。在图12A至图12H，仅示出与对应的半导体组件相关的一个接触特征103a。如同图10的实施例，接触特征103a和103b可包括经二维地图案化的接触特征，例如界定二维的长形接触特征的图案用以改善接合结构的对准的多个相交的传导区段。举例而言，图12A至图12H中的接触特征103a可包括由绕着中心区域设置的长形区段所组成的接合结构。在图12A至图12H中所示的接触特征103a界定可有助于改善接合结构的旋转对准的长征接触特征的图案。举例而言，在图12A至图12H中，接触结构102可包括旋转对称、或接近对称的长形接触特征103a。因此，图12A至图12H中的长形接触特征103a可容许线性对准偏差，因为接触结构102包括多个长形传导区段。长形接触特征103A亦可容许旋转对准偏差，因为两个旋转地未对准的接触结构102中的向外延伸的区段122可在两个经接合的半导体组件之间提供足够的电性连接。
接触结构102的图案可以包括任何合适的形状。举例而言，如图12A中所示，接触结构102可以包括挠着中心区域C设置的多边形边界B(例如，四边形、矩形或正方形边界)，中心区域C可以在或可以不在接触结构102的几何中心。向外延伸的区段122可从中心区域C向外径向延伸，以便减少转动的和横向的对准偏差。如同图12A，图12B的接触结构102可以包括挠着中心区域C设置的多边形边界B。此外，多个横向连接件124可以将向外延伸的区段122互连，其可进一步减少对准偏差。
图12C至图12D说明具有多边形边界B的接触结构102，多边形边界B包括五边形边界。在图12D中，横向连接件124可以将向外延伸的区段122互连。图12E至图12F说明具有多边形边界B的接触结构102，多边形边界B包括六边形边界。在图12F中，横向连接件124可以将向外延伸的区段122互连。虽然图12A至图12F描绘具有四边形、五边形和六边形轮廓的多边形边界，但是应该理解的是可以使用任何合适的多边形边界。再者，如图12G至图12H中所示，接触结构102亦可包括弯曲的接触特征103a，例如圆形或椭圆形边界B。图12F说明将向外延伸的区段120连接的横向连接件124。
因此，在此处所揭示的长形接触特征103a和103b可以界定任何合适的图案。有利的是，接触特征103a和103b可以改善横向的和/或转动的对准偏差，同时在直接接合的半导体组件之间提供电性互连。
有可能的是按照上面的教示对于本发明做出许多修改和变化。因此应该理解的是，在所附权利要求书的范畴内，可用与在此处所特别描述不同的方式实施本发明。

Claims (20)

1.一种接合结构，其包括：
第一半导体组件，其包括传导性第一接触结构和相邻所述第一接触结构的非金属性第一接合区域，所述第一接触结构包括传导性第一长形接触特征；以及
第二半导体组件，其包括传导性第二接触结构和相邻所述第二接触结构的非金属性第二接合区域，所述第二接触结构包括传导性第二接触特征，
其中所述第一接合区域与所述第二接合区域接触并且直接接合，以及
其中所述第一长形接触特征被定向以与所述第二接触特征非平行，并且在所述第一长形接触特征和所述第二接触特征之间的相交点处与所述第二接触特征直接接触。
2.如权利要求1所述的接合结构，其中所述第一长形接触特征在所述相交点处与所述第二接触特征直接接合。
3.如权利要求1所述的接合结构，其中所述第二接触特征包括长形接触特征。
4.如权利要求3所述的接合结构，其中所述第一长形接触特征的第一侧上的氧化物与所述第二长形接触特征的第一侧与第二侧上的对应氧化物区域接合。
5.如权利要求1所述的接合结构，其中所述第一接触结构包括格栅图案形式的多个线路。
6.如权利要求1所述的接合结构，其中所述第一接触结构界定了绕着中心区域设置的边界和从所述中心区域向外延伸的多个传导区段。
7.如权利要求6所述的接合结构，其进一步包括多个横向连接件，其连接所述多个传导区段。
8.如权利要求7所述的接合结构，其中所述边界包括多边形或饼图案。
9.如权利要求1所述的接合结构，其中所述第一长形接触特征具有长度与宽度，所述长度是所述宽度的至少两倍。
10.如权利要求9所述的接合结构，其中所述第一长形接触特征的所述长度是所述宽度的至少五倍。
11.如权利要求1所述的接合结构，其中所述第一接触结构和所述第二接触结构中的至少一者包括金属和传导性掺杂的半导体材料中的至少一者。
12.如权利要求1所述的接合结构，其进一步包括直通硅晶穿孔(TSV)，其被设置在所述第一半导体组件内而在所述第一长形接触特征和所述第二接触特征的所述相交点之下。
13.如权利要求12所述的接合结构，其进一步括一或多个传导迹线，其被设置在所述TSV和所述第一长形接触特征之间且电性连接所述TSV与所述第一长形接触特征。
14.如权利要求1所述的接合结构，其中所述第一长形接触特征和所述第二接触特征中的至少一者是弯曲形的。
15.一种接合方法，其包括：
提供第一半导体组件，其包括传导性第一接触结构和相邻所述第一接触结构的非金属性第一接合区域，所述第一接触结构包括传导性第一长形接触特征；
提供第二半导体组件，其包括传导性第二接触结构和相邻所述第二接触结构的非金属性第二接合区域，所述第二接触结构包括传导性第二接触特征；
定向并且组装所述第一半导体组件和所述第二半导体组件，使得所述第一长形接触特征和所述第二接触特征是非平行的；
直接接合所述第一接合区域与所述第二接合区域；以及
在所述第一长形接触特征和所述第二接触特征之间的相交点处，直接接合所述第一长形接触特征和所述第二接触特征。
16.如权利要求15所述的方法，其中直接接合所述第一接合区域与所述第二接合区域包括在所述第一长形接触特征和所述第二接触特征之间留下初始间隙，并且加热所述第一半导体组件和所述第二半导体组件以使所述第一长形接触特征直接接触所述第二长形接触特征。
17.如权利要求15所述的方法，其进一步包括在直接接触之前，将所述第一长形接触特征直接形成在对应迹在线，所述迹线沿着所述第一长形接触特征的长度对准。
18.一种半导体组件，其包括：
基板，其包括一或多层非金属性材料；
多个传导迹线，其被嵌入在所述基板中，所述迹线横向地延伸穿过所述基板以横向地绕送电性讯号；以及
长形接触特征，其沿着所述多个迹线中的第一迹线延伸并且直接接触所述第一迹线，所述接触特征在所述基板的顶部表面处暴露。
19.如权利要求18所述的半导体组件，其中所述接触特征沿着所述第一迹线的长度的部分延伸。
20.如权利要求18所述的半导体组件，其中所述长形接触特征覆盖所述第一迹线的第一部分，并且其中绝缘材料覆盖所述第一迹线的第二部分。
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US20190244899A1 (en) 2019-08-08
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US20180204798A1 (en) 2018-07-19
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US10269708B2 (en) 2019-04-23

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