TW201724394A - 預清理副產物昇華之反應器系統及其方法 - Google Patents
預清理副產物昇華之反應器系統及其方法 Download PDFInfo
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- TW201724394A TW201724394A TW105117112A TW105117112A TW201724394A TW 201724394 A TW201724394 A TW 201724394A TW 105117112 A TW105117112 A TW 105117112A TW 105117112 A TW105117112 A TW 105117112A TW 201724394 A TW201724394 A TW 201724394A
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- Prior art keywords
- wafer
- tray
- temperature
- heating element
- wafer tray
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- 230000002411 adverse Effects 0.000 description 1
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- 229910052786 argon Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
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- 125000006850 spacer group Chemical group 0.000 description 1
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Classifications
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- C—CHEMISTRY; METALLURGY
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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- C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
- C23C16/4582—Rigid and flat substrates, e.g. plates or discs
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
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- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
- H01L21/6773—Conveying cassettes, containers or carriers
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B3/00—Ohmic-resistance heating
- H05B3/20—Heating elements having extended surface area substantially in a two-dimensional plane, e.g. plate-heater
- H05B3/22—Heating elements having extended surface area substantially in a two-dimensional plane, e.g. plate-heater non-flexible
- H05B3/26—Heating elements having extended surface area substantially in a two-dimensional plane, e.g. plate-heater non-flexible heating conductor mounted on insulating base
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B6/00—Heating by electric, magnetic or electromagnetic fields
- H05B6/02—Induction heating
- H05B6/10—Induction heating apparatus, other than furnaces, for specific applications
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Abstract
本發明提供了一種反應器系統及相關方法,其包括晶片托盤中的加熱元件。加熱元件用於加熱晶片托盤及位於反應槽室組件內的晶片托盤上的基板或晶片,以及用於引起晶片的自然氧化物之昇華。
Description
本發明技術領域涉及積體電路的製造,特別地涉及用於預清洗晶片或基板表面的方法及裝置。
積體電路製造通常涉及在基板(也稱為「晶片」)表面上形成一個或多個材料層。這些材料層包括例如單晶,多晶或其它非晶形材料層。材料層的形成可使用各種薄膜沉積技術來實現,包括各種物理沉積技術,例如物理濺射或化學沉積技術,例如濺射。化學氣相沉積(CVD),原子層沉積或外延沉積。例如,可使用外延沉積處理過程,例如用於形成單晶半導體材料(例如,單晶矽),在基板表面上形成單晶材料。
晶片表面上中間材料(例如,天然氧化物層,例如矽晶片上的氧化矽材料層)的存在可能干擾在晶片表面上形成所期望的材料層。例如,中間材料可能導致在期望材料層的結構中導致相當數量缺陷,或者可能不利地影響所期望材料層的電性能。在一些實施例中,由於在積體電路製造處理過程期間晶片暴露於氧氣例如,在製造系統之間的基板轉移期間暴露於大氣空氣中,例如天然氧化物材料的中間材料可形成在晶片表面上,或製造系統內殘餘氧化劑。因此,從晶片去除自然氧化物的製造技術及系統是需
要的,以便後續在晶片表面上沉積。
在本發明一項中,反應器系統可包括界定出內部槽室的反應室組件;在內部槽室內的基座;位於基座上並適於承載晶片的晶片托盤;以及晶片托盤中的加熱元件,其適於加熱晶片托盤以將晶片加熱至昇華溫度。
在本發明另一項中,一種方法可包括以下步驟:將晶片放置在反應室組件內的晶片托盤上;以及對晶片托盤內的加熱元件供電,以將晶片托盤的溫度從第一溫度升高到第二溫度,以使晶片上的氧化物材料在反應室組件內產生昇華。
在本發明另一項中,反應室系統可包括界定出內部槽室的反應室組件;在內部槽室內的晶片托盤;及由晶片托盤承載的至少一個加熱元件;其中除了由晶片托盤承載的至少一個加熱元件之外,內部槽室中沒有加熱元件。
10‧‧‧反應器系統
12‧‧‧噴頭
14‧‧‧槽室
14a‧‧‧上部槽室區域
14b‧‧‧中間槽室區域
14c‧‧‧下部槽室區域
16‧‧‧晶片托盤
17‧‧‧晶片
18‧‧‧基座
20‧‧‧頂壁
22‧‧‧底部表面
24‧‧‧通道
26‧‧‧歧管
28‧‧‧洞孔
30‧‧‧頂部表面
32‧‧‧底部表面
34‧‧‧反應槽室組件
36‧‧‧側壁
40‧‧‧開口
42‧‧‧底壁
44‧‧‧出口
42‧‧‧底壁
46‧‧‧頂部表面
48‧‧‧凹部
50‧‧‧頂部表面
52,54‧‧‧感測器
56‧‧‧通道
58‧‧‧間隙
60‧‧‧外周邊
62‧‧‧頂部表面
64‧‧‧底部表面
66‧‧‧加熱元件
200‧‧‧方法
202‧‧‧將晶片放置於在晶片托盤上
204‧‧‧在晶片托盤內對加熱元件供電
206‧‧‧提高晶片托盤的溫度以轉移熱量至晶片使得晶片達到
昇華溫度,在該溫度下在內部槽室內晶片上氧化之材料經由昇華產生相變化由固態變為氣體
在下面的說明中說明了範例性實施例,其在附圖中顯示出以及在申請專利範圍中特別清楚地指出及說明。
圖1是用於製造積體電路的反應器系統之橫截面圖。
圖2是用於昇華反應器系統內晶片上的氧化物材料方法之流程圖。
在整個附圖中,類似的附圖標記表示相類似的元件。
圖1顯示出了反應器系統10,其包括反應槽室組件34。組件34包括頂壁20,連接到頂壁20的環形側壁36以及連接到側壁36的底壁42。反應器系統10/組件34可包括噴頭12,用於將處理氣體由組件34界定出的內部反應槽室14中導引到特別是進入待處理的晶片17。內部槽室14可包括上部槽室區域區域14a,中間或中間槽室區域或區域14b及下部槽室區域14c。系統10可包括設置在內部槽室14中的晶片托盤16及基座18。晶片托盤16可位於基座18上或由基座18承載,並且可被配置為在其上面承載晶片17。
噴頭12可包括上部剛性壁體或氣體通道板20,其具有面向上的頂部表面及面向下的底部表面22,其尺寸類似於頂部表面。底部表面22界定出內部槽室14的上部區域14a之一部分。氣體入口連接埠或通道24可穿過從頂部表面延伸到底部表面22的壁體或構件20而形成。通道24可構造成允許氣體從槽室組件34外部的氣體源通過而流入上部槽室區域14a。上部槽室區域14a界定出在底部表面22及噴頭12的多通道歧管26面向上頂部表面30之
間。歧管26界定出從頂部表面30延伸到底部表面32的多個通道或洞孔28使得洞孔28與上部槽室區域14a及中間槽室區域14b流體連通,由上部槽室區域14a及中間槽室區域14b經由洞孔28彼此流體連通。頂部表面30可部分地界定出上部槽室而底部表面32可部分地界定出槽室14的中間槽室區域14b。
噴頭12設置在側壁36頂上及可移除地安裝在側壁36上,側壁36可為圓柱形或圓形側壁。密封件38可密封地接合噴頭12及側壁36,以在噴頭12及側壁36之間形成氣封或氣密性密封。側壁36可界定出徑向(例如從左到右)通道或開口40由側壁36外表面延伸到側壁36的內表面,使得通道40與內部槽室14及槽室組件34外部的大氣流體連通。底壁42可鄰近側壁36的底部固定到側壁36,並且界定出多個出口44,其可允許容納在槽室14內的氣體通過而離開。底壁42的頂部表面46可部分地界定出下部槽室區域14c。
基座18可由金屬(例如,鋁合金),石墨或另一種合適的材料形成。基座18可被配置為接收並保持由晶片托盤16承載的晶片17,從而在處理期間例如在昇華過程期間將晶片17保持在適當位置。基座18包括從基座18的頂部表面50向下延伸短距離的凹部48。頂部表面50可是圓形環形向上表面,並且當從上方觀察時,凹部48可是圓形的。凹部48可具有等於或類似於托盤16垂直高度的垂直深度,其可容納在凹部48中。晶片托盤16及凹部48的尺寸可使得當基板或晶片17放置在晶片托盤16上時,基板或晶片17的頂部表面可與基座18的頂部表面50實質上為共面的。這種構造可促進或允許氣體或氣體實質上為層流及/或實質上均勻的速度穿過基板17的頂部表面,因為氣體或氣體通過開口40移動進入槽室14中。基座18還可包括第一溫度測量裝置或感測器52及第二溫度測量裝置或感測器54。基座可進一步
界定出多個冷卻通道56,其配置成當晶片托盤16內之加熱元件加熱時將基座18保持在期望溫度。冷卻通道56可與例如水的冷卻液源流體連通以及泵運以移動水或其它冷卻液體移動通過冷卻通道56。
基座18可固定地附接到底壁42或以其它方式設置在槽室14中,使得在槽室組件34中處理晶片17的各個步驟期間基座18並不相對於內部槽室14移動。間隙或通道58可在其間延伸以及提供中間槽室區域14b及下部槽室區域14c之間的流體連通。間隙58可是環形間隙,其可四週全向地延伸圍繞著基座18的外周邊60於側壁36及基座外周邊60之間。此外,通道58的寬度可變化,以提供橫跨頂部表面50及晶片托盤16的頂部,如本領域所理解的。例如,間隙58可在靠近真空源的區域中包括窄的寬度,並且包括遠離真空源相當寬的寬度。間隙58寬度可在大於0公釐(mm)到大約4mm,或從大約0.5mm或1.0mm到大約3.0或4.0mm的範圍內,並且大約是2.0mm。間隙58可從頂部到底部(頂部表面50到基座18的底部表面)漸縮,使得間隙58在其頂部比在其底部寬或在其頂部比在其底部窄。
晶片托盤16可具有相對低的質量,這允許其快速加熱。晶片托盤的質量可在從約0.4或0.5千克至約1.0,1.1,1.2,1.3,1.4或1.5千克的範圍內。晶片托盤16具有面向上的頂部表面62及面向下的底部表面64。當晶片托盤16位於凹部48內時,底部表面64可接觸基座18面向上的表面。頂部表面62可實質上與頂部表面50共面之晶片托盤16具有實質上圓形的外周邊,其從頂部表面62延伸到底部表面64並且界定出托盤16的外徑,在一個實施例中,托盤16的外徑可在約280,290或300mm的範圍內,約310,320或330mm,並且可約為305mm。晶片托盤16可在其中界定出凹部。晶片托盤16可由相對非
反應性材料形成,例如非金屬材料。適於晶片托盤16的一些材料可包括一種或多種氧化鋁,氮化硼及碳化矽。晶片托盤16可包括這些材料,由這些材料實質地組成或由這些材料組成。在一個特定實施例中,晶片托盤16實質上由碳化矽(SiC)組成。晶片托盤16還可包括例如氮化鋁(AlN)或氮化硼(BN)的材料,由其實質地組成或由其組成。
晶片托盤16的厚度可根據要在其上面昇華的晶片17尺寸而變化。作為範例,晶片托盤16可具有界定出在頂部表面62及底部表面64之間的厚度(當托盤16實質上為水平時,其為垂直厚度)。該厚度例如為不大於5.0mm,可在從約1.0mm至約5.0mm,或從約2.0mm至約4.5mm,或從約3.0mm至約4.0mm厚,以及為約3.5mm厚的範圍內。如圖1所示,晶片托盤16頂部表面62可與基座18頂部表面50位於相同的高度,使得晶片托盤16的厚度可等於凹槽48的垂直深度,托盤16可位於或嵌套在其內側。因此,基座18的凹部48具有垂直深度與上面所標示晶片托盤16厚度在相同範圍內。
可在晶片托盤16中形成凹槽,其從頂部表面62向下延伸並且可被配置成在昇華處理期間承受以及保持晶片17在其中。形成在晶片托盤16中的凹部可實質上具有等於晶片17的高度或垂直厚度的垂直深度,儘管這可變化,並且晶片17可些微地延伸到晶片托盤16的頂部表面62上方。界定出晶片托盤16中該凹部的底部(或晶片托盤16面向上的表面,晶片17的底部表面位於其上面)可完全地或可包括相對平滑的部分,例如具有粗糙度平均值(Ra)為0.4μm或更小,以減輕反應物與基板底部表面反應。形成在頂部表面62中的凹槽可成形為使得凹槽的周邊可實質上類似於晶片17的周邊。例如,當從上方觀察時,當晶片17可是實質上為圓柱形或圓形時,形成在頂
部表面62中的凹部從上方觀察時也可是大致為圓柱形或圓形,或者具有淺圓柱形狀,其具有高達實質上等於或略微小於晶片17的高度,並且具有直徑略大於晶片。晶片托盤16可包括形成在其中的洞孔,其從頂部表面62延伸到底部表面64,適於容納通過其中的推移針銷,而允許擱置在基座16頂上以及接合或接觸晶片托盤16向上推移與晶片托盤16的接合。
至少一個加熱元件66可設置在晶片托盤16內或在頂部表面62及底部表面64之間嵌入晶片托盤16中。加熱元件66可以是鎢為主的電阻加熱元件,其由專用電源供電,該專用電源被配置為加熱到通常不超過約700℃。雖然加熱元件66為約700℃或另一溫度,但晶片17及晶片托盤16可能不會達到這樣的溫度並且可能實質上為較小。例如如果晶片17上的氧化物層昇華發生在或約為100℃昇華溫度,則加熱元件66可位於大於昇華溫度的溫度,例如約400℃。因此,雖然元件66可在晶片托盤16內為400℃,但是溫度可從元件66經由晶片托盤16傳導到晶片17以及經由晶片17以提高晶片17或晶片17的表面溫度升高到昇華溫度或約為100℃附近。傳移到晶片17的熱量取決於槽室環境(壓力,氣體型式,氣體流量)。昇華相變可能發生,甚至於加熱元件可能比昇華溫度更高。
雖然加熱元件66可包括鎢(W),由鎢(W)實質地組成或由鎢(W)組成,但加熱元件66可優先地包括鉬(Mo),由實質上鉬(Mo)組成或者由鉬(Mo)組成,可包括這兩種元素,或可由另一種合適的材料形成。加熱器元件66可埋嵌在石墨中,並且埋嵌石墨的元件塗覆SiC,AlN或BN。晶片托盤16內的加熱元件66優先地具有其自己的專用電源及熱電偶。此外,加熱元件66可被配置成以非常快的速率加熱或躍昇溫度。例如,元件66可以約50℃/秒
至約200℃/秒或約75℃/秒至約150℃/秒的範圍內,或者175℃/秒,並且可約為100℃/秒的溫度躍昇速率加熱。
加熱元件66因此可位於晶片托盤16內而不是位於另一位置,例如位於基座18內。形成在基座18的頂部表面50中的凹部48可具有等於第一垂直距離的垂直凹部深度,於晶片托盤16設置在凹部48內時,當晶片17由晶片托盤16承載或放置在晶片托盤16頂上時,晶片17的底部表面可位於距加熱元件66的頂部或頂部表面的第二垂直距離處。另一種方式,托盤16內部的第二垂直距離可從晶片的底部表面到加熱元件66的頂部進行測量,並且第二距離可小於第一距離。因此,如果第一距離(凹陷深度或凹陷48距離)約為3.5mm,則從晶片17的底部表面到托盤16內的加熱器元件66頂部的距離可小於3.5mm。
晶片17表面可包括氮化矽材料(例如,使用於在晶片表面上形成各種電子器件的氮化矽材料,包括電子器件的間隔物特徵)以及氧化矽材料,其藉由預先處理過程加以去除。在基板17表面上氮化矽材料能夠選擇性地相對於基板表面上氧化矽材料以大於約7:1的選擇性加以去除。在一些實施例中,相對於氮化矽去除氧化矽的預先清理處理過程選擇性可約為6:1至約150:1。例如,選擇性可約為6:1至約60:1,或約7:1至約15:1,或約8:1至約15:1,或約8:1至約12:1。
在預先清理材料的形成期間,晶片17可保持在期望的溫度,包括例如當晶片17的表面暴露於預先清理處理過程的反應氣體時。在一些實施例中,在預先清理材料的形成期間,晶片17可保持在高於反應氣體冷凝溫度的溫度。例如,晶片17可保持在大於約15℃或大於約20℃的溫度。在一
些其它實施例中,晶片17可保持在約15℃至約50℃,或約15℃至約30℃,或約25℃至約30℃的溫度範圍內。例如,晶片17可保持在約22℃至約28℃的範圍內的溫度,這可促進相對於晶片17表面上氮化矽材料去除氧化矽的高選擇性。
用於積體電路製造的處理過程可包括預清洗晶片表面以去除不需要的材料。在一些實施例中,不期望的材料包括氧化物材料(例如形成在矽晶片上的天然氧化矽材料)。預先清理材料的沉積及隨後預先清理材料的揮發或昇華可有利地使得從晶片表面去除氧化物材料。
作為進一步實施例,但不作為限制,為了形成預先清理材料,反應物物質在預先清理處理過程期間流入反應槽室並且與晶片表面上不期望的材料化學地相互作用。在一些實施例中,預先清理材料可包括一種或多種組成份,從反應物種類及晶片表面氧化物材料之間的化學反應或反應物物質本身之間的化學反應產生。例如,預先清理處理過程可使用包含鹵素的反應氣體,使得含鹵素的反應氣體與晶片表面的氧化矽發生化學反應,以形成包括鹵素及矽的預先清理材料。
在一些實施例中,可通過使預先清理材料藉由昇華方式進行揮發來實現氧化物去除。可在預先清理的晶片表面上形成目標材料,包括例如沉積導電材料。導電材料可包括非限制性之含半導體材料(即含矽材料),含金屬材料或其組合。如本發明所使用的,標靶材料是直接沉積為與預先清理晶片表面接觸的材料。此外,移除預先清理材料可包括從晶片移除全部或部分預先清理材料。在一些實施例中,去除自然氧化物材料的晶片可加以圖案化(即具有凹槽圖案,例如在其表面上的溝槽)。在一些實施例中,基
板可包括暴露的電子器件(即晶體結構)。
在一些實施例中,反應槽室可是外延沉積槽室,並且標靶材料可文單晶矽。例如,預先清理材料可通過在反應槽室中昇華而從晶片移除以提供預先清理的晶片表面,並且隨後可在反應槽室中預先清理的晶片表面上進行矽的外延成長,以在晶片上形成單晶矽層。
在一個特定範例中,從晶片表面昇華自然氧化物層的預先清理處理過程發生在與晶片上單晶矽層的後續成長相同的反應槽室中。在其中隨後在晶片上形成標靶材料的相同反應槽室中移除預先清理材料可有利地提供用稍後沉積標靶材料具有相當品質的表面。此外,其可有利地提供可不含或實質上不含不期望污染物材料的槽室。例如,預先清理材料可在晶片表面上提供保護層,減少或防止或實質上防止在將晶片輸送到用於標靶材料沉積的反應槽室期間在晶片表面上發生額外的氧化。在一些實施例中,在隨後形成標靶材料的相同反應槽室中去除預先清理材料可促進減少的缺陷計數或改進的電性能或兩者標靶材料的沉積。在一些實施例中,在隨後形成標靶材料的相同反應槽室中去除預先清理材料有助於在預先清理處理過程之後將晶片輸送到真空環境之外。此外,使用彼此並不真空耦合的反應槽室(即使用藉由各種門閥彼此並不耦合的反應槽室,例如群集工具中反應槽室)也可便於在預先清理處理之後將晶片輸送到真空環境之外。
在一些實施例中,預先清理處理過程可包括多個循環,其中每個循環可包括形成預先清理材料及去除預先清理材料。包括多於一個循環的預先清理過程可有利地表現出特別高的選擇性。例如,與預先清理處理過程的第一循環選擇性性能相比,預先清理處理過程的第二循環及其它隨後
的循環可顯示出相對於去除晶片表面的自然氧化矽從晶片表面顯著地更高的選擇性地從晶片表面去除另一種材料,例如氮化矽。
預先清理處理過程的反應氣體組成份可包括一種或多種運載氣體。合適的運載氣體可包括任何數量的惰性氣體。在一些實施例中,運載氣體可包括氬(Ar)。在一些實施例中,反應氣體還可包括含鹵素氣體。例如,含鹵素氣體可是含氟氣體。合適的含氟氣體可包括非限制性之三氟化氮(NF3),氟化氫(HF)或雙原子氟(F2)。在一些實施例中,反應氣體還可包括含氫氣體。合適的含氫氣體可包括例如氨(NH3)。
預先清理材料可包括通過反應氣體及晶片表面氧化矽的反應形成的一種或多種成份。例如,包含氨及一種或多種含氟化合物的反應物氣體可與氧化矽化學反應以產生水蒸氣,以及包含氮,氫及矽的預先清理材料。在一些實施例中,氨及三氟化氮,氟化氫或氟可與氧化矽反應以提供包含六氟矽酸銨或(NH4)2SiF6的預先清理材料。在一些實施例中,預先清理材料可包括例如氟化銨(NH4F)或氟化氫銨(NH4HF2)。
不受任何特定理論或操作模式的限制,據信當由反應物氣體含鹵素成分(例如NF3,HF及/或F2)的氟(F)原子與氨(NH3)反應以形成氟化氫(HF)時,其可與氨(NH3)結合以形成氟化銨(NH4F)。在一些實施例中,氟化銨可通過分解及與氧化矽反應以形成四氟化矽(SiF4)及水蒸氣(H2O)而除去氧化矽,並且四氟化物(SiF4)可與NH4F結合形成六氟矽酸銨,其中六氟矽酸銨在基板表面上形成薄膜層。例如,氟化銨帶負電之氟(F)可吸引到相當多帶正電氧化矽之矽(Si),而銨(NH4)可吸引到氧化矽的氧(O)。在一些實施例中,包括六氟矽酸銨的預先清理材料可通過加熱基板而分解及/或揮發,例
如分解形成四氟化物(SiF4),氨(NH3)及/或氟化氫(HF)。
可使用各種技術去除(例如,分解及/或揮發)預先清理材料。在一些實施例中,可通過將晶片17加熱到接近,位於或高於預先清理材料組成份的昇華溫度的溫度以移除預先清理材料。例如,晶片17可通過晶片托盤16中的加熱元件66加熱到約80℃至約500℃範圍內的溫度,包括約80℃至約100℃,在有利於昇華條件下的預先清理材料。例如,晶片17可加熱到約100℃的溫度,以引起六氟矽酸銨的昇華。昇華溫度通常可在約80℃至約120℃的範圍內。
根據一項,晶片托盤16內的加熱元件66使昇華發生所需要的顆粒量最小化。使用於發生昇華的顆粒數量最小化是指晶片17在晶片17表面上氧化物材料昇華相變化期間保持靜止。此外,加熱方向將來自晶片17下方,而不是來自上方。從其底部表面下方加熱晶片17應限制在昇華期間產生任何顆粒之增加。
如圖2所示,其顯示出一種方法200以昇華反應器系統內部槽室內晶片上氧化物材料,其使用具有加熱元件在晶片托盤中。方法200可包括各種步驟,例如將晶片放置於在晶片托盤上,通常在202處所示。晶片17可沿箭頭A的方向(圖1)移動通過開口40,以將其定位在晶片托盤16上。在晶片托盤內對加熱元件供電的步驟一般顯示為204。在一個範例性實施例中,加熱元件66由專用電源供電。將晶片托盤的溫度從第一溫度升高到第二溫度的步驟,其中當晶片達到第二溫度時,晶片上的氧化物材料通過昇華從固體變成內部槽室中的氣體,在一個範例性實施例中,第二溫度可是通常約為100℃昇華溫度。
在一些實施例中,晶片托盤16內的加熱元件66將在預先清理處理過程(氧化物層的轉化)之後進行加熱/啟動。此外,加熱元件66有可能也可用於在預先清理處理期間保持晶片17的溫度。冷卻通道56可與加熱元件協作以保持(經由冷卻)晶片17的期望溫度於晶片17變得太熱而不從加熱元件66傳遞熱量到晶片17。
方法200可包括一些附加步驟,作為範例而非限制性,其中第一溫度在約15℃至約30℃的範圍內,並且其中第二溫度可在約75℃至約150℃。另外,方法200可包括以上述溫度升高速率升高晶片托盤內加熱元件的溫度之步驟,其可在約50℃/秒至約200℃/秒的範圍內,或者約75℃/秒至約150℃/秒或175℃/秒,並且可約為100℃/秒。同樣地,由於熱量快速地由加熱的加熱元件66傳遞到晶片17,晶片17及其所有表面的溫度可快速升高,因而晶片17的加熱或溫度升高可以高速率在相同的範圍發生,其與上面所提到的加熱元件66的高速率之範圍相同。
此外,方法200可包括為加熱元件66供電的步驟,其可由專用電源完成。方法200還可包括以下步驟:將晶片17上的底部表面定位成離晶片托盤中的加熱元件一段垂直距離,其中從晶片17上的底部表面到加熱元件的頂部表面的垂直距離66可小於凹部48的垂直凹部深度。方法200還可包括用界定出多個冷卻通道56的基座18冷卻晶片托盤16,並且用作從晶片托盤16吸收熱能的散熱器。在將晶片托盤16的溫度從第一溫度升高到第二溫度的同時,方法200還可包括將晶片17保持恆定的垂直高度之步驟。甚至進一步地,方法200可包括以下步驟:在晶片17上方通過等離子體相之元素以及氣相化學元素之一,以處理及與內部槽室14內晶片17上的自然氧化物層反應;並
且在內部槽室14內引發昇華相變化,其中所有發生在內部槽室14內的自然氧化物處理及昇華可防止或實質上減少在兩個槽室之間的晶片17轉移期間通常發生的外來顆粒污染。另外,在氧化物材料昇華之後,方法200可進一步包括以下步驟:從晶片托盤16及從內部槽室14移除晶片17;維持對加熱元件66的功率以保持晶片托盤加熱到從約80℃至約120℃範圍內的溫度;將第二晶片定位在內部槽室14內的晶片托盤16上,第二晶片包括固體相之自然氧化物層;在不超過約兩(2.0)秒內從第二晶片將氧化物層昇華。升高晶片托盤16上晶片17溫度的步驟可通過從下方加熱晶片17來實現,其中從下面支撐晶片托盤16的基座18沒有或不包括加熱元件。
在前面的說明中,為了簡潔,清楚及理解而使用了特定術語。除了現有技術的要求之外,並不暗示不必要的限制,因為這些術語用於說明性目的以及旨在被廣泛地解釋。
此外,本文所說明及列舉說明是範例性,以及本發明不限於所顯示出或所說明的確切細節。
10‧‧‧反應器系統
12‧‧‧噴頭
14‧‧‧槽室
14a‧‧‧上部槽室區域
14b‧‧‧中間槽室區域
14c‧‧‧下部槽室區域
16‧‧‧晶片托盤
17‧‧‧晶片
18‧‧‧基座
20‧‧‧頂壁
22‧‧‧底部表面
24‧‧‧通道
26‧‧‧歧管
28‧‧‧洞孔
30‧‧‧頂部表面
32‧‧‧底部表面
34‧‧‧反應槽室組件
36‧‧‧側壁
40‧‧‧開口
42‧‧‧底壁
44‧‧‧出口
42‧‧‧底壁
46‧‧‧頂部表面
48‧‧‧凹部
50‧‧‧頂部表面
52,54‧‧‧感測器
56‧‧‧通道
58‧‧‧間隙
60‧‧‧外周邊
62‧‧‧頂部表面
64‧‧‧底部表面
66‧‧‧加熱元件
Claims (20)
- 一種反應器系統,其包括:反應槽室組件,其界定出內部區域槽室;在內部槽室內的基座;位於基座上及適於承載晶片的晶片托盤;及晶片托盤中的加熱元件適於加熱晶片托盤將晶片加熱至昇華溫度。
- 依據申請專利範圍第1項之反應器系統,其中晶片托盤具有不超過5公釐的厚度。
- 依據申請專利範圍第1項之反應器系統,其中晶片托盤包括氮化鋁及氮化硼中的一種。
- 依據申請專利範圍第1項之反應器系統,其中晶片托盤具有約0.4千克至約1.5千克範圍內的質量。
- 依據申請專利範圍第1項之反應器系統,其中系統與晶片結合,晶片具有底部表面;其中晶片托盤在凹部內;以及更進一步包括:形成在基座中凹部,從基座的頂部表面向下延伸以及具有垂直凹槽深度;及從晶片的底部表面到加熱元件的頂部表面的垂直距離,其中垂直距離小於凹部深度。
- 依據申請專利範圍第1項之反應器系統,其中垂直距離不超過約3.5mm。
- 依據申請專利範圍第1項之反應器系統,其與晶片結合;其中晶片具有自然氧化物層及由晶片托盤承載;及電源可操作地耦合到加熱元件以及能夠對加熱元件加熱,使得加熱元件 能夠將晶片加熱到氧化物層的昇華溫度。
- 依據申請專利範圍第1項之反應器系統,其中基座不包括加熱元件。
- 依據申請專利範圍第1項之反應器系統,其更進一步包括:電源,其可操作地耦合到加熱元件以及能夠以約50℃/秒到約200℃/秒的範圍內的溫度升高速率對加熱元件加熱。
- 一種方法,包括以下步驟:將晶片放置在反應槽室組件內的晶片托盤上;及對晶片托盤內的加熱元件供電將晶片托盤的溫度從第一溫度升高到第二溫度,以使晶片上的氧化物材料在反應槽室組件內經歷昇華。
- 依據申請專利範圍第1項之方法,其中第一溫度在約15℃至約30℃的範圍內;及其中第二溫度在約75℃至約150℃的範圍內。
- 依據申請專利範圍第1項之方法,其更進一步包括以下步驟:以約50℃/秒至約200℃/秒的範圍內的速率升高晶片托盤內加熱元件的溫度。
- 依據申請專利範圍第1項之方法,其更進一步包括以下步驟:以約50℃/秒至約200℃/秒的範圍內的速率升高晶片托盤的溫度。
- 依據申請專利範圍第1項之方法,其更進一步包括以下步驟:提供界定出凹部的基座,晶片托盤設置在凹部中,以及基座具有凹部深度;及將晶片的底部表面定位在晶片托盤中的加熱元件上方一段垂直距離處,其中垂直距離小於凹陷深度。
- 依據申請專利範圍第1項之方法,其更進一步包括以下步驟:用界定出多個冷卻通道及用散熱器的基座冷卻晶片托盤。
- 依據申請專利範圍第1項之方法,其更進一步包括在將晶片托盤的溫度從第一溫度升高到第二溫度的過程中將晶片保持在恆定的垂直高度之步驟。
- 依據申請專利範圍第1項之方法,其更進一步包括以下步驟:等離子體相元素及氣相化學元素之一通過晶片上方,以處理內部槽室內的晶片上之自然氧化物層並與其產生反應。
- 依據申請專利範圍第1項之方法,其中晶片是第一晶片;以及在氧化物材料昇華之後還包括以下步驟:從晶片托盤及內部槽室移除第一晶片;保持對加熱元件的功率將晶片托盤加熱到從80℃至約120℃的範圍內的溫度;將第二晶片定位在內部槽室內的晶片托盤上,第二晶片包括固體相之自然氧化物層;在不超過兩秒鐘內將氧化物層昇華。
- 依據申請專利範圍第1項之方法,其更進一步包括以下步驟:將晶片托盤支撐在不包括加熱元件的基座上。
- 一種反應槽室系統,其包括:反應槽室組件,其界定出內部槽室;在內部槽室內的晶片托盤;及由晶片托盤承載的至少一個加熱元件;其中除了由晶片托盤承載的至少一個加熱元件之外,內部槽室中並無加熱元件。
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