TW201719851A - 電磁遮罩封裝結構及其製造方法 - Google Patents
電磁遮罩封裝結構及其製造方法 Download PDFInfo
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Abstract
本發明公開了一種電磁遮罩封裝結構及其製造方法。該電磁遮罩封裝結構包括基板、安裝於該基板上的至少一個元器件、注膠層、包覆該注膠層外表面的遮罩金屬層;基板外側設有接地端,基板上設有第一通孔,至少一元器件上設有第二通孔,該第一通孔和第二通孔內壁均設有導電層;該遮罩金屬層通過導體順次連接該第二通孔的導電層、第一通孔的導電層及該接地端形成導電回路,使遮罩金屬層接地。從而提供一種結構簡單、使用可靠、加工方便的電磁遮罩封裝結構,降低材料和加工成本。
Description
本發明涉及晶片封裝技術領域,尤其是涉及一種電磁遮罩封裝結構及其製造方法。
目前,通訊產品已廣泛普及並有了長足發展,與此同時,對通訊產品小型化和高靈敏度的要求也越來越高,對信號品質的要求也越發嚴格,因此,電磁相容(EMI)成了系統小型化封裝中一個非常重要的問題。
為遮罩外界磁場對射頻模組的干擾,現有技術中主要存在如下解決方案:1、射頻模組安裝在主機板上,直接在主機板上模組周圍放置金屬遮罩蓋,其存在金屬遮罩蓋設計複雜,成本高,且要佔據主機板空間,增加PCB尺寸,遮罩蓋和PCB板之間有分層風險的缺陷;2、在射頻模組內置金屬遮罩蓋,該方案中金屬遮罩蓋導致PCB面積增加,成本高,且封裝注膠過程容易有氣洞問題;3、模組表面電鍍/噴塗導電材料,和模組基板背面接地I/O或基板上表面邊緣接地I/O 連接,也存在需要增加PCB和產品尺寸、封裝注膠時需要單顆封裝、增加成本的問題;4、模組表面電鍍/噴塗導電材料,和模組基板側面外露接地導線連接,需要增加PCB尺寸,且整片PCB產品電鍍/噴塗,產品導電材料厚度不容易控制,影響EMI效果;5、模組上表面電鍍/噴塗導電材料和金線接地,側面通過金線實現遮罩,該方案金線接地工藝時間長,且不可靠,另大幅增加成本。
針對現有技術中存在的上述問題,本發明提供了一種電磁遮罩封裝結構及其製造方法,旨在提供一種結構簡單、使用可靠、加工方便的電磁遮罩封裝結構,降低材料和加工成本。
本發明是通過如下技術方案實現的:
一種電磁遮罩封裝結構,包括基板、安裝於該基板上的至少一個元器件、覆蓋該元器件並填充該元器件與該基板之間空隙的注膠層、包覆該注膠層外表面的遮罩金屬層;該基板外側設有至少一個接地端,基板上與接地端對應的位置設有第一通孔,至少一元器件上設有第二通孔,該第一通孔和第二通孔內壁均設有導電層,該遮罩金屬層通過導體順次連接該第二通孔的導電層、第一通孔的導電層及該接地端形成導電回路,使遮罩金屬層接地。
本發明還公開了一種電磁遮罩封裝結構的製造方法,包括步驟:
製作基板,在基板外側設置至少一個接地端,基板上與接地端對應的位置開設第一通孔,第一通孔內壁附著導電膜,並將第一通孔內壁的導電膜與接地端電連接;
將至少一個元器件安裝於該基板上,並在至少一個元器件上開設第二通孔,第二通孔內壁附著導電膜並將該導電膜與第一通孔內壁的導電膜電連接;
注膠覆蓋該元器件並填充該元器件與該基板之間空隙;
注膠層開設連通至該第二通孔的缺口;
在注膠層外表面形成遮罩金屬層,遮罩金屬層填充該缺口並與該第二通孔內壁的導電膜電連接。
本發明公開的電磁遮罩封裝結構及其製造方法有效利用元器件和濺鍍,形成接地回路,達到電磁遮罩效果,不必單獨設置遮罩蓋,減小空間佔用; 電磁遮罩封裝結構側面無濺鍍金屬,模組後續安裝到主機板上不會有短路問題,從而提供了一種結構簡單、使用可靠、加工方便的電磁遮罩封裝結構,降低材料和加工成本。
圖1至圖5是本發明的電磁遮罩封裝結構在一實施例中的製造工藝流程示意圖;
圖6為本發明的電磁遮罩封裝結構中倒裝晶片在一實施例中的結構示意圖。
請參閱圖1所示,本發明的電磁遮罩封裝結構在本實施例中包括基板9,基板9具有第一表面9b及與該第一表面9b平行設置的第二表面9c,再參閱圖2所示,該基板9上安裝有至少一個元器件,例如,元器件安裝於第一表面9b上。參閱圖3和圖4所示,還包括注膠層2,注膠層2覆蓋該元器件並填充該元器件與該基板9之間空隙。再參閱圖5所示,注膠層2外表面包覆有遮罩金屬層3。第二表面9c外側設有接地端5,基板9上與接地端5對應的位置設有第一通孔9a,第一通孔9a貫穿該第一表面9b和第二表面9c。至少一元器件上設有第二通孔1a,第二通孔1a和第一通孔9a內壁均設有導電層。注膠層2上設有連通第二通孔1a至遮罩金屬層3的缺口2a(如圖4所示),該缺口2a內設有連接遮罩金屬層3與第二通孔1a的導電層的導體,遮罩金屬層3通過導體順次連接該第二通孔1a的導電層、第一通孔9a的導電層及該接地端5形成導電回路,使遮罩金屬層3接地。
可以理解的是,在具體實施中,接地端5可以如圖5所示,設於基板9的第二表面9c上,以便於直接接地,接地端5也可以根據基板9上元器件的佈局,設置於基板9的其他未被覆蓋的表面上,並且根據常識可以理解的是,接地端5可以直接接地,也可以根據實際需要連接到其他電器接地的外殼,達到使遮罩金屬層3接地的效果即可。
在具體實施中,上述元器件可以為裸晶片、無源器件、封裝晶片中的一種或多種。當該元器件為裸晶片8時,裸晶片8可倒裝焊接在基板9上,形成倒裝晶片1,具體而言,裸晶片8通過多個導電銅柱10和倒裝焊腳固定連接於基板9上,相應的,第二通孔1a的導電層、第一通孔9a的導電層通過導電銅柱10和倒裝焊腳連接導通,從而形成路徑順次為遮罩金屬層3、缺口2a內的導體、第二通孔1a的導電層、第一通孔9a的導電層、導電銅柱10、倒裝焊腳、接地端5的導電回路,使遮罩金屬層3接地。裸晶片8也可以通過粘合劑粘合於該基板9上,並通過連接線7與設於基板9上的焊墊9d之間電連接。當該元器件為無源器件6或封裝後的晶片時,無源器件6或封裝後的晶片採用表面貼裝的方式安裝於該基板9上。
為簡化結構和加工,上述導體為遮罩金屬層3填充在該缺口內的部分。以倒裝晶片1為例,參閱圖6所示,倒裝晶片1包括晶片本體1b,晶片本體1b的一面設有導電銅柱10,導電銅柱10前端設有焊腳1c,倒裝晶片1通過焊腳1c倒裝焊接在基板9上,晶片本體1b的另一面為晶片金屬層,晶片本體1b上設有連通至晶片金屬層的第二通孔1a,第二通孔1a內壁附著有導電層。倒裝晶片1固定在基板後通過注膠層2填充封裝,注膠層2上開設有連通至晶片金屬層的缺口,如此一來,在注膠層2外表面形成遮罩金屬層3時,遮罩金屬層3同時填充入該缺口內,使遮罩金屬層3與倒裝晶片1的晶片金屬層導電連接,進而形成路徑順次為遮罩金屬層3、倒裝晶片1的晶片金屬層、第二通孔1a的導電層、導電銅柱10、焊腳1c、第一通孔9a的導電層、接地端的導電回路,使遮罩金屬層3接地,對封裝於基板9上的倒裝晶片1起到電磁遮罩作用。可以理解的是,在基板9和遮罩金屬層3之間還可同時遮罩封裝其他元器件,如上述裸晶片、無源器件、封裝晶片。
從本發明的上述電磁遮罩封裝結構可知,其有效利用了封裝的元器件,通過在元器件及基板內部設置導電通孔,將遮罩金屬層3接地,達到電磁遮罩效果,不必外設遮罩器件及遮罩線路,有效簡化了結構,同時有利於減小封裝結構的尺寸。
相應的,本發明還公開了上述電磁遮罩封裝結構的製造方法,現結合圖1至圖6作詳細說明,具體步驟如下:
製作基板9,在基板9外側設置至少一個接地端5,基板9上與接地端5對應的位置開設第一通孔9a,第一通孔9a內壁塗敷導電膜,並將第一通孔9a內壁的導電膜與接地端5電連接;
將至少一個元器件安裝於該基板上,並在至少一個元器件上開設第二通孔1a,第二通孔1a內壁塗敷導電膜並將該導電膜與第一通孔9a內壁的導電膜電連接;
注膠覆蓋該元器件並填充該元器件與基板9之間空隙,將零部件封裝在基板9上;
在注膠層2開設連通至該第二通孔1a的缺口2a;
在注膠層2外表面形成遮罩金屬層3,遮罩金屬層3填充該缺口2a並與該第二通孔1a內壁的導電膜電連接。在具體實施中,遮罩金屬層3可選用銅等材料通過濺鍍的方式在注膠層表面形成遮罩層,也可以選用含鐵、鈷、鎳或相應合金的高導磁率、高導電率的膠體形成遮罩層。
為提高加工效率,上述製作基板9的步驟中,該基板採用連片基板並按預定規格劃分為多個單元基板,在每個單元基板分別設置接地端5、第一通孔9a及其內壁的導電膜,完成後續步驟,並在形成遮罩金屬層3的步驟後還包括切割形成單顆電磁遮罩封裝結構的步驟。採用連片加工的工藝還存在如下優點:其一,在形成遮罩金屬層3時,可以整片濺鍍,相對單顆濺鍍大大節約材料成本,其二,切割形成的單顆電磁遮罩封裝結構側面無濺鍍金屬,後續安裝到主機板上不會造成短路隱患。
以上實施例僅用以說明本發明的技術方案而非限制,儘管參照較佳實施例對本發明進行了詳細說明,本領域的普通技術人員應當理解,可以對本發明的技術方案進行修改或等同替換,而不脫離本發明技術方案的精神和範圍。
1‧‧‧倒裝晶片
2‧‧‧注膠層
3‧‧‧遮罩金屬層
4‧‧‧倒裝晶片金屬層
5‧‧‧接地端
6‧‧‧無源器件
7‧‧‧連接線
8‧‧‧裸晶片
9‧‧‧基板
10‧‧‧導電銅柱
9a‧‧‧第一通孔
1b‧‧‧晶片本體
1c‧‧‧焊腳
2a‧‧‧缺口
1a‧‧‧第二通孔
9b‧‧‧第一表面
9c‧‧‧第二表面
9d‧‧‧焊墊
無
1‧‧‧倒裝晶片
2‧‧‧注膠層
3‧‧‧遮罩金屬層
4‧‧‧倒裝晶片金屬層
5‧‧‧接地端
6‧‧‧無源器件
7‧‧‧連接線
8‧‧‧裸晶片
9‧‧‧基板
10‧‧‧導電銅柱
9a‧‧‧第一通孔
1c‧‧‧焊腳
1a‧‧‧第二通孔
9b‧‧‧第一表面
9c‧‧‧第二表面
9d‧‧‧焊墊
Claims (10)
- 一種電磁遮罩封裝結構,包括基板、安裝於該基板上的至少一個元器件、覆蓋該元器件並填充該元器件與該基板之間空隙的注膠層、包覆該注膠層外表面的遮罩金屬層;該基板外側設有至少一個接地端,基板上與接地端對應的位置設有第一通孔,至少一元器件上設有第二通孔,該第一通孔和第二通孔內壁均設有導電層,該遮罩金屬層通過導體順次連接該第二通孔的導電層、第一通孔的導電層及該接地端形成導電回路,使遮罩金屬層接地。
- 如申請專利範圍第1項所述的電磁遮罩封裝結構,其中,該基板具有第一表面及與該第一表面平行設置的第二表面,該元器件安裝於該第一表面,該接地端設於該第二表面外側,該第一通孔貫穿該第一表面和第二表面。
- 如申請專利範圍第1項所述的電磁遮罩封裝結構,其中,該注膠層上設有連通該第二通孔至該遮罩金屬層的缺口,該缺口內設有連接該遮罩金屬層與該第二通孔的導電層的導體。
- 如申請專利範圍第3項所述的電磁遮罩封裝結構,其中,該導體為該遮罩金屬層填充在該缺口內的部分。
- 如申請專利範圍第1項所述的電磁遮罩封裝結構,其中,該元器件為裸晶片,該裸晶片倒裝焊接於該基板上。
- 如申請專利範圍第1項所述的電磁遮罩封裝結構,其中,該元器件為裸晶片,該裸晶片粘合於該基板上,並通過連接線與基板之間電連接。
- 如申請專利範圍第1項所述的電磁遮罩封裝結構,其中,該元器件為無源器件或封裝後的晶片,該無源器件或封裝後的晶片採用表面貼裝的方式安裝於該基板上。
- 一種電磁遮罩封裝結構的製造方法,包括步驟:
製作基板,在基板外側設置至少一個接地端,基板上與接地端對應的位置開設第一通孔,第一通孔內壁附著導電膜,並將第一通孔內壁的導電膜與接地端電連接;
將至少一個元器件安裝於該基板上,並在至少一個元器件上開設第二通孔,第二通孔內壁附著導電膜並將該導電膜與第一通孔內壁的導電膜電連接;
注膠覆蓋該元器件並填充該元器件與該基板之間空隙;
注膠層開設連通至該第二通孔的缺口;
在注膠層外表面形成遮罩金屬層,遮罩金屬層填充該缺口並與該第二通孔內壁的導電膜電連接。 - 如申請專利範圍第8項所述的電磁遮罩封裝結構的製造方法,其中,該製作基板的步驟中,該基板採用連片基板並按預定規格劃分為多個單元基板,在每個單元基板分別設置接地端、第一通孔及其內壁的導電膜,完成後續步驟,並在形成遮罩金屬層的步驟後還包括切割形成單顆電磁遮罩封裝結構的步驟。
- 如申請專利範圍第8項或第9項所述的電磁遮罩封裝結構的製造方法,其中,該遮罩金屬層通過金屬濺鍍的方式形成於注膠層外表。
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US10541209B2 (en) * | 2017-08-03 | 2020-01-21 | General Electric Company | Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof |
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US10796976B2 (en) * | 2018-10-31 | 2020-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming the same |
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US8946886B1 (en) * | 2010-05-13 | 2015-02-03 | Amkor Technology, Inc. | Shielded electronic component package and method |
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US20130323409A1 (en) * | 2012-05-31 | 2013-12-05 | Skyworks Solutions, Inc. | Systems and methods for controlling electromagnetic interference for integrated circuit modules |
US9129954B2 (en) * | 2013-03-07 | 2015-09-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor package including antenna layer and manufacturing method thereof |
US8987872B2 (en) * | 2013-03-11 | 2015-03-24 | Qualcomm Incorporated | Electromagnetic interference enclosure for radio frequency multi-chip integrated circuit packages |
US20150085462A1 (en) * | 2013-09-26 | 2015-03-26 | Yoshinari Matsuda | Electromagnetic interference shielding material, electromagnetic interference shielding device, method for making the electromagnetic interference shielding device, electromagnetic interference shielding package module and appliance |
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