TW201620101A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW201620101A
TW201620101A TW104138448A TW104138448A TW201620101A TW 201620101 A TW201620101 A TW 201620101A TW 104138448 A TW104138448 A TW 104138448A TW 104138448 A TW104138448 A TW 104138448A TW 201620101 A TW201620101 A TW 201620101A
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Taiwan
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conductive
conductive bumps
semiconductor wafer
substrate
wires
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TW104138448A
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TWI591785B (zh
Inventor
林彥良
郭庭豪
吳勝郁
陳承先
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台灣積體電路製造股份有限公司
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Abstract

提供一種半導體結構及其形成方法。該半導體結構包括：基板，其包括多個導線；以及一個半導體晶片，所述半導體晶片包括：表面，其朝向所述多個導線；以及多個傳導襯墊，其位於所述表面之上以及通過多個傳導凸塊與所述多個導線相應地電連接。每個所述多個傳導凸塊的一個高度是由所述多個傳導襯墊和相應的所述導線之間的最小距離確定。

Description

半導體裝置及其製造方法
本發明系有關於一種半導體結構，且特別是有關於一種凸塊直接連接導線(Bump On Trace BOT)的半導體結構。
由於積體電路的發明，各種電子器件(例如，電晶體、二極體、電阻器以及電容器等)以及半導體封裝在集成密度方面的持續改進，半導體工業已經經歷連續的快速增長。在大多數情況下，這些集成密度方面的改進都源於反復削減最小特徵尺寸，使更多器件被集成到半導體晶片或封裝中。
用於允許更多器件集成到半導體封裝的一種方法是採用凸塊直接連接導線(BOT)的結構。BOT結構用於倒裝片封裝，其中金屬凸塊(用於支撐設備模具)直接落在封裝基板的金屬線上，而不是被放置在金屬襯墊上，該金屬襯墊具有比金屬線更大的寬度。BOT結構的優點包括更小的晶片面積要求和低製造成本。
對於BOT結構，所述半導體晶片與所述封裝基板的熱膨脹係數(CTE)之間的不匹配可能導致金屬線上的應力，引起所述金屬線從所述封裝基板剝離。此外，對於具有更細凸塊間距(相鄰的結合凸塊之間的距離)的BOT結構，由於所述導線的寬度減小，導線和所述封裝基板之間的結合力變小，這也導致所述金屬線從所述封裝基板剝離。鑒於以上所述，有必要解決上述問題以及傳統BOT結構中其 它方面的不足。
本發明提供一種半導體結構，其包括：基板，其包括多個導線；以及半導體晶片，所述半導體晶片包括：表面，其朝向所述多個導線；以及多個傳導襯墊，其位於所述表面之上以及通過多個傳導凸塊與所述多個導線對應地電連接，其中每個所述多個傳導凸塊的一個高度是由所述多個傳導襯墊和相應的所述導線之間的最小距離確定。
本發明亦提供一種半導體結構，其包括：基板，該基板包括多個導線，該多個導線覆蓋該基板之表面；以及半導體晶片，該半導體晶片經由多個傳導凸塊電連接到該多個導線，其中該多個傳導凸塊部分地分佈在該半導體晶片的一中心區域，以及部分地分佈在該半導體晶片的一周邊區域，且位於該中心區域的該多個傳導凸塊與位於該周邊區域的該多個傳導凸塊具有一不同的高度。
本發明更提供一種形成半導體結構的方法，其包括：提供一個包括多個導線的基板；提供一個半導體晶片；形成多個傳導襯墊於所述半導體晶片之表面上；通過多個傳導凸塊，所述多個傳導襯墊和所述多個導線對應地電耦合；以及確定每個所述多個傳導凸塊的一個高度為所述多個傳導襯墊和相應的導線之間的一個最小距離。
100‧‧‧半導體結構
101‧‧‧基板
102‧‧‧半導體晶片
102a‧‧‧半導體晶片表面
103、103c、103p‧‧‧傳導凸塊
104‧‧‧導線
104a‧‧‧導線頂面
105‧‧‧凹槽
106‧‧‧表面
107‧‧‧導體
108‧‧‧導電材料
111‧‧‧中心區域
112‧‧‧周邊區域
113、114、1022、1122‧‧‧傳導襯墊
112‧‧‧周邊區域
117‧‧‧寬度
901‧‧‧導電材料
902‧‧‧掩膜層
1011‧‧‧多層次金屬結構
1012‧‧‧焊接掩模
1013‧‧‧球墊
1014‧‧‧焊料球
1021‧‧‧下傳導凸塊冶金(UBM)結構
1023‧‧‧鈍化層
Hc‧‧‧傳導凸塊的高度
Hp‧‧‧傳導凸塊的高度
Dc‧‧‧中心區域上的傳導襯墊和基板之間的距離
Dp‧‧‧周邊區域上的傳導襯墊和基板之間的最小距離
H‧‧‧傳導凸塊與UBM結構之間的介面到傳導凸塊與導體之間的介面的距離
D‧‧‧傳導襯墊和相應的導線的頂面之間的最小距離
為協助讀者達到最佳理解效果，建議在閱讀本揭露時同時結合附圖及以下詳細說明。應該注意的是，遵照行業內標準做法，各特徵不是按比例繪製。事實上，為了清楚的討論，各特徵尺寸可以任意放大或縮小。
圖1為示出根據一些實施例的半導體結構之示意圖。
圖1A為示出根據一些實施例的半導體結構之示意圖。
圖2為示出根據本公開內容的圖1A的半導體結構之截面 圖。
圖3A為根據一些實施例的半導體晶片的示意圖。
圖3B為示出根據本公開內容的圖3A的半導體晶片的截面圖。
圖4A及圖4B為示出根據一些實施例的半導體晶片的截面圖。
圖5A為示出根據一些實施例的半導體晶片的示意圖。
圖5B為根據本公開內容的圖5A的半導體晶片的截面圖。
圖6A及圖6B為示出根據一些實施例的半導體晶片的截面圖。
圖7代表根據一些實施例的製造半導體結構的流程圖。
圖8A-8F代表根據本公開內容的圖7的製造半導體結構的流程圖。
圖9A-9F示意性示出根據本公開內容的圖8D及圖8E的製造半導體結構的方法。
以下揭露內容提供了數個不同的實施例或示例，用於實現所提供主題的不同特徵。為簡化本公開內容，各器件和佈局的具體示例描述如下。當然，這些僅僅是示例且並不旨在有所限定。例如，本描述中的第一特徵基於第二特徵之上，跟隨第二特徵的形成可以包括一些實施例，該實施例中第一特徵和第二特徵以直接接觸形成；也可以包括一些實施例，該實施例中附加特徵形成於第一特徵和第二特徵之間，以使得該第一特徵和第二特徵以間接接觸形成。此外，本公開內容可在各個示例中重複參考數值和/或字母。這種重複是為了簡化和清楚的目的，本身並不表明所討論的各個實施例和/或配置之間的關係。
此外，為便於描述本文，空間相對術語，如“在...之下”，“以下”，“下”，“上方”，“上面的”等，在本文中被使用。該術語用來描述一個元件，或與另一元件(多個)特徵的關係，或圖中所示的特徵(多個特徵)。空間相對術語意在包含正在使用或操作中的裝置的不同方向，除了在附圖中已描述的方向。該裝置可被另外定位(旋轉90度或沿其它方向)，並在此使用的空間相對描述符同樣可以相應地解釋。
隨著在先進設備封裝方面的更細間距不斷增長的需求，凸塊直接連接導線(BOT)的半導體結構也越來越受歡迎。然而，由於半導體結構的基板和半導體晶片的熱膨脹係數不同，所以基板的彎曲條件和半導體彎曲條件因此也不同，導致了在基板和半導體晶片之間虛焊接的風險。為瞭解決上述問題，本發明提供了一種半導體結構，其中，電連接基板與所述半導體結構的半導體晶片的傳導凸塊的高度可以被改變，以避免製造半導體的過程中產生虛焊。
參照附圖，圖1為示出根據一些實施例的半導體結構100的示意圖。所述半導體結構100包括基板101、半導體晶片102、傳導凸塊103及導線104，該導線104提供於所述基板101的表面106上。所述導線104直接覆蓋所述基板101。在一些實施例中，所述基板包括印刷電路板(PCB)。
參照附圖，圖1A為示出根據本公開內容的一些實施例的半導體結構100的示意圖。所述半導體結構100包括基板101、半導體晶片102、傳導凸塊103、導線104，所述導線104提供於所述基板101的表面106上，以及凹槽105，所述凹槽105被填充導電材料108。所述導線104與所述凹槽105相連。
圖2為詳細示出本公開內容中的圖1的半導體結構100的截面圖，其中該示例性截面圖是從沿圖1A的線A-A'橫跨之平面而得到 的。該半導體結構100包括基板101。所述基板101具有凹槽105，所述凹槽105形成於所述基板101內，且填充了導電材料108。導線104提供於所述基板101的表面106上，且安置於所述基板101的表面106上，以使得導線104直接覆蓋所述基板101，且在所述凹槽105內連接所述導電材料108。所述導電材料108是由與所述導線104相同的材料形成。所述傳導凸塊103於所述半導體結構100內部提供導電通道和機械連接。所述傳導凸塊103通過導體107電連接所述導線104，該傳導凸塊103放置在接近所述基板101的所述凹槽105處，且在所述基板101的所述凹槽105之上。在一些實施例中，所述導體107可以由無鉛焊料、共晶焊料或類似材料組成。所述半導體晶片102電連接到所述傳導凸塊103，即所述半導體晶片102和所述導線104通過傳導凸塊103電連接。
在一些實施方案中，所述半導體晶片102通過傳導凸塊103以倒裝晶片配置連接到所述基板101(也已知為可控塌陷晶片連接或C4)。與傳統的封裝技術相比，如絲焊和卷帶自動結合(TAB)，倒裝晶片封裝具有在所述半導體晶片和所述基板之間較短的信號傳輸通道，從而提供了更好的電性能。此外，倒裝晶片封裝被設計成暴露半導體晶片的背面(不朝向基板的表面)，以便增加散熱速率。在一些實施例中，所述半導體結構100可以是半導體封裝，其半導體封裝提供防止衝擊和腐蝕的保護，並消散半導體晶片產生的熱量。
所述半導體晶片102可包括邏輯裝置，嵌入式快閃記憶體裝置、存儲裝置、微機電(MEMS)裝置、類比裝置、CMOS裝置、這些裝置的組合，或類似的半導體裝置。在一些實施例中，所述半導體晶片102以如下的方式連接到位於半導體晶片表面102a的所述傳導凸塊103。首先，傳導襯墊1022和鈍化層1023(其一般是由聚醯亞胺材料製成)在所述半導體晶片102上依次形成。所述鈍化層1023暴露所述傳導襯墊1022的一部分。下傳導凸塊冶金(UBM)結構1021隨後形成在 所述傳導襯墊1022的暴露部分和所述鈍化層1023上。在最後的操作中，所述傳導凸塊103連接到所述UBM結構1021，從而電連接所述半導體晶片102和傳導凸塊103。
在一些實施例中，所述UBM結構1021包括形成於所述傳導襯墊1022上的金屬粘合層；阻擋層，所述阻擋層用於防止擴散；以及焊料可潤濕層，所述焊料可潤濕層用於連接所述傳導凸塊103。所述UBM結構1021提供的功能，例如在所述傳導凸塊103與所述半導體晶片102的所述傳導襯墊1022之間的傳導凸塊連接、擴散阻擋和適當的粘附等，以使得焊接材料可以塗覆到所述UBM結構1021，然後進行回流工藝，以形成所需要的傳導凸塊103。所述UBM結構1021通常包括鈦-銅-鎳(Ti-Cu-Ni)金屬層，並且可以通過，例如濺射、蒸發、電鍍等來製造。
所述基板101可包括體矽，其體矽是摻雜或未摻雜的，或包括絕緣矽(SOI)基板的有源層。通常，SOI基板包括半導體材料，如矽、鍺、矽鍺、SOI、絕緣體矽鍺(SGOI)，或其組合。在一些實施例中，所述基板101包括多層基板、梯度基板、混合取向基板和它們的任何組合和/或類似物，使得所述半導體封裝可容納更多有源器件、無源器件和電路。在一些實施例中，所述基板101可被形成，通過使用具有通孔的多個含環氧基絕緣層，所述通孔填充有導電塞或填充材料。提供多層次金屬結構1011(例如，形成於所述多個含環氧基絕緣層內的導電塞，填充材料或導線)以形成沿垂直方向上的導電路徑。在一些實施例中，焊接掩模1012定位於所述基板101底部，所述焊接掩模1012圍繞球墊1013，所述球墊1013經配置以接收外部端子，例如焊料球1014，其提供用於產生所述半導體結構的外部連接器。
所述導線104提供於所述基板101的所述表面106上，以形成電子式連接。所述導線104基本上由純銅、鋁銅、或其它金屬材料如 鎢、鎳、鈀、金，和/或它們的合金形成。與常規的焊接技術相比，本公開內容採用凸塊直接連接導線(BOT)結構。在BOT結構中，所述傳導凸塊103直接安裝在所述導線104上，而不是安裝在焊接襯墊上(常規方法)。安裝在所述導線104上比安裝在焊接襯墊上具有更大的寬度，從而減少了所需的晶片面積和傳導凸塊間距。
在一些實施方案中，傳導凸塊103作為所述焊接元件被提供，以使得所述傳導凸塊103代替常規的焊接傳導凸塊安裝在所述導線104上。即，所述半導體晶片102經由所述傳導凸塊103連接到導線104。所述傳導凸塊103提供導電路徑以及所述半導體晶片102和所述基板101之間的熱傳導路徑。本公開內容所述的傳導凸塊103可以是棱鏡或圓柱體。應當指出的是，所述傳導凸塊103的熔點高於所述導體107的熔融溫度。
在一些實施例中，所述傳導凸塊103由金屬製成。在一些實施例中，所述傳導凸塊103的材料由錫、鉛、銅、金、銀、鋅、鉍、鎂、銻、銦和它們的合金中選擇。使用銅作為所述傳導凸塊103的材料具有以下優點：與常規焊料傳導凸塊的技術相比，採用銅凸塊作為焊料元件不僅有助於實現具有傳導凸塊橋接最小可能性的更細間距，也為電路降低了電容負載(電子互連)。銅凸塊提供更高的可靠性，且改善的電性能和熱性能。然而在回流焊中，傳統焊料傳導凸塊塌陷，銅凸塊保持其形狀。
所述傳導凸塊103具有高度H，所述高度H是從所述傳導凸塊103與所述UBM結構1021之間的介面到所述傳導凸塊103與所述導體107之間的介面來測量。對於一些實施例，UBM結構1021是可選的。對於一些沒有UBM結構1021實施例，所述高度H從所述傳導凸塊103和傳導襯墊1022之間的介面上測量。在一些實施方案中，所述高度H可通過改變UBM結構1021或傳導襯墊1022的面積大小來調整。
圖3A及圖5A是包含多個傳導襯墊1022的所述半導體晶片102之示意圖，其中所述傳導襯墊1022部分地分佈在所述半導體晶片102的一個中心區域111，以及部分地分佈在所述半導體晶片102的一個周邊區域112。所述周邊區域112是圍繞所述半導體晶片102邊緣的區域，所述周邊區域112具有寬度117，所述寬度117為最小傳導凸塊間距之約6倍。所述中心區域111是被所述周邊區域112環繞之所述半導體晶片102的區域。位於所述中心區域111的所述多個傳導襯墊114之間的距離大於位於週邊區域112的傳導襯墊113之間的距離。
圖3B是詳細示出本公開內容中的圖3A中半導體晶片102的截面圖，其中該示例性截面圖是從沿圖3A的線B-B'橫跨之平面而得到的。一些傳導凸塊103P被安裝在所述半導體晶片102的所述周邊區域112中的一些傳導襯墊113上。一些傳導凸塊103c被安裝在所述半導體晶片102的所述中心區域111中的一些傳導襯墊114上。所述傳導凸塊103經由所述導體107將所述半導體晶片102連接到所述基板101。為簡單起見，所述導體107在圖3A中被省略。在一些實施例中，在所述半導體晶片102的所述中心區域111的所述每個傳導凸塊103c的面積小於在所述半導體晶片102的所述周邊區域112的所述每個傳導凸塊103P的面積。在這樣的情況下，位於所述中心區域111的所述傳導凸塊103c的高度大於位於所述周邊區域112的所述傳導凸塊103P的高度。在一些實施例中，位於所述周邊區域112的所述傳導凸塊103P的面積與位於所述中心區域111的所述傳導凸塊103c的面積之比例介於約1.1至約2.67之間。位於所述周邊區域112的所述傳導凸塊103P的面積與位於所述中心區域111的所述傳導凸塊103c的面積之比例的限制是由多個實際的基板翹曲以及鑒於凸塊製造的工藝而確定。
返回參照圖2，所述傳導凸塊103的所述高度H是由所述傳導襯墊1022和相應的所述導線104的頂面104a之間的最小距離D確 定。在一些實施例中，所述傳導凸塊103的所述高度H被設計成與所述最小距離D成正比。一種正因數α被預先確定，以顯示D和H之間的依賴關係，且D和H之間的相關性被表達為：H=α x D，其中α大於0且小於1。
例如(沒有實施UBM結構)，如圖3B所示，所述傳導凸塊103p的所述高度Hp是由所述傳導襯墊113與其相應的導線104之間的最小距離確定。同樣地，所述傳導凸塊103c的所述高度Hc也是由所述傳導襯墊114與其相應的導線104之間的最小距離確定。因為所述高度Hp需要為比所述高度Hc小，位於所述周邊區域112的所述傳導襯墊113比位於中心區域111的所述傳導襯墊114具有更大的襯墊尺寸。
例如如圖2所示，所述半導體晶片102和所述基板101被認為基本上彼此平行，因此高度Hp可以基本上等於高度Hc。因此，位於中心區域111的所述UBM結構1021(或傳導襯墊)的面積大小基本上等於位於周邊區域112的所述UBM結構1021(或傳導襯墊)的面積大小。
對於一些實施例，如圖2中所示，所述基板101與所述半導體晶片102不以平行方式放置。例如如圖4A所示，所述基板101彎曲，但是所述半導體晶片102不彎曲。然而，應用於上述實例的設計規則(H=α x D)依然可以被採用。所述平坦半導體晶片102連接至一個具有凹狀頂面的基板101。因此，所述半導體晶片102的邊緣更接近所述基板101，或者說，所述半導體晶片102的周邊區域更接近所述基板101。位於所述周邊區域112上的所述傳導襯墊113和所述基板101之間的最小距離Dp小於位於所述中心區域111上的所述傳導襯墊114和所述基板101之間的距離Dc。所述傳導襯墊113的面積尺寸被設計成大於所述傳導襯墊114的面積尺寸。因此，所述中心區域111的所述傳導凸塊103c生成至比所述周邊區域112的所述傳導凸塊103p更大的高度。而 且，由於所述基板101是彎曲的，處於所述中心區域111的每個傳導襯墊114之間的最小距離均可以是不同的。例如，靠近所述中心區域111的所述傳導襯墊與靠近所述中心區域111邊緣的所述傳導襯墊相比更加接近所述基板101。
在一些實施例中，如圖4B中所示，所述半導體晶片102彎曲但是所述基板101不彎曲。然而，應用於上述實例的設計規則(H=α x D)依然可以被採用。平坦基板101連接至一個具有凸狀頂面的半導體晶片102，以使得所述半導體晶片102的周邊區域更接近所述基板101。位於所述周邊區域112上的所述傳導襯墊113和所述基板101的最小距離Dp小於位於所述中心區域111上的所述傳導襯墊114和所述基板101的距離Dc。所述傳導襯墊113的面積尺寸被設計成大於所述傳導襯墊114的面積尺寸。因此，所述中心區域111的傳導凸塊103c生成至比所述周邊區域112的傳導凸塊103p更大的高度。而且，由於所述半導體晶片102是彎曲的，處於所述中心區域111的所述每個傳導襯墊114之間的最小距離均可以是不同的。例如，靠近所述中心區域111的所述傳導襯墊與靠近所述中心區域111邊緣的所述傳導襯墊相比更加接近所述基板101。所述半導體晶片102的所述所有傳導凸塊以基於最小距離D的調整高度電連接到所述基板101。因此，可以避免產生虛焊(cold joint)。
圖5B是詳細示出本公開內容中的圖5A中半導體晶片102的截面圖，其中該示例性截面圖是從沿圖5A的線C-C'橫跨之平面而得到的。一些傳導凸塊103P被安裝在所述半導體晶片102的所述周邊區域112中的一些傳導襯墊113上。一些傳導凸塊103c被安裝在所述半導體晶片102的所述中心區域111中的一些傳導襯墊114上。所述傳導凸塊103經由所述導體107將所述半導體晶片102連接到所述基板101。為簡單起見，所述導體107在圖5A中被省略。在一些實施例中，在所述中 心區域111的所述每個傳導凸塊103c的面積大於在所述周邊區域112的所述每個傳導凸塊103P的面積。在這樣的情況下，位於所述中心區域111的所述傳導凸塊103c的高度小於位於所述周邊區域112的所述傳導凸塊103P的高度。在一些實施例中，位於所述周邊區域112的所述傳導凸塊103P的面積與位於所述中心區域111的所述傳導凸塊103c的面積之比例介於約0.17至約0.91之間。位於所述周邊區域112的所述傳導凸塊103P的面積與位於所述中心區域111的所述傳導凸塊103c的面積之比例的限制是由多個實際的基板翹曲以及鑒於凸塊製造的工藝而確定。
在一些實施例中，如圖6A中所示，所述基板101彎曲但是所述半導體晶片102不彎曲。然而，應用於上述實例的設計規則(H=α x D)依然可以被採用。平坦半導體晶片102連接至一個具有凸狀頂面的基板101。因此，所述半導體晶片102的中心更接近所述基板101，或者說，所述半導體晶片102的中心區域更接近所述基板101。所述傳導襯墊113和所述基板101之間的最小距離Dp大於位於所述中心區域111的所述傳導襯墊114與所述基板101之間的距離Dc。所述傳導襯墊113的面積尺寸被設計成小於所述傳導襯墊114的面積尺寸。因此，所述中心區域111的所述傳導凸塊103c被設計成比所述周邊區域112的所述傳導凸塊103p更小的高度。而且，由於所述基板101是彎曲的，處於所述中心區域111的所述每個傳導襯墊114之間的最小距離均可以是不同的。例如，靠近所述中心區域111的邊緣的所述傳導襯墊與靠近所述中心區域111的所述傳導襯墊相比更加接近所述基板101。所述傳導凸塊被設計成具有不同的高度，以使得所述半導體晶片102的所述所有傳導凸塊電連接到所述基板101。
在一些實施例中，如圖6B中所示，所述半導體晶片102彎曲但是所述基板101不彎曲。應用於上述實例的設計規則(H=α x D)依然可以被採用。平坦基板101連接至一個具有凹狀頂面的半導體晶片102。因此，所述半導體晶片102的中心區域更接近所述基板101。所述傳導襯墊113和所述基板101的最小距離Dp大於所述中心區域上的所述傳導襯墊114和所述基板101的距離Dc。所述傳導襯墊113的面積尺寸被設計成小於所述傳導襯墊114的面積尺寸。因此，所述中心區域111的傳導凸塊103c被設計成比所述周邊區域112的所述傳導凸塊103p更小的高度。而且，由於所述半導體晶片102是彎曲的，處於所述中心區域111的所述每個傳導襯墊114之間的最小距離均可以是不同的。例如，靠近所述中心區域111邊緣的所述傳導襯墊與靠近所述中心區域111的所述傳導襯墊相比更加接近所述基板101。所述半導體晶片102的所述所有傳導凸塊以基於最小距離D的調整高度電連接到所述基板101。因此，可以避免產生虛焊(cold joint)。
圖7是一種製造半導體結構方法的流程圖，如圖1中所示。在操作701中，提供一基板101，該基板包括導線104。在操作702中，提供半導體晶片102。在操作703中，傳導襯墊形成於所述半導體晶片102之表面上。在操作704中，所述傳導襯墊通過傳導凸塊103相應地與所述傳導跡線104電耦合。在操作705中，所述傳導襯墊103的一個高度被確定為所述傳導襯墊與相應的所述導線104之間的最小距離。
圖8A至圖8F示例性示出圖7所述的操作方法。圖8A中，提供基板101。圖8B中，導線104形成於所述基板101之表面106上，其中所述導線104直接覆蓋所述基板101。圖8A和8B示例性示出操作701。圖8C中，提供半導體晶片102。圖8C示例性示出操作702。圖8D中，傳導襯墊1022形成於所述半導體晶片102上。圖8D示例性示出操作703。圖8E中，傳導凸塊103形成於所述傳導襯墊1022上。圖8F中，在BOT配置中，所述傳導凸塊103電耦合到所述導線104(通過導體107)。圖8E及8F示例性示出操作704。
於半導體晶片上形成傳導襯墊有許多方法。例如，圖9A至圖9D示例性示出於半導體晶片上形成傳導襯第一特徵的一種方法。圖9A中，導電材料901形成於半導體晶片102之表面106上。圖9B中，掩模層902被圖案化，且形成於所述導電材料901上，以暴露所述導電材料901的一部分。圖9C中，所述導電材料901的所述暴露部分被蝕刻掉，且所述掩模層902被去除。所述導電材料901在所述半導體晶片102的所述周邊區域112上形成所述傳導襯墊113，並在所述半導體晶片102的所述中心區域111形成所述傳導襯墊114。在一些實施例中，所述傳導凸塊103P和103c是由在所述傳導襯墊上電鍍導電材料而形成。形成所述傳導襯墊和所述傳導凸塊的方法在圖9A-9D被說明，且該方法不視為一種限制。
在所述傳導襯墊上電鍍導電材料的一定時間內，電鍍到所述傳導襯墊上的所述導電材料901的總量是固定的。如果所述傳導襯墊的面積越大，相應的所述傳導凸塊的高度則越小。例如圖9E所示，當位於所述周邊區域112上的所述傳導襯墊113的面積大於位於所述中心區域111的所述傳導襯墊114的面積時，位於所述周邊區域112的所述傳導凸塊103p的高度小於位於所述中心區域111的所述傳導凸塊103c的高度。例如圖9F所示，當位於所述周邊區域112上的所述傳導襯墊113的面積小於位於所述中心區域111的所述傳導襯墊導114的面積時，位於所述周邊區域112的所述傳導凸塊103p的高度大於位於所述中心區域111的所述傳導凸塊103c的高度。基於所述傳導襯墊的可調面積，所述半導體晶片102的所述傳導凸塊的高度可以被設計為沒有間隙地使所述傳導凸塊電連接到所述基板101。
相比於圖9A至圖9F所示的示例，一些實施例進一步具有額外的UBM結構，該額外的UBM結構設置在所述傳導襯墊上。掩模可在形成UBM之前設置在所述傳導襯墊上。所述掩模的圖案被設計成具 有不同尺寸的凹槽，以形成具有不同面積尺寸的UBM。為了UBM的形成，可以採用電鍍以在凹槽中填充導電材料。與傳導襯墊相同，所述依次形成的傳導凸塊的高度也取決於UBM的面積尺寸，其中所述傳導凸塊置於UMB之上。所述UBM面積尺寸越大，在UBM上的所述傳導凸塊越短。
在一些實施例中，傳導凸塊是由在傳導襯墊上電鍍導電材料而形成。在一些實施例中，電耦合所述傳導襯墊和所述傳導凸塊包括於所述半導體晶片的所述傳導凸塊上塗覆焊料材料，且包括回流焊料材料。一些實施例中，於所述半導體晶片上形成所述傳導凸塊包括形成所述傳導凸塊，所述傳導凸塊相應地放置在所述半導體晶片的所述中心區域和所述周邊區域的所述傳導襯墊上。
本公開內容的一些實施方案提供一種半導體結構，其包括：基板，其包括多個導線；半導體晶片，所述半導體晶片包括表面，其朝向所述多個導線；以及多個傳導襯墊，其位於所述表面之上以及通過多個傳導凸塊與所述多個導線對應地電連接。每個所述多個傳導凸塊的一個高度是由所述多個傳導襯墊和相應的所述導線之間的最小距離確定。
本公開內容中的一些實施例提供了一種半導體結構，該半導體結構包括基板。所述基板包括多個導線，所述多個導線覆蓋在所述基板之表面上；以及一個半導體晶片。所述半導體晶片經由多個傳導凸塊電連接到所述多個導線。所述多個傳導凸塊部分地分佈在所述半導體晶片的一個中心區域，以及部分地分佈在所述半導體晶片的一個周邊區域。位於所述中心區域的所述多個傳導凸塊與位於所述位於周邊區域的所述多個傳導凸塊具有不同的高度。
本公開內容中的一些實施例提供一種形成半導體結構的方法。該方法包括提供一個包括多個導線的基板；提供一個半導體晶 片；形成多個傳導襯墊於所述半導體晶片之表面上；通過多個傳導凸塊，所述多個傳導襯墊和所述多個導線對應地電耦合；以及確定每個所述多個傳導凸塊的一個高度為所述多個傳導襯墊和相應的導線之間的一個最小距離。
前述概述了幾個實施例的特徵，使得本領域技術人員可以更好地理解本公開內容的各個方面。本領域技術人員應當理解，他們可以容易地使用本公開作為用於實現相同目的和/或實現本文所介紹的實施例的相同的優點設計或修改其他過程和結構的基礎。本領域技術人員也應該認識到，這樣的等效構造不偏離本公開內容的精神和範圍，並且它們可以在此不脫離本公開的精神和範圍的前提下進行各種改變，替換和變更。
100‧‧‧半導體結構
101‧‧‧基板
102‧‧‧半導體晶片
102a‧‧‧半導體晶片表面
103‧‧‧傳導凸塊
104‧‧‧導線
104a‧‧‧導線頂面
105‧‧‧凹槽
106‧‧‧表面
107‧‧‧導體
108‧‧‧導電材料
1011‧‧‧多層次金屬結構
1012‧‧‧焊接掩模
1013‧‧‧球墊
1014‧‧‧焊料球
1021‧‧‧下傳導凸塊冶金(UBM)結構
1022‧‧‧傳導襯墊
1023‧‧‧鈍化層
H‧‧‧傳導凸塊與UBM結構之間的介面到 傳導凸塊與導體之間的介面的距離
D‧‧‧傳導襯墊和相應的導線的頂面之間 的最小距離

Claims (10)

  1. 一種半導體結構，其包括：基板，其包括多個導線；以及半導體晶片，所述半導體晶片包括：表面，其朝向所述多個導線；以及多個傳導襯墊，其位於所述表面之上以及通過多個傳導凸塊與所述多個導線對應地電連接，其中每個所述多個傳導凸塊的一個高度是由所述多個傳導襯墊和相應的所述導線之間的最小距離確定。
  2. 根據請求項1所述的半導體結構，其中所述多個導線直接覆蓋於所述基板上或與包含導電材料的凹槽相連接。
  3. 根據請求項1所述的半導體結構，其中所述基板的熱膨脹係數與所述半導體晶片的熱膨脹係數不同。
  4. 一種半導體結構，其包括：基板，所述基板包括多個導線，所述多個導線覆蓋於所述基板之表面上；以及半導體晶片，所述半導體晶片經由多個傳導凸塊電連接到所述多個導線，其中所述多個傳導凸塊部分地分佈在所述半導體晶片的中心區域，以及部分地分佈在所述半導體晶片的周邊區域，且位於所述中心區域的所述多個傳導凸塊與位於所述周邊區域的所述多個傳導凸塊具有不同的高度。
  5. 根據請求項4所述的半導體結構，其中當位於所述中心區域的所述多個傳導凸塊的面積小於位於所述周邊區域的所述多個傳導凸塊的面積時，位於所述中心區域的所述多個傳導凸塊的高度大於位於所述周邊區域的所述多個傳導凸塊的高度。
  6. 根據請求項4所述的半導體結構，其中位於所述中心區域的所述多個傳導凸塊的高度小於位於所述周邊區域的所述多個傳導凸塊的高度時，位於所述中心區域的所述多個傳導凸塊的面積大於位於所述周邊區域的所述多個傳導凸塊的面積。
  7. 根據請求項4所述的半導體結構，其中位於所述中心區域的所述多個傳導凸塊之間的距離大於位於所述周邊區域的所述多個傳導凸塊之間的距離。
  8. 一種形成半導體結構的方法，其包括：提供一個包括多個導線的基板；提供一個半導體晶片；形成多個傳導襯墊於所述半導體晶片之表面上；通過多個傳導凸塊，所述多個傳導襯墊和所述多個導線對應地電耦合；以及確定每個所述多個傳導凸塊的一個高度為所述多個傳導襯墊和相應的導線之間的一個最小距離。
  9. 根據請求項8所述的方法，其進一步包括形成所述多個導線，所述多個導線直接覆蓋於所述基板上，且所述多個導線連接凹槽，所述凹槽包含導電材料。
  10. 根據請求項8所述的方法，其中於所述半導體晶片上形成所述多個傳導凸塊包括形成所述多個傳導凸塊，所述多個傳導凸塊相應地放置在所述半導體晶片的所述中心區域和所述周邊區域的所述多個傳導襯墊上。
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US9679862B2 (en) 2017-06-13
TWI591785B (zh) 2017-07-11
KR101772284B1 (ko) 2017-08-28
KR20160064965A (ko) 2016-06-08
US20170263583A1 (en) 2017-09-14
US10163844B2 (en) 2018-12-25
US20160155715A1 (en) 2016-06-02

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