TW201611202A - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TW201611202A
TW201611202A TW103130721A TW103130721A TW201611202A TW 201611202 A TW201611202 A TW 201611202A TW 103130721 A TW103130721 A TW 103130721A TW 103130721 A TW103130721 A TW 103130721A TW 201611202 A TW201611202 A TW 201611202A
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Taiwan
Prior art keywords
layer
semiconductor package
encapsulation layer
circuit
fabricating
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TW103130721A
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English (en)
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TWI611523B (zh
Inventor
邱士超
林俊賢
孫銘成
白裕呈
沈子傑
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矽品精密工業股份有限公司
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Priority to TW103130721A priority Critical patent/TWI611523B/zh
Priority to CN201410507705.2A priority patent/CN105514053B/zh
Priority to US14/603,844 priority patent/US20160071780A1/en
Publication of TW201611202A publication Critical patent/TW201611202A/zh
Application granted granted Critical
Publication of TWI611523B publication Critical patent/TWI611523B/zh
Priority to US15/968,093 priority patent/US20180247891A1/en

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Abstract

一種半導體封裝件之製法，係先提供一設有線路層與阻塊之承載件，再形成一具有相對之第一表面及第二表面的封裝層於該承載件上，使該封裝層包覆該線路層與該阻塊，且該第一表面結合於該承載件上，之後移除該承載件與該阻塊，以令該封裝層之第一表面上形成開口，供電子元件設於其中，故於置放該電子元件之前，可先對線路層與該電子元件分別進行測試，以淘汰不良品，因而能避免將半導體封裝件整體報廢而造成材料浪費之問題。

Description

半導體封裝件及其製法
本發明係有關一種封裝製程，特別是關於一種半導體封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品亦朝著輕、薄、短、小、高積集度、多功能化方向發展。而為滿足封裝結構高積集度(Integration)以及微型化(Miniaturization)的封裝需求，封裝基版除了導入球柵陣列(BGA)的設計，封裝形式逐漸由打線式(Wire Bonding)封裝或覆晶式(Flip Chip,FC)封裝進展到直接在一封裝基板(packaging substrate)中嵌埋並電性整合一例如具有積體電路之半導體晶片，此種封裝件能縮減整體半導體裝置之體積並提昇電性功能。
如第1圖所示，習知嵌埋式半導體封裝件1包括：一具有相對第一及第二表面10a,10b及貫穿該第一及第二表面10a,10b之開口100之核心板10、設於該開口100中之晶片11、設於該核心板10之第一及第二表面10a,10b與晶片11上之線路增層結構13、以及設於該線路增層結構13上之防銲層16。
所述之晶片11具有作用面11a及非作用面11b，於該作用面11a上具有複數電極墊110，且藉由黏著材12填充於該開口100，以固定該晶片11於該開口100中。
所述之線路增層結構13具有至少一介電層130、設於該介電層130上之線路層131、及複數設於該介電層130中並電性連接該電極墊100與線路層131之導電盲孔132。
所述之防銲層16具有複數開孔160，以令該線路層131之部分表面外露於各該開孔160中，俾供作為電性接觸墊以外接其他電子裝置。
惟，習知半導體封裝件1中，因整體結構包含核心板10，導致增加整體結構之厚度，而難以符合薄化之需求，且需考量該核心板之製作成本，因而難以降低整體製作成本。
再者，習知半導體封裝件1之製法需先埋設該晶片11，待製作該線路增層結構13後，才進行測試，故當測試後該半導體封裝件1為不良品時，不論晶片11、該線路增層結構13或核心板10好壞與否，均需將該半導體封裝件1整體報廢，導致材料浪費，且大幅提高製作成本。
再者，該晶片11需經由各該線路層131才能電性連接外部的電子元件，導致訊號傳遞路徑冗長，因而降低該半導體封裝件1之電性效能。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明提供一種半導體封裝件，係包括：封裝層，係具有相對之第一表面與第二表面，且該封裝層之第一表面上具有至少一開口；線路層，係形成於該封裝層之第一表面且嵌埋於該封裝層中；以及至少一電子元件，係設於該開口中並外露出該第一表面。
前述之半導體封裝件中，該開口未連通至該第二表面。
前述之半導體封裝件中，該電子元件未外露出該第二表面。
本發明亦提供一種半導體封裝件之製法，係包括：提供一具有線路層之承載件；形成至少一阻塊於該承載件上；形成一具有相對之第一表面及第二表面的封裝層於該承載件上，使該封裝層包覆該線路層與該阻塊，且該第一表面結合於該承載件上；移除該承載件與該阻塊，以令該封裝層之第一表面上形成開口；以及設置至少一電子元件於該開口中。
前述之製法中，該阻塊係以金屬電鍍方式或網版印刷方式形成者。
前述之半導體封裝件及其製法中，該封裝層係以模壓製程或壓合製程形成者，故形成該封裝層之材質係為封裝膠材、介電材或感光型絕緣材。
前述之半導體封裝件及其製法中，復包括形成線路結構於該封裝層之第二表面上，且該線路結構電性連接該線 路層。又包括形成絕緣保護層於該封裝層之第二表面上，且供部分該線路結構外露出該絕緣保護層。另外，該線路結構具有形成於該封裝層中之複數導電柱，以供該線路結構藉該些導電柱電性連接該線路層，且該導電柱係為先以雷射方式、機械鑽孔方式或曝光顯影方式於該封裝層之第二表面上形成複數通孔，再形成導電材於各該通孔中。
前述之半導體封裝件及其製法中，復包括形成絕緣保護層於該封裝層之第一表面上，且供部分該線路層外露出該絕緣保護層。
前述之半導體封裝件及其製法中，復包括設置堆疊件於該封裝層之第一表面上，且該堆疊件電性連接該線路層或電子元件。
前述之半導體封裝件及其製法中，復包括設置堆疊件於該封裝層之第二表面上。
另外，前述之半導體封裝件及其製法中，復包括形成線路重佈結構於該封裝層之第一表面與該線路層上或第二表面上。
由上可知，本發明之半導體封裝件及其製法中，藉由無習知核心板之設計，以減少整體結構之厚度，且降低成本。
再者，藉由在該封裝層中設置阻塊，之後再移除該阻塊，以形成開口，故於置放該電子元件之前，可先對線路層與該電子元件分別進行測試，以淘汰不良品，因而能避免將半導體封裝件整體報廢而造成材料浪費之問題。
又，該電子元件可與該堆疊件直接電性連接，而無需經由該線路層，故能縮短訊號傳遞路徑，以提高該半導體封裝件之電性效能。
1,2,4,5‧‧‧半導體封裝件
10‧‧‧核心板
10a,20a‧‧‧第一表面
10b,20b‧‧‧第二表面
100,200‧‧‧開口
11‧‧‧晶片
11a‧‧‧作用面
11b‧‧‧非作用面
110‧‧‧電極墊
12,22‧‧‧黏著材
13‧‧‧線路增層結構
130,400,500‧‧‧介電層
131,23‧‧‧線路層
132‧‧‧導電盲孔
16‧‧‧防銲層
160,260‧‧‧開孔
20‧‧‧封裝層
21‧‧‧電子元件
210‧‧‧電極
230‧‧‧電性接觸墊
231‧‧‧導電跡線
24‧‧‧導電層
25‧‧‧線路結構
250‧‧‧導電柱
26‧‧‧絕緣保護層
27‧‧‧導電元件
28‧‧‧阻塊
29‧‧‧承載件
290‧‧‧結合層
3‧‧‧堆疊封裝單元
30‧‧‧堆疊件
40,50‧‧‧線路重佈結構
401,501‧‧‧線路部
A‧‧‧置放區
第1圖係為習知半導體封裝件之剖面示意圖；第2A至2G圖係為本發明半導體封裝件之製法之剖視示意圖；第3圖係為第2G圖之後續製程；以及第4及5圖係分別為第2G圖之不同實施例。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“左”、“右”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2G圖係為本發明無核心式(coreless)半導體封裝件2之製法之剖視示意圖。
如第2A圖所示，提供一具有結合層290之承載件29，再形成一線路層23於該承載件29之結合層290上。
於本實施例中，該承載件29可選用金屬板、半導體晶圓或玻璃板，且該結合層290係為離形膜、黏著材或絕緣材等，該結合層290亦可為複合材料，如箔片(foil)上具有晶種層(seed layer)。
再者，該承載件29係定義有一置放區A，使該線路層23位於該置放區A外。
又，該線路層23係包含複數導電跡線231與複數電性接觸墊230，且該線路層23以電鍍或其它方式製作，並無特別限制。
如第2B圖所示，形成一阻塊28於該承載件29之置放區A之結合層290上。
於本實施例中，該阻塊28係以金屬電鍍方式形成者，亦可以網版印刷(screen printing)高分子材料的方式形成。
如第2C圖所示，形成一封裝層20於該結合層290上以覆蓋該線路層23與該阻塊28，使該線路層23嵌埋於該封裝層20中。
於本實施例中，該封裝層20具有相對之第一表面20a及第二表面20b，且該第一表面20a結合於該結合層290上。
再者，該封裝層20係以模壓(molding)或壓合 (laminate)製程形成者，且該封裝層20之材質係為封裝膠體、介電材或感光型絕緣材，但並不限於此。
又，於該封裝層20之第二表面20b上復可壓合一導電層24，以利於後續製作線路。例如，係先壓合如銅箔之導電層24於該封裝層20之第二表面20b上，再將該導電層24與該封裝層20一併結合於該結合層290上。或者，亦可先壓合該封裝層20於該結合層290上，再將該導電層24形成於該封裝層20上。
另外，於另一實施例中，可於封裝層20之第二表面20b上濺鍍形成該導電層24。
如第2D圖所示，利用該導電層24以電鍍形成一線路結構25於該封裝層20之第二表面20b上，且該線路結構25具有形成於該封裝層20中之導電柱250，以電性連接該線路層23之電性接觸墊230。
於本實施例中，該導電柱250之製作可先以雷射方式於該封裝層20之第二表面20b上形成通孔，再於該通孔中形成導電材。或者，以感光型材料製作該封裝層20，再以曝光顯影方式形成通孔，之後於該通孔中形成導電材。
如第2E圖所示，移除多餘之導電層24，且移除該承載件29、結合層290與該阻塊28，以令該封裝層20之第一表面20a上於對應該置放區A之處形成開口200。
於本實施例中，係移除該線路結構25以外之導線層24，即保留該線路結構25下之導線層24。
如第2F圖所示，分別形成一如防銲層之絕緣保護層 26於該封裝層20之第一與第二表面20a,20b上，且該些絕緣保護層26具有複數開孔260，以令該些電性接觸墊230與該線路結構25之部分表面(作為電性連接墊251)外露於各該開孔260，供接置其它外部元件。
如第2G圖所示，設置至少一電子元件21於該開口200內，且藉由黏著材22填充於該開口200中，以固定該電子元件21於該開口200中。
於本實施例中，該電子元件21係為主動元件、被動元件或其組合者，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。於此，該電子元件21係為被動元件，其左、右兩側具有電極210。
再者，該電子元件21亦可依需求藉由打線方式(wire bonding)電性連接該線路層23。
於後續製程中，如第3圖所示，該線路層23(即該電性接觸墊230)與該電子元件21之電極210可藉由複數如銲錫材料或銅柱之導電元件27接置一堆疊件30，以形成一堆疊封裝單元3。
於本實施例中，該堆疊件30係為封裝基板、半導體晶片、晶圓、中介板或封裝件。
再者，於其它實施例中，亦可於該封裝層20之第二表面20b與該線路結構25上接置其它電子裝置。
另外，如第4圖所示，於移除多餘之導電層24後，可進行線路重佈層(redistribution layer,RDL)製程，以形成一線路重佈結構40於該封裝層20之第二表面20b上，且 該線路重佈結構40電性連接該線路結構25。之後，再形成該絕緣保護層26於該線路重佈結構40上，且該些絕緣保護層26外露出該線路重佈結構40之部分表面，供後續製程中接置其它外部元件。
或者，如第5圖所示，移除該承載件29、結合層290與該阻塊28之後，可進行線路重佈層(redistribution layer,RDL)製程，以形成一線路重佈結構50於該封裝層20之第一表面20a上，且該線路重佈結構50電性連接該線路層23。之後，再形成該絕緣保護層26於該線路重佈結構50上，且該些絕緣保護層26外露出該線路重佈結構50之部分表面，供後續製程中接置其它外部元件。需注意，該線路重佈結構50不會覆蓋該開口200之上方，以供後續放置該電子元件21。
於本實施例中，該線路重佈結構40,50係包含相疊之至少一線路部401,501與至少一介電層400,500，該介電層400,500係形成於該封裝層20上，且該線路部401,501係作為電性連接之用。
本發明之半導體封裝件2並無習知核心板，故能減少整體結構之厚度，且可降低成本。
再者，本發明之製法中，係藉由預留該電子元件21之放置空間，即於封裝層20中設置阻塊28，之後再移除該阻塊28，以形成置放該電子元件21之開口200，故於置放該電子元件21之前，可先對線路層23(或線路結構25)與該電子元件21分別進行測試，以淘汰不良品，如此即可 避免將不良之半導體封裝件2整體報廢而造成材料浪費，藉以節省成本。
又，該電子元件21可與該堆疊件30直接電性連接，而無需經由該線路層23，故能縮短該堆疊封裝單元3之訊號傳遞路徑，以提高該堆疊封裝單元3之電性效能。
本發明復提供一種半導體封裝件2，係包括：一封裝層20、一線路層23以及至少一電子元件21。
所述之封裝層20係具有相對之第一表面20a與第二表面20b，且該封裝層20之第一表面20a上具有至少一開口200，該開口200未連通至該第二表面20b。再者，該封裝層20之材質係為封裝膠體、介電材或感光型絕緣材。
所述之線路層23係形成於該封裝層20之第一表面20a且嵌埋於該封裝層20中。
所述之電子元件21係設於該開口200中並外露出該第一表面20a，且該電子元件21未外露出該第二表面20b。該電子元件21係為主動元件、被動元件或其組合者。
於一實施例中，所述之半導體封裝件2復包括一線路結構25，係形成於該封裝層20之第二表面20b上且電性連接該線路層23。又包括一絕緣保護層26，係形成於該封裝層20之第二表面20b上且外露出該線路結構25之部分表面。
於一實施例中，所述之半導體封裝件2復包括一絕緣保護層26，係形成於該封裝層20之第一表面20a上且外露出該線路層23之部分表面。
於一實施例中，所述之半導體封裝件2復包括複數導電元件27，係形成於該線路層23之部分表面上。
於一實施例中，所述之半導體封裝件2復包括複數導電元件27，係形成於該電子元件21上。
於一實施例中，該封裝層20之第一表面20a上設有堆疊件30，且該堆疊件30電性連接該線路層23或電子元件21。
於一實施例中，該封裝層20之第二表面20b上設有堆疊件30，且該堆疊件30電性連接該線路結構25。
於一實施例中，所述之半導體封裝件4復包括線路重佈結構40，係形成於該封裝層20之第二表面20b上。
於一實施例中，所述之半導體封裝件5復包括線路重佈結構50，係形成於該封裝層20之第一表面20a上。
綜上所述，本發明之半導體封裝件及其製法，藉由無核心式之設計，以降低整體結構之厚度而達到薄化之需求，且降低成本。
再者，藉由預留該電子元件之放置空間，以於置放該電子元件之前，先對線路層與該電子元件分別進行測試，藉此淘汰不良品，故能避免將半導體封裝件整體報廢而造成材料浪費之問題。
又，藉由先佈線再設置電子元件之方式，使該電子元件能直接電連接該堆疊件，而無需經由線路層，故能縮短訊號傳遞路徑，以提高電性效能。
上述實施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
20‧‧‧封裝層
20a‧‧‧第一表面
20b‧‧‧第二表面
23‧‧‧線路層
230‧‧‧電性接觸墊
24‧‧‧導電層
25‧‧‧線路結構
250‧‧‧導電柱
28‧‧‧阻塊
29‧‧‧承載件
290‧‧‧結合層

Claims (25)

  1. 一種半導體封裝件，係包括：封裝層，係具有相對之第一表面與第二表面，且該封裝層之第一表面上具有至少一開口；線路層，係形成於該封裝層之第一表面且嵌埋於該封裝層中；以及至少一電子元件，係設於該開口中並外露出該第一表面。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該開口未連通至該第二表面。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，形成該封裝層之材質係為封裝膠材、介電材或感光型絕緣材。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該電子元件未外露出該第二表面。
  5. 如申請專利範圍第1項所述之半導體封裝件，復包括線路結構，係形成於該封裝層之第二表面上且電性連接該線路層。
  6. 如申請專利範圍第5項所述之半導體封裝件，復包括絕緣保護層，係形成於該封裝層之第二表面上且外露出該線路結構之部分表面。
  7. 如申請專利範圍第1項所述之半導體封裝件，復包括絕緣保護層，係形成於該封裝層之第一表面上且外露出該線路層之部分表面。
  8. 如申請專利範圍第1項所述之半導體封裝件，復包括複數導電元件，係形成於該線路層之部分表面上。
  9. 如申請專利範圍第1項所述之半導體封裝件，復包括複數導電元件，係形成於該電子元件上。
  10. 如申請專利範圍第1項所述之半導體封裝件，復包括堆疊件，係設於該封裝層之第一表面上且電性連接該線路層或電子元件。
  11. 如申請專利範圍第1項所述之半導體封裝件，復包括堆疊件，係設於該封裝層之第二表面上。
  12. 如申請專利範圍第1項所述之半導體封裝件，復包括線路重佈結構，係形成於該封裝層之第一表面與該線路層上。
  13. 如申請專利範圍第1項所述之半導體封裝件，復包括線路重佈結構，係形成於該封裝層之第二表面上。
  14. 一種半導體封裝件之製法，係包括：提供一具有線路層之承載件；形成至少一阻塊於該承載件上；形成一具有相對之第一表面及第二表面的封裝層於該承載件上，使該封裝層包覆該線路層與該阻塊，且該第一表面結合於該承載件上；移除該承載件與該阻塊，以令該封裝層之第一表面上形成開口；以及設置至少一電子元件於該開口中。
  15. 如申請專利範圍第14項所述之半導體封裝件之製法， 其中，該封裝層係以模壓製程或壓合製程形成者。
  16. 如申請專利範圍第14項所述之半導體封裝件之製法，其中，該阻塊係以金屬電鍍方式或網版印刷方式形成者。
  17. 如申請專利範圍第14項所述之半導體封裝件之製法，復包括形成線路結構於該封裝層之第二表面上，並令該線路結構電性連接至該線路層。
  18. 如申請專利範圍第17項所述之半導體封裝件之製法，其中，該線路結構具有形成於該封裝層中之複數導電柱，以供該線路結構藉該些導電柱電性連接該線路層。
  19. 如申請專利範圍第18項所述之半導體封裝件之製法，其中，該導電柱係為先以雷射方式、機械鑽孔方式或曝光顯影方式於該封裝層之第二表面上形成複數通孔，再形成導電材於各該通孔中。
  20. 如申請專利範圍第17項所述之半導體封裝件之製法，復包括形成絕緣保護層於該封裝層之第二表面上，且供部分該線路結構外露出該絕緣保護層。
  21. 如申請專利範圍第14項所述之半導體封裝件之製法，復包括形成絕緣保護層於該封裝層之第一表面上，且供部分該線路層外露出該絕緣保護層。
  22. 如申請專利範圍第14項所述之半導體封裝件之製法，復包括設置堆疊件於該封裝層之第一表面上，且令該堆疊件電性連接至該線路層或電子元件。
  23. 如申請專利範圍第14項所述之半導體封裝件之製法， 復包括設置堆疊件於該封裝層之第二表面上。
  24. 如申請專利範圍第14項所述之半導體封裝件之製法，復包括形成線路重佈結構於該封裝層之第一表面上。
  25. 如申請專利範圍第14項所述之半導體封裝件之製法，復包括形成線路重佈結構於該封裝層之第二表面上。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI651788B (zh) * 2016-08-29 2019-02-21 上海兆芯集成電路有限公司 電子結構以及電子結構陣列

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI559829B (zh) * 2014-10-22 2016-11-21 矽品精密工業股份有限公司 封裝結構及其製法
US10490880B2 (en) * 2017-05-26 2019-11-26 Qualcomm Incorporation Glass-based antenna array package
KR102509644B1 (ko) 2018-11-20 2023-03-15 삼성전자주식회사 패키지 모듈
US20210057397A1 (en) * 2019-08-20 2021-02-25 Qualcomm Incorporated Electrodeless passive embedded substrate

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002261190A (ja) * 2001-02-28 2002-09-13 Sony Corp 半導体装置、その製造方法及び電子機器
US8193034B2 (en) * 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
US20080136002A1 (en) * 2006-12-07 2008-06-12 Advanced Chip Engineering Technology Inc. Multi-chips package and method of forming the same
US20100073894A1 (en) * 2008-09-22 2010-03-25 Russell Mortensen Coreless substrate, method of manufacturing same, and package for microelectronic device incorporating same
JP5026400B2 (ja) * 2008-12-12 2012-09-12 新光電気工業株式会社 配線基板及びその製造方法
TWI417993B (zh) * 2009-02-04 2013-12-01 Unimicron Technology Corp 具凹穴結構的封裝基板、半導體封裝體及其製作方法
TWI387027B (zh) * 2009-02-16 2013-02-21 Advanced Semiconductor Eng 無核心封裝基板及其製造方法
TWI377653B (en) * 2009-02-16 2012-11-21 Unimicron Technology Corp Package substrate strucutre with cavity and method for making the same
US8049114B2 (en) * 2009-03-22 2011-11-01 Unimicron Technology Corp. Package substrate with a cavity, semiconductor package and fabrication method thereof
KR20110039879A (ko) * 2009-10-12 2011-04-20 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
KR101095130B1 (ko) * 2009-12-01 2011-12-16 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
JP5711472B2 (ja) * 2010-06-09 2015-04-30 新光電気工業株式会社 配線基板及びその製造方法並びに半導体装置
CN102376675B (zh) * 2010-08-04 2015-11-25 欣兴电子股份有限公司 嵌埋有半导体元件的封装结构及其制法
AT13055U1 (de) * 2011-01-26 2013-05-15 Austria Tech & System Tech Verfahren zur integration eines elektronischen bauteils in eine leiterplatte oder ein leiterplatten-zwischenprodukt sowie leiterplatte oder leiterplatten-zwischenprodukt
CN102694102B (zh) * 2011-03-22 2014-11-05 展晶科技(深圳)有限公司 发光二极管封装结构及其制造方法、以及光源装置
KR101298280B1 (ko) * 2011-10-25 2013-08-26 삼성전기주식회사 임베디드 인쇄회로기판 및 이의 제조 방법
JP6029342B2 (ja) * 2012-06-15 2016-11-24 新光電気工業株式会社 配線基板及びその製造方法
CN103906370B (zh) * 2012-12-27 2017-01-11 碁鼎科技秦皇岛有限公司 芯片封装结构、具有内埋元件的电路板及其制作方法
US20150118770A1 (en) * 2013-10-28 2015-04-30 Avago Technologies General Ip (Singapore) Pte. Ltd. Wafer-level packages having voids for opto-electronic devices
KR20150065029A (ko) * 2013-12-04 2015-06-12 삼성전기주식회사 인쇄회로기판, 그 제조방법 및 반도체 패키지
US9595485B2 (en) * 2014-06-26 2017-03-14 Nxp Usa, Inc. Microelectronic packages having embedded sidewall substrates and methods for the producing thereof
US9913385B2 (en) * 2015-07-28 2018-03-06 Bridge Semiconductor Corporation Methods of making stackable wiring board having electronic component in dielectric recess

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI651788B (zh) * 2016-08-29 2019-02-21 上海兆芯集成電路有限公司 電子結構以及電子結構陣列

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