TW201523753A - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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TW201523753A
TW201523753A TW103124970A TW103124970A TW201523753A TW 201523753 A TW201523753 A TW 201523753A TW 103124970 A TW103124970 A TW 103124970A TW 103124970 A TW103124970 A TW 103124970A TW 201523753 A TW201523753 A TW 201523753A
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processed
tray
objects
wiring substrate
sealing resin
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TWI546871B (zh
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Yoshiaki Goto
Takashi Imoto
Takeshi Watanabe
Yuusuke Takano
Yusuke Akada
Yuji Karakane
Yoshinori Okayama
Akihiko Yanagida
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Toshiba Kk
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Abstract

本發明提供一種可提高導電性屏蔽層之形成性且可降低形成成本之半導體裝置之製造方法。 於實施形態之製造方法中，準備：複數個半導體封裝體20，其等包括作為被處理物而搭載於配線基板上之半導體晶片及密封樹脂層；以及托盤21，其包括複數個被處理物收納部22。於被處理物收納部22內，形成有包括具有底面之非貫通孔之凹陷部30。將半導體封裝體20分別配置於複數個被處理物收納部22內。對收納於托盤21之半導體封裝體20濺鍍金屬材料而形成導電性屏蔽層。

Description

半導體裝置之製造方法 [相關申請案]
本申請案係享受將日本專利申請案2013-258705號(申請日：2013年12月13日)作為基礎申請案之優先權。本申請案係藉由參照該基礎申請案而包含基礎申請案之全部內容。
本發明之實施形態係關於一種半導體裝置之製造方法。
對於用於通信設備等之半導體裝置，為了抑制EMI(Electro Magnetic Interference，電磁干擾)等電磁波干擾，而使用利用導電性屏蔽層覆蓋封裝體表面之構造。作為具有屏蔽功能之半導體裝置，已知有如下構造，即：於具有將搭載於配線基板上之半導體晶片密封之密封樹脂層的半導體封裝體中，沿著密封樹脂層之上表面及側面設置有導電性屏蔽層。作為導電性屏蔽層之形成方法，可使用鍍敷法、濺鍍法、導電膏之塗佈法等。導電性屏蔽層之形成方法中之鍍敷法具有預處理步驟、鍍敷處理步驟、水洗般之後處理步驟等濕式步驟，故而無法避免半導體裝置之製造成本之上升。又，導電膏之塗佈法亦因對密封樹脂層之側面之塗佈步驟等，而半導體裝置之製造成本容易上升。
濺鍍法為乾式步驟，故而可減少導電性屏蔽層之形成步驟數或形成成本等。於將濺鍍法應用於導電性屏蔽層之形成之情形時，對在使半導體封裝體單片化之前形成導電性屏蔽層進行研究。於此種情形 時，首先，於將半導體晶片搭載於多孔(multi-cavity)之集合基板之各配線基板區域之後，將複數個半導體晶片統一地進行樹脂密封。繼而，將密封樹脂層與集合基板之一部分切斷而形成半切槽。半切槽係以配線基板區域之接地配線於側面露出之方式形成。藉由對具有半切槽之樹脂密封體濺鍍金屬材料而形成導電性屏蔽層。於密封樹脂層之側面及配線基板區域之側面之一部分，介隔半切槽而濺鍍金屬材料。
半切槽之寬度存在限制，故而於介隔半切槽濺鍍金屬材料之情形時，鄰接之半導體封裝體成為阻礙，有無法利用導電性屏蔽層充分地覆蓋密封樹脂層或配線基板區域之側面之虞。若利用足夠之厚度之導電性屏蔽層覆蓋密封樹脂層或配線基板區域之側面，則金屬材料較厚地堆積於不存在障礙物之密封樹脂層之上表面，而導電性屏蔽層之形成成本增加。又，厚度較薄之集合基板之半切之切口深度難以控制，根據情況，有導致半導體封裝體單片化之虞。根據此種情況，尋求當應用濺鍍法於封裝體表面形成導電性屏蔽層時，更確實且低成本地形成導電性屏蔽層之技術。
本發明所欲解決之問題在於提供一種當應用濺鍍法於封裝體表面形成導電性屏蔽層時，可提高導電性屏蔽層之形成性之半導體裝置之製造方法。
實施形態之半導體裝置之製造方法包括如下步驟：準備複數個被處理物，上述複數個被處理物包括配線基板、搭載於配線基板上之半導體晶片、以及以將半導體晶片密封之方式設置於配線基板上之密封樹脂層；準備托盤，上述托盤包括複數個被處理物收納部、以及分別設置於複數個被處理物收納部內之凹陷部；以密封樹脂層之上表面及側面與配線基板之側面之至少一部分露出之方式，將被處理物分別配置於托盤之被處理物收納部內；及將收納有複數個被處理物之托盤 載置於濺鍍裝置之平台上，對複數個被處理物濺鍍金屬材料，藉此形成覆蓋密封樹脂層之上表面及側面與配線基板之側面之至少一部分之導電性屏蔽層。凹陷部包括具有底面之非貫通孔。
1‧‧‧半導體裝置
2‧‧‧配線基板
2a‧‧‧第1面
3‧‧‧半導體晶片
4‧‧‧密封樹脂層
5‧‧‧導電性屏蔽層
5X‧‧‧無用之金屬膜
6‧‧‧絕緣基材
7‧‧‧內部連接端子
8‧‧‧外部連接端子
9‧‧‧阻焊層
10‧‧‧接地配線
11‧‧‧接著層
12‧‧‧電極墊
13‧‧‧接合線
20、40‧‧‧半導體封裝體
21、21A、21B‧‧‧托盤
22‧‧‧處理物收納部
22X‧‧‧被處理物收納部
23‧‧‧吸附部
24‧‧‧凹部
25‧‧‧壁狀部
25A、25B、25C、25D‧‧‧壁狀部
26、28‧‧‧肋部
27‧‧‧凸部
29‧‧‧傾斜部
30‧‧‧含有非貫通孔之凹陷部
30A‧‧‧含有貫通孔之凹陷部
31‧‧‧第1卡合部
32‧‧‧第2卡合部
33‧‧‧被處理物之位置修正部
34‧‧‧楔形部
35‧‧‧濺鍍裝置之平台
36‧‧‧抗附著板
41‧‧‧凸塊電極
圖1係表示藉由第1實施形態之製造方法所製造之半導體裝置之俯視圖。
圖2係圖1所示之半導體裝置之剖面圖。
圖3係表示圖1所示之半導體裝置之形成導電性屏蔽層之前之狀態之剖面圖。
圖4係表示於第1實施形態之製造方法中使用之托盤之平面圖。
圖5係將圖4所示之托盤之一部分放大表示之平面圖。
圖6係沿著圖5之A-A線之剖面圖。
圖7係表示圖4至圖6所示之托盤之第1變化例之平面圖。
圖8係表示圖4至圖6所示之托盤之第2變化例之平面圖。
圖9係表示將圖4至圖6所示之托盤堆積之狀態之剖面圖。
圖10(a)及(b)係表示利用圖4至圖6所示之托盤之位置修正部修正被處理物之位置之狀態的剖面圖。
圖11(a)及(b)係表示第1實施形態之半導體裝置之製造步驟之剖面圖。
圖12係表示於第1實施形態之製造方法中所使用之托盤之其他例及使用其之半導體裝置之製造步驟之剖面圖。
圖13係表示於第2實施形態之製造方法中所使用之被處理物之剖面圖。
圖14係表示第2實施形態之半導體裝置之製造步驟之第1例之剖面圖。
圖15係表示第2實施形態之半導體裝置之製造步驟之第2例之剖 面圖。
以下，對實施形態之半導體裝置之製造方法進行說明。
[第1實施形態] (半導體裝置)
首先，參照圖1及圖2對藉由第1實施形態之製造方法所製造之半導體裝置進行說明。圖1係半導體裝置之俯視圖，圖2係半導體裝置之剖面圖。該等圖中所示之半導體裝置1係附有屏蔽功能之半導體裝置，其包括：配線基板2；半導體晶片3，其搭載於配線基板2之第1面2a上；密封樹脂層4，其將半導體晶片3密封；以及導電性屏蔽層5，其覆蓋密封樹脂層4之上表面及側面與配線基板2之側面之至少一部分。再者，密封樹脂層4之上表面等之上下之方向係以配線基板2之搭載有半導體晶片3之面在上之情形為基準。
配線基板2具有絕緣樹脂基材作為絕緣基材6。於絕緣基材6之上表面，設置有具有成為與半導體晶片3之電性連接部之內部連接端子7的第1配線層。於絕緣基材6之下表面，設置有具有成為與外部設備等之電性連接部之外部連接端子8的第2配線層。於第1及第2配線層上，分別形成有阻焊層9。配線基板2亦可為矽中介層(silicon interposer)等。第1配線層與第2配線層係例如經由以貫通絕緣基材6之方式設置之通孔(未圖示)而電性連接。第1及第2配線層或包含通孔之配線基板2之配線網具有於絕緣基材6之側面露出一部分之接地配線。
於圖2中表示形成於絕緣基材6之內部之實心膜狀(或網狀膜狀)之接地配線10。接地配線10係防止無用電磁波經由配線基板2而洩漏至外部。接地配線10之端部係於絕緣基材6之側面露出。接地配線10之自絕緣基材6露出之部分成為與導電性屏蔽層5之電性連接部。此處表示實心膜狀之接地配線10，但接地配線10之形狀並不限定於此。自絕 緣基材6之側面露出一部分之接地配線亦可為通孔。於使作為接地配線之通孔自絕緣基材6之側面露出之情形時，為了使露出面積增大，較佳為將通孔之至少一部分於絕緣基材6之厚度方向切斷，使該切斷面於絕緣基材6之側面露出。
於配線基板2之第1面2a上，搭載有半導體晶片3。半導體晶片3係經由接著層11而接著於配線基板2之第1面2a。設置於半導體晶片3之上表面之電極墊12係經由Au線等接合線13而與配線基板2之內部連接端子7電性連接。進而，於配線基板2之第1面2a上，形成有將半導體晶片3與接合線13等一併密封之密封樹脂層4。密封樹脂層4之上表面及側面與配線基板2之側面之至少一部分係由導電性屏蔽層5覆蓋。導電性屏蔽層5係與接地配線10之自絕緣基材6之側面露出之部分電性連接。
導電性屏蔽層5較佳為由防止自密封樹脂層4內之半導體晶片3或配線基板2之配線層放射之無用電磁波向外部洩漏、或防止自外部設備放射之電磁波對半導體晶片3造成不良影響，且電阻率較低之金屬材料層形成，例如應用使用有銅、銀、鎳等之金屬材料層。導電性屏蔽層5之厚度較佳為基於其電阻率而設定。例如較佳為以將導電性屏蔽層5之電阻率除以厚度所得之薄片電阻值成為小於等於0.5Ω之方式，設定導電性屏蔽層5之厚度。藉由將導電性屏蔽層5之薄片電阻值設為小於等於0.5Ω，可再現性良好地抑制來自密封樹脂層4之無用電磁波洩漏或自外部設備放射之電磁波向密封樹脂層4內侵入等。
自半導體晶片3等放射之無用電磁波或自外部設備放射之電磁波係被覆蓋密封樹脂層4之導電性屏蔽層5遮斷。因此，可抑制無用電磁波經由密封樹脂層4洩漏至外部或來自外部之電磁波侵入至密封樹脂層4內。有電磁波亦自配線基板2之側面洩漏或侵入之虞。因此，導電性屏蔽層5較佳為覆蓋配線基板2之側面整體。圖2係表示利用導電性 屏蔽層5覆蓋配線基板2之側面整體之狀態。藉此，可有效地抑制電磁波自配線基板2之側面洩漏或侵入。雖然於圖2中省略圖示，但亦可視需要利用耐蝕性或耐遷移性等優異之保護層(例如不鏽鋼層等鐵系保護層)覆蓋導電性屏蔽層5。
(半導體裝置之製造方法)
其次，對第1實施形態之半導體裝置1之製造步驟進行說明。首先，應用通常之半導體封裝體之製造步驟，實施至如圖3所示形成導電性屏蔽層5之前之步驟為止，藉此製作不具有導電性屏蔽層5之半導體封裝體20。即，製作不具有導電性屏蔽層5之半導體封裝體20作為應用濺鍍法之導電性屏蔽層5之形成步驟、即導電性屏蔽層5之濺鍍成膜步驟中之被處理物。不具有導電性屏蔽層5之半導體封裝體20係例如以下述方式製作。
首先，於多孔之集合基板之各配線基板區域(2)分別搭載半導體晶片3。經由接合線13將各配線基板區域(2)之內部連接端子7與半導體晶片3之電極墊12電性連接。統一地對搭載於多孔之集合基板上之複數個半導體晶片3進行樹脂密封。對應於各配線基板區域(2)而將包含複數個半導體晶片3之樹脂密封體切割。即，將包含集合基板及密封樹脂層之樹脂密封體整體切斷，使形成導電性屏蔽層5之前階段之半導體封裝體20單片化。圖3係表示經單片化之半導體封裝體20。
於導電性屏蔽層5之形成步驟(濺鍍步驟)中，將經單片化之半導體封裝體20用作被處理物。作為被處理物之複數個半導體封裝體20係收納於托盤中被輸送至濺鍍步驟，於該狀態下供於濺鍍步驟。濺鍍步驟用之托盤具有複數個被處理物收納部。托盤較佳為由例如聚苯醚(PPE)或聚苯硫醚(PPS)等耐熱樹脂形成。半導體封裝體20係以密封樹脂層4之上表面及側面與配線基板2之側面之至少一部分分別露出之方式配置於設置在托盤之複數個被處理物收納部內。於收納於托盤之狀 態下，對經單片化之半導體封裝體20上濺鍍金屬材料，藉此，形成覆蓋密封樹脂層4之上表面及側面與配線基板2之側面之至少一部分之導電性屏蔽層5。
圖4至圖6係表示濺鍍步驟用之托盤21。圖4係托盤21之平面圖，圖5係將托盤21之一部分放大表示之平面圖，圖6係沿著圖5之A-A線之剖面圖。然而，於圖6中省略半導體封裝體20之圖示。該等圖中所示之托盤21具有複數個被處理物收納部22。圖4所示之托盤21具有114個被處理物收納部22之形成區域，但中央附近之4部位被作為搬送時之吸附部23。被處理物收納部22具有供配置作為被處理物之半導體封裝體20之凹部24。凹部24具有矩形之平面形狀，以便可收納矩形之半導體封裝體20。凹部24之周圍係由局部地設置之壁狀部25包圍。換言之，藉由利用壁狀部25包圍凹部24之形成部分之周圍之一部分，而形成供配置半導體封裝體20之凹部24。
壁狀部25係設置於與凹部24之各邊對應之位置，且具有相當於各邊之一部分之長度。凹部24係藉由被壁狀部25包圍而形成，該壁狀部25係以相當於凹部24之各邊之一部分之方式局部地設置。為了不妨礙金屬材料對密封樹脂層4或配線基板2之側面之濺鍍性，凹部24之深度係於半導體封裝體20之上表面不自托盤21超出之範圍內設定得較淺。例如於配置厚度為1mm之半導體封裝體20之情形時，凹部24之距離托盤21之上表面之深度被設為1.2mm。壁狀部25之高度係如於下文進行詳細敍述般，被設定為低於配置在凹部24內之半導體封裝體20之上表面。
關於提高濺鍍步驟中之金屬材料對半導體封裝體20之密封樹脂層4之側面及配線基板2之側面之濺鍍性之方面，凹部24具有較半導體封裝體20更大之平面形狀(俯視時之平面形狀)。然而，若僅為具有此種形狀之凹部24，則存在如下之虞：於將半導體封裝體20偏斜地配置 之情形時，導電性屏蔽層5對於密封樹脂層4及配線基板2之側面之一部分之形成性降低。因此，包圍凹部24之4個壁狀部25A、25B、25C、25D分別具有肋部26作為半導體封裝體20之定位部。肋部26係針對各壁狀部25A、25B、25C、25D分別形成有2個。藉由利用複數個肋部26將半導體封裝體20之各側面定位，可提高矩形形狀之半導體封裝體20之定位精度。
肋部26係設置於壁狀部25之兩端，且具有自壁狀部25之上部朝凹部24之內側傾斜之形狀。由肋部26之下端界定之凹部24之底面係對應於半導體封裝體20之外形形狀。因此，收納於凹部24內之半導體封裝體20係藉由沿傾斜狀之肋部26滑落至凹部24之底面為止而被定位。肋部26之傾斜角度(底面與傾斜面之角度)較佳為考慮半導體封裝體20之定位性與金屬材料之覆著性而設定為35~50度之範圍。關於肋部26之前端，為了提高半導體封裝體20之定位性，儘可能使角R較小。然而，若重複由樹脂材料形成之托盤21之成形，則有相當於模具之部分磨耗而角R變大之虞。針對此種方面，有效的是於肋部26之前端之前方形成刻蝕部。又，為了提高金屬材料對於密封樹脂層4及配線基板2之各側面之濺鍍性，使肋部26之寬度較窄，且使頂部為曲面狀(圓弧等)。進而，肋部26之高度係設定為低於配置在凹部24內之半導體封裝體20之上表面。
為了防止肋部26之折斷或利用樹脂材料射出成型托盤21之後之翹曲等，於2個肋部26間設置有凸部27。壁狀部25含有兩端之肋部26及設置於其等之間之凸部27。凸部27係支持肋部26且賦予防止托盤21之翹曲等之強度，故而其高度較佳為於可維持肋部26之支持性或強度等之範圍內較低。因此，凸部27具有高度較肋部26低且前端較肋部26之前端更後退之形狀。凸部27具有相較傾斜狀之肋部26相對較小之傾斜形狀(例如剖面三角形狀)。凸部27之具體之高度較佳為以不超過將 1個半導體封裝體20之下端部與鄰接之半導體封裝體20之上端部連結之線之方式設定。即便使凸部27之高度較上述更低，亦未提高金屬材料之覆著性。因此，若為上述範圍內，則較佳為將凸部27之高度加高，而提高凸部27之強度等。
壁狀部或肋部(定位部)之形狀並不限定於上述形狀。圖7及圖8係表示包圍凹部24之整個周圍之壁狀部25。圖7所示之托盤21具有自壁狀部25之各壁面向凹部24之內側突出之肋部28作為半導體封裝體20之定位部。肋部28之前端係與半導體封裝體20之外形形狀對應。因此，配置於凹部24內之半導體封裝體20係藉由肋部28之前端而定位。圖8所示之托盤21具有作為半導體封裝體20之定位部而設置於壁狀部25之各壁面之傾斜部(傾斜面)29。傾斜部29係以自壁狀部25之上端向凹部24之內側傾斜之方式設置。由傾斜部29之下端界定之凹部24之底面係與半導體封裝體20之外形形狀對應。因此，收納於凹部24內之半導體封裝體20係藉由沿傾斜部(傾斜面)29滑落至凹部24之底面為止而被定位。
被處理物收納部22具有分別設置於複數個凹部24內之凹陷部30。凹陷部30有助於提高托盤21之強度，且於利用樹脂材料製作托盤21時使托盤21之實體積減小而減少樹脂材料之使用量，藉此降低托盤21之製造成本。又，藉由利用凹陷部30減小托盤21之實體積，亦可謀求托盤21之輕量化。托盤21基本而言係於實施1次濺鍍步驟之後作為原料再利用或廢棄。因此，托盤21之原材料費之降低有助於濺鍍步驟之成本之降低。進而，藉由使托盤21輕量化，亦可降低半導體封裝體20之搬送成本等。圖6係表示具有底面之非貫通孔(孔)作為凹陷部30。
收納半導體封裝體20之托盤21係將操作性或搬送性等加以考慮而設為可堆積。圖9係表示將複數個托盤21(21A、21B)堆積之狀態。 為了防止堆積有複數個托盤21時之位置偏移或伴隨於此之半導體封裝體20之位置偏移等，托盤21具有設置於下表面側之第1卡合部31及設置於上表面側之第2卡合部32。圖6及圖9所示之托盤21具有作為第1卡合部31之凸部、及作為第2卡合部32之凹部。於將複數個托盤21A、21B堆積時，上段側之托盤21B之第1卡合部(凸部)31卡合於下段側之托盤21A之第2卡合部(凹部)32。堆積有複數個托盤21A、21B時之托盤21之位置偏移等得到防止。
進而，於圖6所示之托盤21之下表面側，進而設置有被處理物之位置修正部33。位置修正部33具有前端成為R形狀之楔形部34。如圖10(a)所示，於如收納於托盤21A之被處理物收納部22內之半導體封裝體20之一端重疊於壁狀部25上之情形時，若於其上堆積托盤21B，則托盤21A內之半導體封裝體20被托盤21B之定位部33之楔形部34壓下。因此，可將半導體封裝體20配置於被處理物收納部22內之正確之位置。考慮金屬材料對於密封樹脂層4或配線基板2之各側面之濺鍍性，使壁狀部25之高度低於配置在凹部24內之半導體封裝體20之上表面。因此，可利用位置修正部33將端部重疊於壁狀部25上之半導體封裝體20壓下至正確之位置。
如圖11(a)所示，作為被處理物之半導體封裝體20被以收納於托盤21之被處理物收納部22內之狀態輸送至濺鍍步驟，且載置於濺鍍裝置之平台35上。如圖11(b)所示，以將半導體封裝體20收納於托盤21之狀態實施濺鍍成膜，藉此，形成覆蓋密封樹脂層4之上表面及側面與配線基板2之側面之導電性屏蔽層5。根據所處理之半導體封裝體20之批次數等，有產生未配置半導體封裝體20之被處理物收納部22X之情形。於此種情形時，由於凹陷部30為具有底面之非貫通孔(孔)，故而雖然無用之金屬膜5X附著於凹陷部30內，亦無無用之金屬膜5X污染濺鍍裝置之平台35之情況。因此，可降低平台35之清潔或更換所需 之成本。
此處，於將凹陷部30設為貫通孔之情形時，與非貫通孔(孔)相比，可進一步減少樹脂材料之使用量，故而可更有效地獲得作為減量用之凹陷部30之效果。進而，托盤21之輕量化效果等亦變大。然而，於含有貫通孔之凹陷部30中，當如上述般產生未配置半導體封裝體20之被處理物收納部22X時，無用之金屬膜5X附著於濺鍍裝置之平台35而將其污染。因此，於使用含有貫通孔之凹陷部30之情形時，較佳為於濺鍍裝置之平台35上配置抗附著板，於其上載置收納有半導體封裝體20之托盤21。
圖12係表示對應用含有貫通孔之凹陷部30A之托盤21與使用該托盤21之半導體封裝體20之濺鍍成膜步驟作為第1實施形態之變化例。圖12所示之托盤21具有分別設置於複數個凹部24內之含有貫通孔之減量用之凹陷部30A。收納有半導體封裝體20之托盤21係載置於配置在濺鍍裝置之平台35上之抗附著板36上。抗附著板36係防止無用之金屬膜5X附著於平台35者，故而例如可使用容易洗淨之不鏽鋼板等。
如上所述，於產生未配置半導體封裝體20之被處理物收納部22X之情形時，濺鍍粒子係通過含有貫通孔之凹陷部30A。由於在平台35上配置有抗附著板36，故而通過凹陷部30A之濺鍍粒子係附著於抗附著板36上。無用之金屬膜5X係形成於抗附著板36上，故而不會污染濺鍍裝置之平台35。雖然產生抗附著板36之配置或更換等所需之步驟數，但與濺鍍裝置之平台35之清潔或更換所需之步驟數相比，可削減成本。又，含有貫通孔之凹陷部30A係與含有非貫通孔之凹陷部30相比，原材料費之降低效果較大。
於第1實施形態之製造方法中，於將半導體封裝體20收納於托盤21之狀態下實施濺鍍步驟，故而可提高濺鍍步驟中之經單片化之半導體封裝體20之操作性等。因此，與利用半切槽實施之濺鍍步驟相比， 可防止因切割步驟之深度控制而導致之作業性降低或因實施2次切割步驟而導致之步驟數增加等。關於利用半切槽之濺鍍步驟，不僅如上述般使切割步驟之步驟數增加，導電性屏蔽層對於密封樹脂層之側面等之形成性亦變差。
針對此種方面，於在將半導體封裝體20收納於托盤21之狀態下實施濺鍍步驟之情形時，因托盤21之被處理物收納部22之形狀，具體而言因凹部24、壁狀部25、肋部26等之形狀，而導電性屏蔽層5對於密封樹脂層4或配線基板2之側面之形成性提高。即，可不使形成於密封樹脂層4之上表面之導電性屏蔽層5之厚度變厚，而於密封樹脂層4或配線基板2之側面形成具有為了獲得屏蔽效果而所需之厚度之導電性屏蔽層5。因此，可抑制導電性屏蔽層5之形成所需之材料成本之增加等。藉由該等，可提高導電性屏蔽層5對於半導體封裝體20之形成性，且可減少導電性屏蔽層5之形成步驟數或形成成本等。
進而，於第1實施形態之製造方法中，由於使用具有含有非貫通孔之凹陷部30或含有貫通孔之凹陷部30A之托盤21，故而可降低托盤21之製造成本。於具有含有非貫通孔之凹陷部30之托盤21之情形時，即便直接供於濺鍍步驟，亦不會因未配置半導體封裝體20之被處理物收納部22X而污染濺鍍裝置之平台35。於具有含有貫通孔之凹陷部30A之托盤21之情形時，由於托盤21隔著抗附著板36載置於濺鍍裝置之平台35上，故而不會因未配置半導體封裝體20之被處理物收納部22X而污染濺鍍裝置之平台35。因此，可抑制濺鍍步驟所需之步驟數或成本之增加。
[第2實施形態] (被處理物)
其次，參照圖13至圖15對第2實施形態之製造方法進行說明。圖13係於半導體裝置之製造步驟中用作為被處理物之半導體封裝體之剖 面圖，圖14及圖15係表示使用圖13所示之被處理物之半導體裝置之製造步驟。第2實施形態之製造方法係利用第1實施形態之托盤21中之凹陷部30、30A作為BGA(Ball Grid Array，球柵陣列)型半導體封裝體之凸塊電極之收容部。於第2實施形態之製造步驟中使用之托盤21係除將凹陷部30、30A用作凸塊電極之收容部以外，具有與第1實施形態之托盤21相同之構造。如圖13所示，於第2實施形態中用作為被處理物之半導體封裝體40具有設置於配線基板2之外部連接端子8上之焊接凸塊等凸塊電極41。
(半導體裝置之製造方法)
其次，對第2實施形態之半導體裝置1之製造步驟進行說明。如圖14及圖15所示，半導體封裝體40係於將凸塊電極41收容於凹陷部30、30A之狀態下，配置於托盤21之被處理物收納部22內。收容凸塊電極41之凹陷部可為具有底面之非貫通孔(30)及貫通孔(30A)之任一者。與第1實施形態同樣地，半導體封裝體40被以收納於托盤21之狀態輸送至濺鍍步驟，且於該狀態下供於濺鍍步驟。濺鍍步驟係以與第1實施形態相同之方式實施。藉由此種濺鍍步驟，形成覆蓋密封樹脂層4之上表面及側面與配線基板2之側面之導電性屏蔽層5。
此處，若於使半導體封裝體40單片化之後形成凸塊電極41，則凸塊電極41之製造成本等大幅度地增加。因此，凸塊電極41係於使半導體封裝體40單片化之前形成。亦考慮利用黏著片材等保持單片化後之半導體封裝體40之凸塊電極41之形成面側而實施濺鍍構成，但於此情形時，濺鍍膜折入至凸塊電極41之形成面側之虞較大。針對此種方面，藉由使用具有凹陷部30、30A之托盤21，可與不具有凸塊電極41之半導體封裝體20同樣地，對具有凸塊電極41之單片狀態之半導體封裝體40實施濺鍍步驟。即，可利用濺鍍步驟於具有凸塊電極41之半導體封裝體40良好地形成導電性屏蔽層5。其他效果係與第1實施形態相 同。
再者，對本發明之若干實施形態進行了說明，但該等實施形態係作為示例而提出者，並非意欲限定發明之範圍。該等新穎之實施形態能夠以其他各種形態實施，可於不脫離發明之主旨之範圍內進行各種省略、替換、變更。該等實施形態及其變化包含於發明之範圍或主旨中，並且包含於申請專利範圍中所記載之發明及其均等範圍內。
20‧‧‧半導體封裝體
21‧‧‧托盤
22‧‧‧處理物收納部
24‧‧‧凹部
25‧‧‧壁狀部
25A、25B、25C、25D‧‧‧壁狀部
26‧‧‧肋部
27‧‧‧凸部
30‧‧‧含有非貫通孔之凹陷部

Claims (5)

  1. 一種半導體裝置之製造方法，其包括如下步驟：準備複數個被處理物，上述複數個被處理物包括配線基板、搭載於上述配線基板上之半導體晶片、以及以將上述半導體晶片密封之方式設置於上述配線基板上之密封樹脂層；準備托盤，上述托盤包括複數個被處理物收納部、以及分別設置於上述複數個被處理物收納部內之凹陷部；以於上述配線基板上搭載有上述半導體晶片之面在上之情形時之上述密封樹脂層之上表面及側面與上述配線基板之側面之至少一部分露出之方式，將上述被處理物分別配置於上述托盤之上述複數個被處理物收納部內；及將收納有上述複數個被處理物之上述托盤載置於濺鍍裝置之平台上，且對上述複數個被處理物濺鍍金屬材料，藉此形成覆蓋上述密封樹脂層之上表面及側面與上述配線基板之側面之至少一部分之導電性屏蔽層；且上述凹陷部包括具有底面之非貫通孔。
  2. 一種半導體裝置之製造方法，其包括如下步驟：準備複數個被處理物，上述複數個被處理物包括配線基板、搭載於上述配線基板上之半導體晶片、以及以將上述半導體晶片密封之方式設置於上述配線基板上之密封樹脂層；準備托盤，上述托盤包括複數個被處理物收納部、以及分別設置於上述複數個被處理物收納部內之凹陷部；以於上述配線基板上搭載有上述半導體晶片之面在上之情形時之上述密封樹脂層之上表面及側面與上述配線基板之側面之至少一部分露出之方式，將上述被處理物分別配置於上述托盤 之上述複數個被處理物收納部內；及將收納有上述複數個被處理物之上述托盤載置於濺鍍裝置之平台上，且對上述複數個被處理物濺鍍金屬材料，藉此形成覆蓋上述密封樹脂層之上表面及側面與上述配線基板之側面之至少一部分之導電性屏蔽層；且上述凹陷部包括貫通孔，將上述托盤載置於配置在上述濺鍍裝置之平台上之抗附著板上，於該狀態下實施上述濺鍍。
  3. 如請求項1或2之半導體裝置之製造方法，其中上述被處理物收納部包含：凹部，其具有大於上述被處理物之矩形之平面形狀；壁狀部，其以形成上述凹部之方式包圍上述凹部之周圍之至少一部分；及定位構件，其設置於上述壁狀部，將配置於上述凹部內之上述被處理物定位。
  4. 如請求項3之半導體裝置之製造方法，其中上述托盤係於下表面側包含具有以與上述壁狀部對應之方式設置之楔形部的上述被處理物之位置修正部，於堆積有複數個上述托盤時，利用上述位置修正部之上述楔形部修正收納於下段側之托盤之上述被處理物之位置。
  5. 如請求項1或2之半導體裝置之製造方法，其中上述被處理物進而包含凸塊電極，該凸塊電極係設置於上述配線基板之與搭載有上述半導體晶片之面為相反側之面，上述被處理物係於將上述凸塊電極收容於上述凹陷部內之狀態下，配置於上述被處理物收納部內。
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