TW201511135A - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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TW201511135A
TW201511135A TW102144958A TW102144958A TW201511135A TW 201511135 A TW201511135 A TW 201511135A TW 102144958 A TW102144958 A TW 102144958A TW 102144958 A TW102144958 A TW 102144958A TW 201511135 A TW201511135 A TW 201511135A
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trench
insulating film
semiconductor device
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Toshifumi Nishiguchi
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Toshiba Kk
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Abstract

本實施形態提供一種可對應元件構造之微細化而提高終端部之耐壓之半導體裝置之製造方法。本實施形態係半導體裝置之製造方法，該半導體裝置包含：設置半導體元件之元件部、及包圍上述元件部之終端部；且該製造方法係形成沿自形成上述半導體元件之第1導電形之半導體層之第1面至與上述第1面為相反側之第2面之方向延伸之複數個溝槽；形成覆蓋上述第1面及上述複數個溝槽之內面之絕緣膜；除去上述複數個溝槽中之位於上述終端部之溝槽之底面所形成之上述絕緣膜之一部分；於除去上述絕緣膜之一部分之上述溝槽之底部中離子注入第2導電形之雜質。

Description

半導體裝置之製造方法
本申請案享受以日本專利申請案2013-191139號(申請日：2013年9月13日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
本實施形態係關於半導體裝置之製造方法。
對電力控制用之半導體裝置，追求源/汲極間之高耐壓化與低開啟電阻化。例如，在MOS(Metal Oxide Semiconductor：金屬氧化物半導體)型電晶體中，採用溝槽閘極構造而實現其微細化，藉此可降低開啟電阻。另一方面，源/汲極間耐壓可藉由使用以電晶體構造之端部為終端之保護環構造，實現高耐壓化。但，隨著元件構造之微細化，追求其構造及製造方法之改良。
本實施形態提供一種可對應元件構造之微細化而提高終端部之耐壓之半導體裝置之製造方法。
本實施形態係半導體裝置之製造方法，該半導體裝置具有：設置半導體元件之元件部、及包圍上述元件部之終端部；且該製造方法係形成沿自形成上述半導體元件之第1導電形之半導體層之第1面至與上述第1面為相反側之第2面之方向延伸之複數個溝槽；形成覆蓋上述第1面及上述複數個溝槽之內面之絕緣膜；除去上述複數個溝槽中之位於上述終端部之溝槽之底面所形成之上述絕緣膜之一部分；於除去 上述絕緣膜之一部分之上述溝槽之底部中離子注入第2導電形之雜質。
1‧‧‧半導體裝置
5‧‧‧汲極層
7‧‧‧漂移層
7a‧‧‧上表面
7b‧‧‧下表面
9a‧‧‧溝槽
9b‧‧‧溝槽
9be‧‧‧底面
13‧‧‧p型區域
15‧‧‧場板極
17‧‧‧場絕緣膜
21‧‧‧p型基極層
23‧‧‧n型源極區域
25‧‧‧閘極電極
27‧‧‧閘極絕緣膜
33‧‧‧層間絕緣膜
33a‧‧‧開口
35‧‧‧源極電極
41‧‧‧絕緣膜
41a‧‧‧絕緣膜
43‧‧‧掩模
43a‧‧‧開口
47‧‧‧p型雜質
AA‧‧‧元件部
EA‧‧‧終端部
X‧‧‧方向
Y‧‧‧方向
Z‧‧‧方向
圖1(a)、(b)係表示實施形態之半導體裝置之模式圖。
圖2(a)~(c)係表示實施形態之半導體裝置之製造過程之模式剖面圖。
圖3(a)~(c)係表示緊接著圖2之製造過程之模式剖面圖。
圖4係表示實施形態之半導體裝置之特性之圖表。
以下，針對實施形態一邊參照圖式一邊進行說明。對圖式中之相同部分，標註相同序號並適當省略其詳細之說明，而針對不同之部分進行說明。另，圖式係模式性或概念性者，各部分之厚度與寬度之關係、部分間之大小之比例等並非一定與現實者相同。又，即使表示相同部分之情形時，亦存在根據圖式而不同地表示相互之尺寸或比例之情形。
圖1係表示實施形態之半導體裝置1之模式圖。半導體裝置1係例如具有溝槽閘極構造之MOS電晶體。圖1(a)係表示對應於圖1(b)所示之A-A線之剖面。圖1(b)係表示設置於晶片面上之溝槽之配置之俯視圖。
半導體裝置1具有設置半導體元件(MOS電晶體)之元件部AA、及包圍元件部之終端部EA。
如圖1(a)所示，半導體裝置1具備汲極層5、設置於汲極層5上之漂移層7。汲極層5為例如設置於矽基板上之n型半導體層。又，汲極層5亦可為n型矽層或n型矽基板本身。設置於汲極層5上之漂移層7係較汲極層5更低濃度之n型半導體層。漂移層7為例如n型矽層。、
在本實施形態中，雖將第1導電形作為n型、第2導電形作為p型 進行說明，但並非限定於此，亦可將第1導電形作為p型，將第2導電形作為n型。又，半導體層並非限定於矽層，例如亦可為碳化矽(SiC)。
如圖1(a)所示，於漂移層7上形成複數個溝槽9a、9b。各溝槽設置於自漂移層7之上表面7a朝向下表面7b之方向(Z方向)。如圖1(b)所示，溝槽9a設置於元件部AA，溝槽9b設置於終端部EA。
如圖1(b)所示，溝槽9a係例如在元件部AA中於Y方向延伸。另一方面，溝槽9b係在終端部EA中以包圍元件部AA之周圍之方式設置。又，如該圖所示，較佳為多重地形成複數個溝槽9b。此時，欲使終端部EA之溝槽之深度較元件部AA之溝槽更深之情形，可藉由擴大終端部EA之溝槽開口寬度來實現。又，為使終端部EA之溝槽開口寬度較淺，可藉由縮小溝槽開口寬度來實現。
在溝槽9a及9b之內部，設置場板極15。場板極15介隔場絕緣膜17與漂移層7相對。且，在設置於元件部AA之溝槽9a之內部，於場板極15上介隔絕緣膜而設置閘極電極25。
再者，在元件部AA中，在位於相鄰之溝槽9a之間之漂移層7上設置p型基極層21。p型基極層21介隔閘極絕緣膜27與閘極電極25相對。進而，於p型基極層21上設置n型源極區域23。
於溝槽9a及9b上，設置覆蓋閘極電極25及場板極15之層間絕緣膜33。層間絕緣膜33具有在元件部AA中與p型基極層21及n型源極區域23連通之開口33a。
再者，在元件部AA中於層間絕緣膜33上設置源極電極35，源極電極35經由開口33a而與p型基極層21及n型源極區域23電性連接。
另一方面，在終端部EA中，於溝槽9b之下方分別形成p型區域13。p型區域13在源/汲極間為斷開時，限制擴展於漂移層7之內部之空乏層向橫向(X方向)擴展，從而提高終端部之耐壓。
即，在半導體裝置1中構成保護環，其包含具有配置於終端部之場板極之複數個溝槽9b、及形成於各溝槽9b之下方之p型區域13。藉此，可提高其特性，例如漂移耐壓、雪崩耐量。
接著，參照圖2及圖3說明實施形態之半導體裝置之製造方法。圖2(a)~圖3(c)係表示實施形態之半導體裝置之製造過程之模式剖面圖。
例如，準備於未圖示之矽基板上形成有n型漂移層7之晶圓。n型漂移層7具有第1面(上表面7a)、及其相反側之第2面(下表面7b)。
如圖2(a)所示，形成沿自n型漂移層7之上表面7a朝向下表面7b之第1方向(Z方向)延伸之溝槽9a及9b。溝槽9a形成於對應於元件部AA之區域，溝槽9b形成於對應於包圍元件部AA之終端部EA之區域。
溝槽9a及9b係例如藉由於n型漂移層7上形成具有對應於各溝槽之位置之開口之掩模，並使用各向異性RIE(Reactive Ion Etching：反應性離子蝕刻)法選擇性地蝕刻n型漂移層7而形成。
接著，如圖2(b)所示，形成覆蓋n型漂移層7之上表面7a、及溝槽9a、9b之內面之絕緣膜41。絕緣膜41係例如藉由將n型漂移層7熱氧化而形成之氧化矽膜。絕緣膜41係例如形成為10奈米(nm)~200nm之厚度。較好的是形成為可除去溝槽9a及9b之蝕刻時形成於其內面之蝕刻損傷之厚度。
接著，如圖2(c)所示，形成覆蓋元件部AA及終端部EA之外側之掩模43。掩模43為例如光阻劑，且具有藉由光微影所形成之開口43a。於開口43a之內側，露出終端部EA之溝槽9b。掩模43嵌入溝槽9a之內部而覆蓋n型漂移層7之上表面7a。且，在後述之離子注入過程中，形成為不於n型漂移層7之上表面7a注入p型雜質之厚度。
其次，如圖3(a)所示，除去覆蓋溝槽9b之底面9be、及n型漂移層7之上表面7a之絕緣膜41之一部分，而殘留覆蓋溝槽9b之內壁之絕緣 膜41之一部分41a。
例如，使用具有Z方向之蝕刻速度較x方向及Y方向之蝕刻速度更快之各向異性之RIE條件，蝕刻露出於開口43a之內側之絕緣膜41。
再次，經由開口43a對n型漂移層7離子注入p型雜質。p型雜質為例如硼(B)，注入於已除去絕緣膜41之溝槽9b之底面、及漂移層7之上表面7a。
p型雜質較好係以於形成於溝槽9a之下方之p型區域13中下端變深之方式注入。為此，期望藉由縮小離子注入之離子束之傾斜角，而增大通道效應成分之比例。具體而言，以使離子束之傾斜角相對於注入方向即Z方向未達7度、較好係成為2.7度以下之方式注入。例如，期望將傾斜角設為0(零)度而注入。
又，覆蓋溝槽9a之內壁之絕緣膜41a抑制了p型雜質向內壁注入，且防止向p型反轉。再者，離子注入之傾斜角之抑制，亦具有降低p型雜質向溝槽9a之內壁注入之效果。藉此，可避免終端部EA之耐壓降低。
接著，如圖3(c)所示，除去掩模43。掩模43係例如可藉由氧氣灰化除去。接著，蝕刻絕緣膜41，自溝槽9a、9b之各者之內面、及漂移層7之上表面7a之整體除去絕緣膜41。
其次，於溝槽9a及9b之內面形成場絕緣膜17，且嵌入成為場板極15之多晶矽(參照圖1)。場絕緣膜17係使用矽之熱氧化法、或CVD(Chemical Vapor Deposition：化學氣相沈積)法而形成。在此例中，例如使用CVD法形成於溝槽9a及9b之各者之內面之情形時，藉由將各溝槽之內面熱氧化而形成場絕緣膜17，亦可減輕其應力。其結果，可獲得抑制晶圓翹曲之效果。又，亦可形成較厚之場絕緣膜17。
接著，依序形成閘極絕緣膜27、閘極電極25、p型基極層21、n型源極區域23、層間絕緣膜33及源極電極35，而完成半導體裝置1。 通過此等過程之熱處理，使注入於溝槽9b之下方之p型雜質47活化，從而可形成p型區域13。
如上述般，藉由更深地形成溝槽9b之下方之p型區域13，可提高形成於終端部EA之保護環構造之耐壓。因此，藉由縮小p型雜質之離子注入之傾斜角，而增加通道效應成分，從而更深地注入p型雜質。
圖4係表示實施形態之半導體裝置之特性之圖表。該圖顯示有改變離子束之傾斜角而注入於矽中之硼之分佈。橫軸係距矽層之表面之深度(μm)，縱軸為硼濃度(cm-3)。
圖4中所示之曲線B顯示將傾斜角設為7度而進行離子注入之硼之分佈。另一方面，曲線C顯示將傾斜角設為0度之情形之硼之分佈。且，注入能量為200keV，劑量為4×1012cm-3。
如自圖4所示之例所明瞭般，相較於將傾斜角設為7度之曲線B，將傾斜角設為0度之曲線C係更深地分佈有硼。即，藉由使傾斜角小於7度，可增加離子注入之通道效應成分。且，可更深地注入雜質。
例如，將注入能量設為100keV而於面方位[100]之矽層注入硼之情形時，通道效應之臨界角為2.7度。且，隨著使注入能量增大，通道效應之臨界角有變小之傾向。即，在以高能量進行離子注入之情形時，較好係將傾斜角設為2.7度以下。又，期望以晶圓相對離子束之角度成為垂直之方式(即，傾斜角成為0度之方式)，設定離子注入裝置之壓盤。
又，在上述製造過程中，自露出於掩模43之開口43a之溝槽9b除去其底部之絕緣膜41。藉此，可避免離子注入之雜質在絕緣膜41中散射而使通道效應成分減少。即，相較於介隔絕緣膜41之直通離子注入，可形成更深之擴散層。再者，殘留於溝槽9b之側壁之絕緣膜41a可抑制雜質注入於溝槽側壁而使保護環耐壓降低。
再者，若為了較深地注入p型雜質而提高離子注入之加速電壓， 則離子之散射變大。因此，存在形成於溝槽9b之下方之p型區域13向橫向(X方向)擴展，而與形成於鄰接之溝槽9b之下方之其他p型區域13連接之虞。且，若形成於各溝槽9b之下方之p型區域13於橫向上連接，則全部p型區域13成為等電位而導致保護環之性能降低。
相對於此，在本實施形態中係將通道效應成分之比例設為較大，而抑制所注入之離子之散射。藉此，可避免相鄰之p型區域13相連接。即，即使半導體元件之構造微細化，而相鄰之溝槽9b之間隔變窄，在本實施形態中仍可維持較高之保護環耐壓、即終端部之耐壓。
在上述例中，雖已說明在終端部EA中於溝槽9b之下方形成p型區域13之例，但實施形態並非限定於此。
例如，形成自第1導電形之半導體層之第1面向第2面延伸之溝槽，且形成覆蓋此溝槽之內面之絕緣膜。其後，不限於終端部EA外，除去任意之溝槽之底面所形成之絕緣膜之一部分。且，亦可將離子束之傾斜角設為未達7度，而於溝槽之底部離子注入第2導電形之雜質。藉此，可形成較深地分佈於溝槽之下方之第2導電形之區域。
雖已說明本發明之若干個實施形態，但該等實施形態係作為例子而提示者，並非意圖限定發明之範圍。該等新穎之實施形態可以其他各種形態予以實施，且可於不脫離發明之主旨之範圍內進行各種省略、替換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，且包含於申請專利範圍所記載之發明及其均等之範圍內。
1‧‧‧半導體裝置
5‧‧‧汲極層
7‧‧‧漂移層
7a‧‧‧上表面
7b‧‧‧下表面
9a‧‧‧溝槽
9b‧‧‧溝槽
13‧‧‧p型區域
15‧‧‧場板極
17‧‧‧場絕緣膜
21‧‧‧p型基極層
23‧‧‧n型源極區域
25‧‧‧閘極電極
27‧‧‧閘極絕緣膜
33‧‧‧層間絕緣膜
33a‧‧‧開口
35‧‧‧源極電極
AA‧‧‧元件部
EA‧‧‧終端部
X‧‧‧方向
Y‧‧‧方向
Z‧‧‧方向

Claims (5)

  1. 一種半導體裝置之製造方法，該半導體裝置包含：設置半導體元件之元件部、及包圍上述元件部之終端部；且該製造方法係形成沿自形成上述半導體元件之第1導電形之半導體層之第1面至與上述第1面為相反側之第2面之方向延伸之複數個溝槽；形成覆蓋上述第1面及上述複數個溝槽之內面之絕緣膜；除去上述複數個溝槽中之位於上述終端部之溝槽之底面所形成之上述絕緣膜之一部分；及於除去上述絕緣膜之一部分之上述溝槽之底部中離子注入第2導電形之雜質。
  2. 如請求項1之半導體裝置之製造方法，其中上述離子注入係在自上述第1面朝向上述第2面之第1方向上注入上述第2導電形之雜質，且將離子束相對上述第1方向之傾斜角設為未達7度。
  3. 如請求項1之半導體裝置之製造方法，其中上述離子注入係在自上述第1面朝向上述第2面之第1方向上注入上述第2導電形之雜質，且將離子束相對上述第1方向之傾斜角設為2.7度以下。
  4. 如請求項1至3中任一項之半導體裝置之製造方法，其中以掩模覆蓋上述複數個溝槽中之設置於上述元件部之溝槽，並於位於上述終端部之上述溝槽之底部中離子注入上述第2導電形之雜質。
  5. 一種半導體裝置之製造方法，其係形成自第1導電形之半導體層之第1面向與上述第1面為相反側之第2面延伸之溝槽；且形成覆蓋上述第1面及上述溝槽之內面之絕緣膜；除去上述溝槽之底面所形成之上述絕緣膜之一部分； 在自上述第1面朝向上述第2面之第1方向上離子注入第2導電形之雜質；將離子束相對於上述第1方向之傾斜角設為未達7度。
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