TW201426883A - 單一或多重閘極場平板之製造 - Google Patents

單一或多重閘極場平板之製造 Download PDF

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TW201426883A
TW201426883A TW103103844A TW103103844A TW201426883A TW 201426883 A TW201426883 A TW 201426883A TW 103103844 A TW103103844 A TW 103103844A TW 103103844 A TW103103844 A TW 103103844A TW 201426883 A TW201426883 A TW 201426883A
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transistor
field plates
gate
dielectric material
field
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TWI560783B (en
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Alessandro Chini
Umesh K Mishra
Primit Parikh
Yi-Feng Wu
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Univ California
Cree Inc
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Abstract

本發明揭示一種用於製造單一或多重閘極場平板之方法，該方法使用在場效應電晶體之表面上之介電材料沈積/生長、介電材料蝕刻及金屬蒸鍍之連續步驟。因為介電材料沈積/生長通常為良好可控的過程，所以此製造方法允許基於場平板運作之嚴密控制。此外，沈積於裝置表面上之介電材料不需自裝置本質(intrinsic)區域移除：此基本上使得能夠無需低損壞介電材料之乾式/濕式蝕刻而實現場平板裝置。使用多重閘極場平板亦藉由多重連接而減少閘極電阻，因此而改良較大周邊及/或次微米閘極裝置之效能。

Description

單一或多重閘極場平板之製造
本發明係關於半導體裝置，且更特定言之，本發明係關於單一或多重閘極場平板之製造。
(註：本申請案參考各種公開案，如在說明書中由在方括號中之參考數字(如[x])所指示的。根據該等參考數字排列之該等公開案之清單位於題為參考文獻之區中的下方。該等公開案之每一以引用方式併入本文中。)
在基於半導體之場效應電晶體(FET)中，在正常運作期間較大電場出現在閘極汲極存取區域中。場平板為用於改良在高電場運作下之裝置效能及減輕表面俘獲現象[1]、[2]之熟知技術。舉例而言，為減輕發生於以高電場運作之裝置中之所有有害效應(崩潰電壓、俘獲效應、可靠性)，場平板已經成為有效且熟知之技術。
場平板之基本概念依裝置作用區域之垂直耗盡而定，因此，能夠增大水平耗盡區域之延伸。對於給定偏壓，此導致在裝置作用區域中之更低電場，減輕了以高電場運作之裝置隨時可發生的所有有害效應(低崩潰、俘獲現象、差可靠性)。此外，定位於閘極汲極存取區域中之場平板亦具有調變裝置作用區域之能力，導致減小減少會在較大射頻(RF)訊號下妨礙適當裝置運作的表面俘獲效應。
但是，所需要的是製造單一或多重閘極場平板之改良方法，及 併入單一或多重閘極場平板之改良結構。
本發明之實施例提供製造單一及多重閘極場平板之改良方法。根據本發明之製造方法使用在場效應電晶體之表面上之介電材料沈積或生長、介電材料蝕刻及金屬蒸鍍之連續步驟。製造方法之優點包括嚴密控制介電材料的厚度，且不存在裝置作用區域之表面對於可能導致在形成場效應電晶體之半導體材料中之損壞的任何乾式或濕式蝕刻製程的任何曝露。此外，沈積於裝置表面上之介電材料不必自裝置本質區域移除，此使得能夠在沒有由乾式或濕式製程引起之損壞的狀況下實現場平板裝置。使用多重閘極場平板藉由使用多重連接而減少閘極電阻，因此，改良較大周邊及/或次微米裝置之效能。最後，藉由適當調整介電材料之厚度，可將平行閘極接觸件沈積於介電材料之頂上，以藉由電連接在裝置非本質區域上之平行閘極接觸件而顯著減少閘極電阻。
10‧‧‧場效應電晶體
12,14‧‧‧歐姆接觸件
16‧‧‧閘極接觸件
18‧‧‧作用區域
20‧‧‧介電材料
22‧‧‧裝置非本質區域
24‧‧‧場平板
26‧‧‧介電材料
28‧‧‧場平板
30‧‧‧單位單元
32‧‧‧基板
34‧‧‧長晶層
36‧‧‧通道層
38‧‧‧障壁層
40‧‧‧間隔層
42‧‧‧源極
44‧‧‧汲極
46‧‧‧閘極
48‧‧‧場平板
50‧‧‧鈍化層
圖1A為場效應電晶體(FIG)之橫截面圖，且圖1B為場效應電晶體(FET)之俯視圖；圖2A為說明介電材料沈積/生長之裝置橫截面圖，且圖2B為說明介電材料沈積/生長之裝置俯視圖；圖3A為說明將介電材料自裝置非本質區域移除之裝置橫截面圖，且圖3B為說明將介電材料自裝置非本質區域移除之裝置俯視圖；圖4A為說明閘極場平板之蒸鍍之裝置橫截面圖，且圖4B為說明閘極場平板之蒸鍍之裝置俯視圖；圖5A為說明多重場平板結構之一實例之裝置橫截面圖，且圖5B為說明多重場平板結構之一實例之裝置俯視圖； 圖6為fmax相關性對閘極指狀物寬度之模擬之圖表；圖7A為說明用於減少之閘極電阻之多重場平板裝置之裝置橫截面圖，且圖7B為說明用於減少之閘極電阻之多重場平板裝置之裝置俯視圖，且圖7C為說明用於減少之閘極電阻之多重場平板裝置之裝置橫截面圖；圖8為基於氮化物HEMT(高電子遷移率電晶體)裝置之單位單元之圖解橫截面圖；圖9為具有與如圖8所說明之裝置不同的組態之基於氮化物HEMT裝置之單位單元的圖解橫截面圖；且圖10為說明基於裝置效能之場平板距離之效應之圖表。
在較佳實施例之以下描述中，參看形成其一部分之隨附圖示，且其中藉由說明本發明可能實施之一特定實施例來展示。應瞭解，可利用其它實施例，且可在未脫離本發明之範疇的情況下對結構加以改變。
概述
本發明描述了用於實現場效應電晶體(FET)之單一或多重閘極場平板結構的簡單製造方法。本發明使用介電材料沈積或生長、介電材料蝕刻及金屬蒸鍍之簡單及通常可良好控制的連續處理步驟。
製造方法
圖1A、1B、2A、2B、3A、3B、4A及4B說明了根據本發明之一實施例之一可能實現之製造方法的步驟，其中該製造方法包含用於製造閘極場平板之方法。
圖1A為場效應電晶體(FET)之橫截面圖，且圖1B為場效應電晶體(FET)10之俯視圖，該場效應電晶體包括源極及汲極歐姆接觸件12及14、一閘極接觸件16及一作用區域18。將製造方法之步驟應用於場效 應電晶體10或其它裝置。該方法通常包含執行介電材料沈積或生長、介電材料蝕刻及金屬蒸鍍以建立在裝置之表面上之一個或一個以上之場平板的連續步驟，其中該等步驟允許基於場平板運作之嚴密控制，且其中沈積於表面上之介電材料不需要自作用區域18移除，進而能夠在無需使用低損壞介電材料之乾式或濕式蝕刻製程的狀況下實現場平板裝置。所執行的步驟進一步包括以下步驟：(1)在裝置之本質區域及非本質區域上使介電材料沈積或生長，其中為達成裝置之適當運作而控制介電材料的厚度；(2)藉由乾式或濕式製程或藉由起離製程圖案化介電材料，使得介電材料主要保持於裝置之作用區域上；及(3)蒸鍍在經圖案化之介電材料上之場平板，其中至少在非本質區域之一側使閘極及場平板接觸件電短路，以在其間提供低電阻連接。將結合圖2A、2B、3A、3B、4A及4B而在下文更詳細地描述該等步驟。
圖2A為說明製造方法之第一步驟之裝置橫截面圖，且圖2B為說明製造方法之第一步驟之裝置俯視圖，該步驟包含在裝置10之本質區域及非本質區域上使介電材料20沈積或生長。為達成完成的裝置10之適當運作，介電材料20之厚度為被控制之關鍵參數。然而，在諸如PECVD(電漿增強化學氣相沈積)之多數沈積/生長技術中，此通常為可良好控制方法。典型材料為氮化矽及二氧化矽，但是，可使用其它材料，只要其可藉由乾式或濕式蝕刻法或藉由起離法而圖案化。
圖3A為說明製造方法之第二步驟之裝置橫截面圖，且圖3B為說明製造方法之第二步驟之裝置俯視圖，該步驟包含藉由蝕刻或自裝置非本質區域22移除而圖案化介電材料20，使得介電材料20主要保持於裝置10之作用區域18上。在藉由蝕刻而形成圖案之狀況下，應強調，在該步驟期間將保護裝置10之表面，防止作用區域18之表面對於可能導致在形成裝置之半導體材料中之損壞的任何乾式或濕式蝕刻製程的任何曝露。在該步驟後，歐姆接觸件12、14以及位於裝置非本質區域 22之閘極部分16為電可存取的。
圖4A為說明製造方法之第三步驟之裝置橫截面圖，且圖4B為說明製造方法之第三步驟之裝置俯視圖，該步驟包含在經圖案化之介電材料20上建立場平板24，其中至少在非本質區域之一側使閘極16及場平板24接觸件電短路，以在其間提供低電阻連接。較佳使用金屬蒸鍍以形成場平板24，其中場平板24包括金屬條或接觸件。場平板24定位於閘極16汲極存取區域，進而提供調變作用區域18的能力，而導致減小妨礙在大射頻訊號下適當的裝置運作之表面俘獲效應。將場平板24連接至裝置本質區域之兩側，且至少在非本質區域22之一側使閘極16及場平板24電短路，以在其兩金屬線之間提供低電阻連接。使場平板24之偏移及長度關於目標裝置效能(如崩潰電壓、射頻效能等)最佳化。
若需要多重場平板結構，則可重複如圖2A、2B、3A、3B、4A及4B所示之介電材料沈積/生長、介電材料蝕刻及金屬蒸鍍的三個步驟。
圖5A為說明一實例之裝置橫截面圖，且圖5B為說明一實例之裝置俯視圖，其係為減少閘極電阻而使用多重閘極場平板來建立多重連接，進而改良較大周邊裝置及/或次微米閘極裝置之效能的實例。該實例為二重場平板結構，該結構包括另一層介電材料26及由金屬條或接觸件構成之另一場平板28。製造方法的參數包含關於閘極16及其它場平板24之介電材料26之厚度、場平板28之長度及偏移，以及引入之場平板24、28之數目。使用多重場平板24、28允許在裝置10之設計中更自由，且在實現高電壓裝置10中具有顯著影響。
本發明之另一優點為能夠減輕因較大周邊裝置中之閘極電阻而造成降低RF效能。通常，在由於閘極電阻增加而導致閘極指狀物寬度增加之情況下，最大振盪頻率(fmax)會隨之減小。
圖6為fmax相關性對閘極指狀物寬度之模擬之圖表。如圖表所示，引入在作用區域之兩端上短路之場平板結構可改良具有較大指狀物寬度之裝置之fmax效能。使用具有與閘極電阻Rg相等之電阻Rf之場平板且將其連接至作用區域之兩側可顯著改良fmax效能。可藉由降低場平板電阻而達成進一步改良。應強調，僅當若藉由場平板結構而加入之寄生電容與本質裝置之寄生電容相比可忽略時，則可觀察到該減小。此可藉由介電材料及其厚度之適當選擇而達成，且必須考慮其作為最佳方法。
在閘極及場平板之間之多重連接亦導致閘極電阻之顯著減少。為在不使RF運作嚴重降級的情況下達成該多重連接，在閘極沈積前蝕刻作用區域之一小部分，以建立在閘極及場平板之間之多重連接，而不使裝置RF運作降級。
在該區域中，可連接閘極及場平板而不對裝置引入任何額外寄生電容。此外，僅當若引入之寄生電容與本質裝置之寄生電容相比較小時，則改良裝置效能。此外，在個別作用區域之間之使用間隔以設計裝置之熱阻抗，其比使用習之技術之裝置更有效。
關鍵參數為介電材料、介電材料之厚度及場平板之長度的選擇。必須考慮該等關鍵參數作為建議之製造方法之最佳化步驟。
使用該方法允許製造具有減小之數目之空橋的較大周邊裝置。此外，次微米裝置之製造可利用本發明。通常，因為與標準閘極形狀相比T形減少了閘極電阻，所以使用T形方法製造次微米裝置。即使使用次微米閘極，可藉由建立多重連接而無T形方法來達成低閘極電阻。
此外，可藉由適當調整介電材料厚度，而將平行閘極接觸件沈積於介電材料上，以藉由使用在裝置之非本質區域上之平行場平板而建立多重連接來顯著減少閘極電阻。藉由平行場平板，藉由在閘極及 場平板之間發生連接處之厚度的適當選擇而提供低電阻路徑。
圖7A為說明用於減少之閘極電阻之多重場平板結構之實例的裝置橫截面圖，且圖7B為說明用於減少閘極電阻之多重場平板結構之實例的裝置俯視圖，且圖7C為說明用於減少閘極電阻之多重場平板結構之實例的裝置橫截面圖。此外，具有覆蓋閘極源極存取區域之場平板(如圖7A、7B及7C所示)亦用於調變源極存取電阻以改良裝置線性效能。
具有場平板之基於氮化鎵之高電子遷移率電晶體
包括AlGaN/GaN高電阻遷移率電晶體(HEMT)之基於GaN之電晶體能夠在RF、微波及毫米波頻率下以高電壓及高功率運作。然而，電子俘獲及在DC及RF特性之間的隨後之差異限制了該等裝置之效能。SiN鈍化已經成功地應用於減輕該俘獲問題，長生具有在10GHz下之10W/mm之功率密度之高效能裝置。舉例而言，[3]揭示一種用於減少在GaN電晶體中之俘獲效應之方法及結構。然而，由於高電場存在於該等結構中，電荷俘獲仍為一問題。
本發明已成功用於改良AlGaN/GaN HEMT功率裝置之效能。在4GHz運作下，對於在藍寶石及碳化矽基板上之裝置已分別達成為12W/mm及18.8W/mm的功率密度。由於涉及場平板之製造的處理步驟的簡單性，本發明可用於AlGaN/GaN HEMT技術及其它半導體裝置的開發。使用適當設計之多重場平板可大大改良該等裝置中之崩潰及較大RF訊號效能。
基於GaN之HEMT包括一通道層及在通道層上之一障壁層。與障壁層接觸形成金屬源極及汲極歐姆接觸件。閘極接觸件形成於在源極及汲極接觸件之間之障壁層上，且間隔層形成於障壁層上方。間隔層可在形成閘極接觸件之前或之後形成。間隔層可包括介電層、未摻雜或耗盡之AlxGa1-xN(0<=x<=1)材料層、或其組合。導電場平板形成於 間隔層上方，且自閘極接觸件之邊緣朝向汲極接觸件延伸距離Lf(場平板距離)。場平板可電連接至閘極接觸件。在一些實施例中，在相同沈積步驟期間場平板作為閘極接觸件之延伸而形成。在其它實施例中，場平板及閘極接觸件在分開的沈積步驟中形成。該排列可減少在裝置中之峰值電場，導致增大崩潰電壓且減小俘獲。電場之減小亦可產生其它利益，例如減小漏電流及增強可靠性。
在圖8中說明了本發明之一實施，該圖為基於氮化物之HEMT裝置之單位單元30之圖解橫截面圖。詳言之，裝置30包括一基板32，其可包含碳化矽、藍寶石、尖晶石、ZnO、矽或能夠支撐第三族氮化物材料之生長的任何其它材料。藉由諸如MOCVD(有機金屬氣相沈積法)、HVPE(氫化物氣相磊晶法)及MBE(分子束磊晶法)之磊晶生長方法使AlzGa1-zN(0<=z<=1)長晶層34在該基板32上生長。長晶層34之形成可視基板32之材料而定。舉例而言，在參考文獻[4]及[5]中教示了在各種基板上形成長晶層34之方法。在參考文獻[6]、[7]及[8]中揭示了在碳化矽基板之上形成長晶層之方法。
高電阻率第三族氮化物通道層36形成於長晶層34上。通道層36可包含AlxGayIn(1-x-y)N(0<=x<=1,0<=y<=1,x+y<=1)。接著，AlxGa1-xN(0<=x<=1)障壁層38形成於通道層36上。通道層36及障壁層38各可包含子層，該等子層可包含第三族氮化物材料之摻雜或未摻雜層。在參考文獻[3]、[9]、[10]、[11]及[12]中說明了例示性結構。在參考文獻[13]及[14]中說明了其它基於氮化物之HEMT結構。
在圖8中說明之實施例中，第三族氮化物半導體間隔層40生長於AlxGa1-xN障壁層28上。間隔層40可具有均勻或分級組合物。間隔層40可被摻雜及/或可被設計為當生長時完全耗盡。
所形成源極42及汲極44電極使歐姆接觸件通過障壁層38，使得當閘電極46以適當位準偏壓時，電流在源極電極及汲極電極42、44之 間經由在通道層36及障壁層38之間之異介面產生之二維電子氣(2DEG)，而流動。在以上引用之專利案及公開案中詳細描述了源極電極及汲極電極42、44之形成。
可蝕刻間隔層40且沈積閘電極46，使得閘電極46之底部位於障壁層38之表面上。形成閘極電極46之金屬可被圖案化，以延伸通過間隔層40，使得閘極46之頂部形成自閘極46之邊緣朝向汲極44延伸距離Lf的場平板結構48。換言之，基於間隔層40之閘極46金屬之部分來形成磊晶場平板48。最後，以介電鈍化層50(如氮化矽)覆蓋該結構。在以上引用之專利案及公開案中詳細描述了形成介電鈍化層50之方法。
在圖9中說明了本發明之其它實施例，該圖為具有與圖8所說明之裝置不同組態之基於氮化物之HEMT裝置之單位單元30的圖解橫截面圖。在圖9中說明之裝置30中之基板32、長晶層34、通道層36及障壁層38類似於在圖8中說明之相應的層。在一些實施例中，基板32包含可自Cree,Inc.of Durham N.C,購得之半絕緣4H-SiC，長晶層34由AlN形成，且通道層36包含GaN：Fe之2μm厚度層，而障壁層38包含0.8nm之AlN及22.5nm之AlxGa1-xN，其中x=0.195，如PL(光致發光)所量測的。
閘電極46形成於障壁層38形成後且鈍化層50沈積於裝置上。然後，場平板48形成於鈍化層50上，該場平板與閘極46重疊且在閘極汲極區域中延伸距離Lf。在圖9中所說明之實施例中，鈍化層50作為用於場平板48之間隔層。在閘極46上方之場平板48之重疊及在閘極汲極區域中之延伸的量為達成最佳結果可變化。場平板48及閘極46可以通路或其它連接件電連接(未圖示)。
在一些實施例中，場平板48可延伸0.2μm至1μm之距離Lf。在一些實施例中，場平板48可延伸0.5μm至0.9μm之距離Lf。在較佳實施例中，場平板48可延伸0.7μm之距離Lf。
建構且測試根據圖9之實施例之基於GaN的HEMT結構。該裝置可在120V及4GHz下運作而達成具有55%之功率增加效率(PAE)之32W/mm的功率密度。
測試基於裝置效能之場平板距離(Lf)的效果。通常根據圖9之實施例製造裝置，除場平板長度Lf自0至0.9μm之距離變化外。然後量測所得裝置之PAE。如圖10所說明的，一旦場平板長度延伸至0.5μm(最佳長度為約0.7μm)，則PAE展示出改良。然而，最佳長度可視特定裝置設計及運作電壓與頻率而定。
參考文獻
以下文獻以引用方式併入本文中：
[1] K Asano等人"Novel High Power AlGaAs/GaAs HFET with a Field-Modulating Plate Operated at 35V Drain Voltage," IEDM Conference, 1998，第59至62頁。
[2] Y. Ando等人"10-W/mm AlGaN-GaN HFET With a Field Modulating Plate," IEEE Electron Device Letters，第24卷，No. 5, 2003年5月，第289至291頁。
[3] 2003年7月1日頒予Wu等人之題為"Group III nitride based FETs and HEMTs with reduced trapping and method for producing the same."的美國專利第6,586,781號
[4] 1994年3月1日頒予Nakamura之題為"Crystal growth method for gallium nitride-based compound semiconductor."的美國專利第5,290,393號
[5] 1997年11月11日頒予Moustakas之題為"Highly insulating monocrystalline gallium nitride thin films."的美國專利第5,686,738號
[6] 1995年2月28日頒予Edmond等人之題為"buffer structure between silicon carbide and gallium nitride and resulting semiconductor devices."的美國專利第5,393,993號
[7] 1996年6月4日頒予Edmond等人之題為"vertical geometry light emitting diode with group III nitride active layer and extended lifetime."的美國專利第5,523,589號
[8] 1998年4月14日頒予Edmond等人之題為"double heterojunction light emitting diode with gallium nitride active layer."的美國專利第5,739,554號
[9] 2001年11月13日頒予Sheppard等人之題為"nitride based transistors on semi-insulating silicon carbide substrates."的美國專利第6,316,793號
[10] 2003年4月15日頒予Smith之題為"aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment."的美國專利第6,548,333號
[11] 2002年11月14日由Chavarkar、Prashant等人公開之題為"group-III nitride based high electron mobility transistor (HEMT) with barrier/spacer layer."的美國專利申請公開案No. 2002/0167023
[12] 2003年1月30日由Parikh、Primit等人公開之題為"insulating gate AlGaN/GaN HEMT."的美國專利申請公開案No. 2003/0020092
[13] 1993年3月9日頒予Khan等人之題為"high electron mobility transistor with GaN/AlxGa1-xN heterojunctions."的美國專利第5,192,987號
[14] 1994年3月22日頒予Khan等人之題為"Method of making a high electron mobility transistor."的美國專利第5,296,395號
[15] Y. -F. Wu, A. Saxler, M. Moore, R.P. Smith, S. Sheppard, P.M. Chavarkar, T. Wisleder, U.K. Mishra, P. Parikh, 0 W/mm GaN HEMTs by field plate optimization IEEE EDL，第25卷，No.3，第117至119頁，2004年3月
[16] S. Karmalkar, U.K. Mishra, Very high voltage AlGaN-GaN HEMT using a field plate deposited on a stepped insulator, Solid State Electronics, 45 (2001) 1645-1652.
結論
在此結束對本發明之較佳實施例之描述。為達成說明及描述之目的，已經提出了本發明之一個或一個以上之實施例之上述描述。吾人不希望窮舉，或將本發明限制為所揭示之精確形式。根據上述教示，可存在許多修正及改變。吾人希望本發明之範疇未被該詳細描述所限制，而藉由附加之申請專利範圍限制本發明之範疇。
10‧‧‧場效應電晶體
12,14‧‧‧歐姆接觸件
16‧‧‧閘極接觸件
18‧‧‧作用區域
20‧‧‧介電材料
22‧‧‧裝置非本質區域
24‧‧‧場平板
26‧‧‧介電材料
28‧‧‧場平板

Claims (30)

  1. 一種電晶體，其包含：一半導體層；一閘極，其位於該半導體層上或位於該半導體層上方；介電材料，其位於該半導體層及一裝置之閘極上；及一或多個場平板，其位於該介電材料上，其中該介電材料並未被移除以曝露該半導體層。
  2. 如請求項1之電晶體，其中：該電晶體係一場效電晶體；及該等場平板之一或多個中關於該閘極的一或多個偏移、一數目之場平板、該等場平板之一或多個的一或多個長度、該介電材料之一或多個厚度或該閘極及該等場平板之一或多個之間的一或多個電連結係使得該電晶體之最大振盪頻率對於範圍在0-100微米之間的一閘極指狀物寬度係減少0-0.5%。
  3. 如請求項1之電晶體，其中：該電晶體係一場效電晶體；及該等場平板之一或多個中關於該閘極的一或多個偏移、一數目之場平板、該等場平板之一或多個的一或多個長度、該介電材料之一或多個厚度或該閘極及該等場平板之一或多個之間的一或多個電連結係使得該電晶體密度在運作於120V及4GHz時產生具有至少55%之功率增加效率之至少32W/mm的一功率密度。
  4. 如請求項1之電晶體，其中：該電晶體係一場效電晶體；及該等場平板之一或多個中關於該閘極的一或多個偏移、一數 目之場平板、該等場平板之一或多個的一或多個長度、該介電材料之一或多個厚度或該閘極及該等場平板之一或多個之間的一或多個電連結係使得該電晶體具有52-60%之一功率增加效率及包含8W/mm之3dB次方的一輸出功率。
  5. 如請求項4之電晶體，其中該等場平板之一或多個在一閘極汲極存取區域中延伸0.5-1微米之一距離。
  6. 如請求項1之電晶體，其進一步包含在該等場平板與該閘極間的多個場平板及多個連接。
  7. 如請求項6之電晶體，其中：該多個場平板包含位於該介電材料之頂部上的平行場平板，該等平行場平板之至少兩者在該裝置之非本質(extrinsic)區域上係電連接，及該介電材料之一或多個厚度係使得由該等場平板所增加之寄生電容相較於一本質(intrinsic)電晶體之寄生電容係可以忽略的。
  8. 如請求項1之電晶體，其中：(1)該介電材料係位於該電晶體之本質及非本質區域；(2)該介電材料主要保持在該半導體層上；及(3)該閘極及該等場平板之一或多個至少在該電晶體之非本質區域之一側處係電連結。
  9. 如請求項8之電晶體，其中該電連結包含一電短路。
  10. 如請求項8之電晶體，其中該等場平板之一或多個具有一電阻Rf，該電阻Rf係等於一閘極電阻Rg。
  11. 如請求項8之電晶體，其中該等場平板之一或多個係連結至該電晶體之本質區域之兩側。
  12. 如請求項9之電晶體，其進一步包含該閘極及該等場平板之一或 多個之間的多個連結。
  13. 如請求項12之電晶體，其進一步包含一作用區域，其中包含該半導體層之該作用區域的一部分係經蝕刻以製造該閘極及該等場平板之一或多個之間的該多個連結。
  14. 如請求項13之電晶體，其進一步包括包含該半導體層之一作用區域，其中該作用區域被劃分為複數個作用區域且該等作用區域之間的間隔建造該電晶體之一熱阻。
  15. 如請求項13之電晶體，其中該電晶體與不具有該多個連結、不具有主要保持在該半導體層上的該介電材料且不具有該電短路之一電晶體相較之下具有一減小之數目之空橋。
  16. 如請求項13之電晶體，其不具有一T形連結。
  17. 如請求項13之電晶體，其中該等場平板之一或多個覆蓋一閘極源極存取區域。
  18. 如請求項1之電晶體，其中該電晶體係以基於氮化物之一高電子遷移率電晶體(HEMT)。
  19. 如請求項1之電晶體，其中該閘極及該等場平板之一或多個至少在該電晶體之一非本質區域中係電連結。
  20. 如請求項11之電晶體，其中該閘極係直接位於該半導體層上。
  21. 如請求項1之電晶體，其中該閘極及該等場平板之一或多個僅在該電晶體之一非本質區域之一或多側處係電連結。
  22. 如請求項1之電晶體，其中該電晶體係一高電子遷移率電晶體(HEMT)且該半導體層係形成於該HEMT之一導電通道之一作用區域之部分。
  23. 如請求項1之電晶體，其中該電晶體之源極接點及該等場平板之一或多個係電連結的。
  24. 如請求項1之電晶體，其中該電晶體係一第三族氮化物場效電晶 體，且該半導體層包含在一通道上之一障壁層使得一二維電子氣被限制於該通道層中。
  25. 如請求項24之電晶體，其中該障壁係AlGaN且該通道係GaN。
  26. 如請求項1之電晶體，其進一步包含在該等場平板之間的多個場平板及額外介電材料。
  27. 如請求項1之電晶體，其中該電晶體係一高電子遷移率電晶體。
  28. 如請求項1之電晶體，其中該一或多個場平板係位於被蝕刻之介電材料上。。
  29. 如請求項1之電晶體，其中該等場平板之至少一者係電連結至該閘極。
  30. 如請求項1之電晶體，其進一步包含連接至該等場平板之一或多個之一源極接點，其中電連結至該源極接點之該場平板之該一或多個係並未電連結至該閘極。
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US20070059873A1 (en) 2007-03-15
US9496353B2 (en) 2016-11-15
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US20170025506A1 (en) 2017-01-26
US10109713B2 (en) 2018-10-23
TWI430341B (zh) 2014-03-11
CN1853261A (zh) 2006-10-25
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