TW511190B - Non-volatile semiconductor memory device with multi-layer gate insulating structure - Google Patents

Abstract

A non-volatile semiconductor memory device with a multi-layer gate insulating structure is provided. The non-volatile semiconductor memory device comprises a gate insulating structure formed between a gate and a channel region, which includes a top silicon nitride layer, an intermediate silicon nitride layer and a bottom silicon nitride layer. When an electric field is applied between the gate and a drain region beside the channel region, hot carriers exhibit a direct tunneling across the bottom silicon nitride layer from the drain region for a write-erase operation. The hot carriers having exhibited the direct tunneling from the drain region are trapped into the intermediate silicon nitride layer.

Description

V. Description of the invention (l) 5-1 Field of the invention The present invention relates to a non- 揎, a type having multiple 閛 -pole insulation; 2 = 圮 memory element, especially a part. Theta structure & non-volatile memory cell 5-2 Background of the invention ... Semiconductors used in microprocessors When the power supply is interrupted, it is stored in this period as volatile. Missed. One solution is to use the eight-n & two-body element's lean material to be completely fluid. For example-battery power or capacitors, U 3: When the memory is interrupted, the stored data: The known non-volatile memory element is a charge trapping device. Examples of complexes include metal-nitride-oxide-semiconductor (MN0S) memory devices, silicon-nitride-oxide_semiconductor (SN0S) memory devices, and silicon-nitride-nitride-oxide-semiconductor ( SONOS) memory element. A typical metal-nitride-oxide-semiconductor (MNOS) memory device is shown in the first figure. The metal-nitride-oxide-semiconductor (MN0s) memory device 1 includes a semiconductor substrate 10, a source / drain 1 formed on the semiconductor substrate 10, and a pair of source / drain electrodes. One pass between poles 1 and 1,

Page 5 511190, description of the invention (2) channel region 1 2. a silicon dioxide layer 1 formed on the channel region 12 2, a silicon nitride layer 14 formed on the silicon dioxide layer 13 and formation One of the aluminum gates 15 on the nitrided layer 14. When this metal-nitride-oxide-semiconductor (MN0S) memory element performs a write operation, a positive voltage is applied to the gate so that an electric field spans the four stacks (1 (), 13). , 14, 15), and further generate hot electrons on the surface of the semiconductor substrate 10. These hot electrons will pass through the Fowler-Nordheim penetration effect or Mr ^ ect tunneling effect, pass through the silicon dioxide layer 13 and be captured in the silicon dioxide layer 13 and The interface between the silicon nitride layers 1 to 4. … When a clear operation is performed, a negative voltage is applied to the gate, so that the electrons trapped between the two-layer interface can perform the Fowler-Nordheim penetration effect in the reverse direction or the direct penetration in the opposite direction The effect (direct tunneling) passes through the silicon dioxide layer i 3 and enters the semiconductor substrate 10. By &, electrons are emitted from the interface between the dioxin layer i 3 and the nitrided dream layer 丄 4. When performing a write operation, although the large silicon oxide layer 13 and the silicon nitride layer 1 4 tend to penetrate the silicon nitride layer 14. Causes unnecessary electric fields. Even if an unnecessary electric field tends to trap most of the thermoelectronic systems trapped in the dioxide, the thermoelectric voltage of a small number of thermoelectrics penetrating the silicon nitride layer 14 is applied to the gate. Non-essential layer 1 3 and silicon nitride layer 1 4 511190

V. Description of the invention (3) The electrons at the interface of (3) are gradually emitted through the stone dioxide layer 3 through the reverse penetration effect. This phenomenon prevents the data electrons at the interface between the silicon dioxide layer 13 and the silicon nitride layer 4 from being easily captured at this interface, or prevents this type of memory device from storing data for a long time. '' In order to improve the charge retention of the metal-nitride-oxide-semiconductor (MN0s) memory element 1, there are many silicon-nitride-oxide-semiconductor (SN0S) memories. The component is generated. / This_ Polycrystalline Silicon-Nitride-Oxide-Semiconductor (SN0S) memory device: The nitride layer is deposited by low-pressure chemical vapor deposition, and hydrogen annealing is used to improve the noise of the nitride layer and the oxide. Interface characteristics. The occupancy characteristics of the polycrystalline silicon-nitride-oxide-semiconductor (s / 0s ^ memory element are two as the thickness of the nitride layer is reduced. However, when the thickness of the nitride layer is reduced, the gate electrode is also improved The hole ejection effect. | To solve this problem, a top oxide layer was formed between the closed electrode and the layer, so a polycrystalline silicon-nitride-oxide-semiconductor (sonos) memory device was developed. The system shown in Fig. 12 is a typical polycrystalline silicon-oxide-nitride-oxy- + conductor (S0N0S) memory element 2, which includes a breast 20 and is formed in a body of morpholine. A source / drain 2 in the hand base 2 〇 A channel area 2 located between a pair of source / drain 2 1 2. Open the J 1 area? ^ ζ ON > W 2 =: oxidized oxide layer 2 3. An intermediate silicon nitride layer 2 formed on the bottom two I Β 4. formed on the intermediate nitride 511190 5. Description of the invention (4) Silicon dioxide ~ Nohan (substrate 20 volts pass through the hole in the polycrystalline silicon gate. With Fowler-one of the main pairs of components can be-Nohan also need to spend a top layer 2 4 A portion of the silicon dioxide layer 25 and a polycrystalline silicon gate 26 formed on the top layer 25. By the electron Fowler-Nordheim penetration effect, electrons enter the intermediate silicon nitride layer 2 4 from the semiconductor to perform writing In order to perform the clearing operation, Fowler-Nordheim penetrating effect can be achieved through the Fowler-Nordheim penetration effect. A The disadvantage is that a high electric field needs to be applied. This-Shi = Reliability and endurance characteristic have a very important effect. Fowler-Nordheim penetrating effect is used to write for a long time. According to Therefore, there is an urgent need to provide a new, non-volatile memory element that can overcome the non-volatile loss of the m, marginal layer structure. "It overcomes the above-mentioned conventional non-volatile memory element 5-3 invention objectives and summary: present The main purpose of the invention is to provide a middle silicon nitride layer and a top tube, a kind of gate insulation layer structure with a bottom silicon nitride layer, a non-volatile memory element, and a complex silicon layer. The low energy barrier makes this invention: J :::::; Zhen layer Carrier ejection to perform the writing of data and the heat of Tongnan efficiency ^ 丄 i 丄 yu

Another purpose of the present invention is to provide a gate insulating layer having a bottom silicon nitride layer, a # m ^ " layer, and a top silicon nitride layer. , Which can be stored in intermediate silicon nitride; t € "# ^ ^ ^ ^ ^ (retention characteristic -SIIJ ::: f provides-a kind of silicon nitride layer with a bottom, non-volatile 圮 丨 咅 ^ _ The memory element of the present invention constructed with a gate insulating layer, which is one of the silicon layers, is advantageous for miniaturization. It is based on the non-volatile semiconductor conductivity of the non-edge layer of the insulating layer and the second nitride chip. It is located above the half-way region between one pole of the semiconductor substrate, and the silicon nitride layer on the silicon nitride layer is inside the semiconductor layer. The above-mentioned volatile semi-conductive semiconductor substrate has a source / sink. The second silicon nitride system of the third conductor substrate of the polar layer is formed on the first layer. When an electric field substrate is directly penetrated, the body memory element memory element of the present invention is electrically connected to the first and first channel region silicon nitride layer and the surface. And on the surface. The second layer is formed in a nitride layer The gate electrode is provided with a first nitride device. The device includes a first nitride layer and a first nitride layer. The source channel region is located in a silicon nitride layer and a first nitride layer. Above. When the gate system is between the gate and the electrode, the silicon layer is trapped in the second layer of the gate. The gate is a conductive one of the first layer, the electrode / drain source, and the first layer, and the second layer. 5. Pingren-Nitride V. Description of the invention (6) 5 4 Detailed description of She Mingyang · The present invention provides a right-side memory element. &Amp; Gate structure t = f-Non-volatile semiconductor layer: Section: Insulation The layer system is formed on the first insulation layer of the three-layer insulation system of the same material. A conductive layer is formed on a substrate and a second insulating layer and is used as a free electrode. The layer is formed on the second insulating layer and the non-volatile memory is formed on the third insulating layer. The crystal element of the present invention is non-volatile :: == Sexual memory electrical »Layer structure of the non-volatile semiconductor ( One: + Conductor substrate contains -P-type Shixi substrate 3 0. A pair of " 1 and distance The buried diffusion region 1 is formed in the P-type silicon substrate 30 for the source / drain 3 i. The _N channel 3 2 is a P-type silicon substrate 30 between the source / drain 31 1. Medium. A first silicon nitride layer 33 having a thickness of about 400 to 2000 angstroms is formed over the ν channel 32. It has a second silicon nitride layer having a thickness of about 40 to 100 angstroms. The 3 4 series is formed on the first silicon nitride layer 3 3. The third silicon nitride layer 3 having a thickness of about 40 to 100 angstroms is formed on the second silicon nitride layer 34. A conductive layer For example, a polycrystalline silicon layer 36 is formed on the third silicon nitride layer 35. The first nitrided layer 34 is used as a charge trapping layer.

Page 10 511190 V. Description of the invention (7) 5 is used as a layer), and the first silicon nitride layer 33 and the third silicon nitride layer are tunneling iayers. The hot electrons emitted through the channel of the drain terminal pass through the bottom penetrating layer, namely the D dagger stone layer 33, and enter the intermediate capture layer, that is, the second nitride stone layer C Μ Μ local native evening spar crystal stone " " Nitride stone " " Silicon Nitride—Silicon Nitride_Semiconductor (Ming ?! Should be non-volatile memory device silicon: the operation steps are as follows: the first operating voltage is given to the second Layer = Shi Xi base 30 to open N channel 32, and a voltage is applied between the drain terminal 31 and the source terminal 31 to induce a shot, production, and hot electrons. These hot electrons pass through the first Silicon nitride layer 3 3: Into a silicon layer 3 4. Preferably, the first operating voltage is about: The operating voltage of the second and second brothers is about 2 5 ~ 5 volts | Volt. The silicon substrate 3 and the source are connected by Fowler-Nordheim in humans; the polycrystalline silicon-nitriding of the present invention should be performed. ^, So that the hole effect (leakage NS) class is non-volatile. A nitrogen oxide semiconductor system is made by N channel 3 2 emitting cold thunder, π ~ 1 #; its-3 4 VA 3 3 ^, T ^ ^, shell material removal operation conditions are as follows: 正; -Positive Partial MP (Osltlve blas) on Shixi substrate 30 and 12 (Ve blas) on polycrystalline stone layer 36, and Enoch (F: N: dheim) channel cold hole via the -nitride stone Layer; #: 二: Γ 夕 layer 3 4. Preferably, the bias voltage of the polycrystalline silicon layer 36 is about 6 to 10 volts and the bias of the dream substrate 30 is about 0 to 5 volts. Black

V. Description of the invention (8) The fourth picture is that the electrons and holes are not intended with respect to the __Weng. The energy barrier for the bottom penetrating layer sand to develop the energy barrier of layer 3 3 is about 2.1 electron volts, which is lower than the energy barrier provided by the layer 3 3 to electrons of about 3.2 electron volts. The first nitrogen: two 2 = about U volts for electrons, which is also lower than dioxygen; energy barrier for electron volts for holes. According to the dagger, the hair / supply hole is about 4.8-silicon nitride-semiconductor (SNNNS) Xi Ba silicon-lice silicon-silicon nitride first nitride layer 3 3 for the bottom body Element 3 uses a division operation, which can provide high-efficiency plutonium carriers; the write and clear layer of the ^ lean material has a high dielectric constant, which is conducive to the miniaturization of the second silicon nitride to reduce data writing. Man and clear wrestling ^ = the shrinkage of 70 pieces of the body, the work-preparation λ · γ, the fine working voltage of Yuechen Su Zuo. Development of the present invention; / Volume stone fossil eve-power consumption of the semiconductor (snnns) non-volatile body 3 can also be reduced. The third nitrogen cut layer 3 of 2 has very good quality and nitrides (traps), and the hot electrons will not easily penetrate the third r. It can avoid the inconvenience caused by the penetration of the hot electrons and trapped in the third. The necessary electric field. Therefore, the retention characteristics (characteristics) of the electronic data stored in the charge trapping layer, that is, the second nitride stone layer 34 can be improved. The above description is only a preferred embodiment of the present invention, and is not intended to Limits the scope of the claimed patent of the invention; all other equivalent changes or modifications that do not depart from the spirit disclosed by the invention should be included in the following patents-

I P.12 511190

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The first diagram is a cross-sectional view of a conventional fuss-type non-volatile memory element. The cross-section of a conventional 8-type non-volatile memory element. The third diagram is one of the present invention's SNNNS-type non-volatile memory. The schematic diagram of the cross-section of the body element; and the main part of the electron and hole energy barrier shown in the fourth figure to match the gate structure of the third figure 1 10 11 12 131 4 1522 0 part representative symbol: metal-nitride-oxide -Semiconductor (MN〇s) memory element semiconductor substrate source / drain channel region monoxide layer nitride nitride layer non-gate polycrystalline silicon oxide-nitride-oxide-semiconductor (s〇N 〇s) Memory element semiconductor substrate _

Page 14 511190 Brief description of the diagram 2 1 Source / Drain 2 2 Channel area 2 3 Bottom silicon dioxide layer 2 4 Middle silicon nitride layer 2 5 Top silicon dioxide layer 2 6 Polycrystalline silicon gate

3 Polycrystalline silicon-silicon nitride-silicon nitride-silicon nitride-semiconductor (SNNNS-type non-volatile memory element 3 0 P-type silicon substrate 3 1 source / drain 3 2 N channel 3 3 first silicon nitride layer 3 4 Second silicon nitride layer 3 5 Third silicon nitride layer 3 6 Polycrystalline silicon gate

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Claims (1)

511190 Case No. 90127945 Date of Amendment VI. Patent Application Scope 1. A multi-layer (mu 11 i-1 ayer) structure including: a semiconductor layer; a first insulating layer formed on the semiconductor layer, the The first insulating layer has a first dielectric constant and a first thickness; a second insulating layer is formed on the first insulating layer, and the second insulating layer has a second dielectric constant and a second thickness; A third insulating layer is formed on the second insulating layer, the third insulating layer has a third dielectric constant and a third thickness; and a conductive layer is formed on the third insulating layer, When an electric field is applied between the semiconductor layer and the conductive layer, hot carriers pass through the first insulating layer directly from the semiconductor layer and are captured in the second insulating layer. 2. The structure described in item 1 of the scope of the patent application, wherein the above-mentioned first insulating layer comprises silicon nitride. 3. The structure described in item 1 of the scope of the patent application, wherein the above-mentioned second insulating layer comprises silicon nitride. 4. The structure described in item 1 of the scope of the patent application, wherein the third insulating layer mentioned above comprises silicon nitride. 5. The structure according to item 1 of the scope of patent application, wherein the above-mentioned conductive layer comprises polycrystalline stone. Page 15 ------- Case No. 9m? / 7 (U5_ year month __Ξ --- revision_ VI. Application Summary ® " " ~~~ 6 · As described in the second item of the scope of patent application The structure, wherein the first thickness of the first insulating layer is about 40 to 100 angstroms. The structure according to item 3 of the scope of patent application, wherein the second thickness of the second insulating layer is About 40 to 100 angstroms. The structure described in item 4 of the scope of patent application, wherein the third thickness of the third insulating layer is about 40 to 100 angstroms. Multi-layer structure 'which includes · A semiconductor layer; a first silicon nitride layer formed on the semiconductor layer; the silicon nitride layer has a first thickness; a nitrogen-second nitrogen nitride layer is formed on the first layer The silicon nitride layer has a second thickness on the nitride layer. The first and second nitride layers are formed on the second nitride layer. The second silicon nitride layer has a third layer. Thickness; and ^ ^ a conductive layer is formed on the third silicon nitride layer, when an electric field = between the semiconductor layer and the conductive layer, the hot carrier is from the half The conductor layer directly passes through the silicon nitride layer and is captured in the second nitride layer. The structure according to item 9 of the scope of the patent application, wherein the first thickness of the first nitrided layer is about 40 to 100 angstroms. P.16.丄 Π9〇 • The structure described in item 9 of the scope of the patent application, wherein the second thickness of the previous friendly silicon layer is about 40 to 100 angstroms. Brother Yi Liao 12. The structure according to item 9 of the scope of the patent application, wherein the third thickness of the fossil evening layer described above is about 40 to 丨 0 Å. Among them, the above-mentioned conductivity 1 3. The structure as described in item 9 of the scope of patent application, the layer includes polycrystalline silicon. 1 4. A non-volatile semiconductor memory device having multiple gate insulation layers, comprising:. Sifan has a semiconductor substrate with one of the first conductivity; a source / drain with a second conductivity that is opposite to the first conductivity; the source / drain is located on a surface of the semiconductor substrate On ", a channel region is located on the surface of the semiconductor substrate between the source and the drain,-a / silicon nitride layer is formed over the channel region; a second A nitride nitride layer is formed on the first nitride layer; a first > nitride nitride layer is formed on the second nitride layer; and a gate electrode is formed on the third nitride layer On the silicon layer, when an electric field is applied between the gate and the drain, hot carriers pass through the third silicon nitride layer directly from the semiconductor substrate and are captured in the second silicon nitride layer. . Page 17 VI. Application scope of patent 15. The non-volatile semiconductor memory device having a plurality of gate insulating layers as described in item 14 of the scope of the patent application, wherein the above-mentioned first conductivity is any of N-type and p-type conductivity. ^ 16. The non-volatile semiconductor memory device having a multilayer gate insulating layer as described in item 14 of the scope of the patent application, wherein the thickness of the 9th silicon nitride layer is about 40 to 100 angstroms. 9 1 7. The non-volatile semiconductor memory device having a multi-layer gate insulation layer as described in item 4 of the scope of the patent application, wherein the thickness of the second silicon nitride is about 40 to 100 angstroms. 18. The non-volatile semiconductor memory device with multi-layer gate insulation as described in item 14 of the scope of the patent application, wherein the thickness of the third nitride H is about 40 to 100 angstroms. ≪ 19. The non-volatile semiconductor memory device having a plurality of gate insulating layers as described in item 14 of the scope of the patent application, wherein the gate electrode described above contains polycrystalline seconds. 20 · —A method for erasing data of SNNNS-type non-volatile memory cells, the non-volatile memory cells including a p-type semiconductor substrate, a first diffusion region with N-type conductivity, and a second diffusion with N-type conductivity Region, the first diffusion region and the second diffusion region are spaced apart from each other and are located on the semiconductor substrate. The first diffusion is located below the bottom surface of the patent specification in the semiconductor substrate and is located in the semiconductor substrate. A channel region between the region and the expanded region, a polycrystalline silicon gate, and a silicon nitride layer including / on top of the polycrystalline silicon gate and the channel region Layer and one of the bottom silicon nitride layers ^ a pole person & ^ method includes: said correction, the data erasing a negative operating voltage is applied to the polycrystalline silicon gate; and a positive operating voltage is known to the The semiconductor substrate is used to generate an electric field between the ancient silicon gate and the semiconductor substrate, and the electric field is strong enough to generate a channel cold hole through the bottom silicon nitride layer into the intermediate nitride. Silicon sound to perform data clearing . 21 • The data erasing method as described in item 20 of the scope of patent application, wherein the negative operating voltage is about -6 to -10 volts. 2 2 · The data erasing method described in item 20 of the scope of patent application, wherein the positive operating voltage is about 0 to 5 volts. 23. The data erasing method as described in item 20 of the scope of patent application, wherein the negative operating voltage is about -6 to -0 volts and the positive operating voltage is about 0 to 5 volts. Page 19