TW201423947A - 堆疊式功率元件模組 - Google Patents

堆疊式功率元件模組 Download PDF

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Publication number
TW201423947A
TW201423947A TW101146419A TW101146419A TW201423947A TW 201423947 A TW201423947 A TW 201423947A TW 101146419 A TW101146419 A TW 101146419A TW 101146419 A TW101146419 A TW 101146419A TW 201423947 A TW201423947 A TW 201423947A
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Taiwan
Prior art keywords
component
substrate
module
filling layer
stacked power
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TW101146419A
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English (en)
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TWI500135B (zh
Inventor
Yin-Po Hung
Tao-Chih Chang
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Ind Tech Res Inst
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Priority to TW101146419A priority Critical patent/TWI500135B/zh
Priority to CN201310033645.0A priority patent/CN103872027B/zh
Priority to US13/849,553 priority patent/US9142473B2/en
Publication of TW201423947A publication Critical patent/TW201423947A/zh
Application granted granted Critical
Publication of TWI500135B publication Critical patent/TWI500135B/zh

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    • H01L23/3135—Double encapsulation or coating and encapsulation
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Abstract

本發明係關於一種堆疊式功率元件模組，利用垂直導通層完成元件之間的連結，大幅縮短電流傳輸路徑，可避免因利用導通孔或打線方式連結而造成之電流集中或接點被破壞。

Description

堆疊式功率元件模組
本發明是有關於一種半導體元件模組，為有關於一種堆疊式功率元件模組。
目前已商品化功率元件模組之設定上多以二維方式排列元件，並輔以打線連結方式完成電性及訊號導通，功率元件直接貼覆於具散熱效果的基底上，此一排列方式雖然可提高散熱效益，但卻會增加模組面積。同時，大量採用打線連接亦容易造成電流密度不均，而導致元件模組失效。
本發明提供一種堆疊式功率元件模組，至少包括一基底具有一第一表面與一第二表面、至少一第一元件、至少一第二元件、一線路圖案與至少一填充層。該至少一第一元件，位於該基底之該第一表面上並與該基底電性連結；該至少一第二元件，位於該至少一第一元件上並與該基底電性連結；該至少一填充層覆蓋於該基底之該第一表面上且包覆該至少一第一元件與該至少一第二元件，且該至少一填充層包括多個第一導電插塞與至少一第二導電插塞。該線路圖案位於該至少一第二元件之上且位於該至少一填充層上。該線路圖案透過該些第一導電插塞連接該至少一第二元件，該線路圖案透過該至少一第二導電插塞連接該 至少一第一元件，其中該至少一第二導電插塞之高度大於每一該至少一第一導電插塞之高度。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
本發明係關於一種立體堆疊封裝方式，以垂直堆疊方式整合多個晶片與/或封裝結構，可使打線銲點大為減少，也可以顯著減小整體封裝體積、重量，縮短元件的電性連接路徑，從而使電性能獲得提昇；且本架構之設計，更有利於進行散熱模組配置，幫助模組內產生之熱量有效散出。
圖1A-圖1H繪示依照本發明之一實施例之一種堆疊式功率元件模組的製作流程剖面示意圖。
參考圖1A，提供一基底100，用以承載金屬基底12，基底100可於後續製程卸下。金屬基底12例如是一導線架(Lead Frame)120，材質例如是銅或鋁合金金屬。導線架120包括有至少一空陷區122與多個半蝕刻區塊124與側壁區塊126，空陷區122暴露出黏著層101之上表面101a。目前圖中所示半蝕刻區塊124即指導線架120將成為後續電性連接(亦即打線接觸端)的導線架部份，而導線架的側壁區塊126後續可成為電性外接端。導線架120包含不只一個半蝕刻區塊與/或不只一個空陷區，圖中僅顯示出一個，但可代表多個。
本實施例所述之空陷區與導線架之間的相對配置位 置或數目並不限於本發明所述，乃視搭配晶片、元件之種類或封裝結構實際需要調整或變動。
參考圖1B，將第一元件20配置於被金屬基底12之空陷區122所暴露出的黏著層101之上表面101a上。第一元件20例如是一功率元件，如金氧場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)、絕緣柵雙極電晶體(Insulated Gate BipolarTransistor,IGBT)或二極體(diode)等或是已經部份封裝完成的封裝體。對應於配置元件，金屬基底12之每一空陷區塊122內至少配置一元件，金屬基底之空陷區塊122的尺寸至少要大於其所對應承載的元件或晶粒，空陷區塊122之圖案設計可視搭配元件或散熱效率考量而調整。
參考圖1C，形成第一填充層202配置於基底100之上並覆蓋暴露出的上表面101a，包覆第一元件20並填滿第一元件與導線架的側壁區塊126之間空隙。第一填充層材料例如為紫外線固化性聚合物、熱固性聚合物、環氧基樹脂(epoxy resin)、聚醯亞胺(polyimide)或苯基環丁烯(benzocyclobutene，BCB)等，可採用灌膠方式或壓合方式來形成。灌膠製程中，一般會使用模型而便於特定位置注入封膠物質，而在封膠物質經過熱處理或紫外線照射後固化形成填充層202後，再移除模型。壓合方式則將所需厚度之介電材料層直接壓合至導線架120與基底100上，即形成填充層202。以此實施例而言，第一填充層202之厚度約與第一元件20厚度大致相等，至少需暴露出部份第一 元件20之銲墊201及銲墊203；所謂厚度相等也就是第一填充層202之上表面202a約與第一元件20之上表面20a共平面。以此實施例而言，第一填充層202之上表面202a約與半蝕刻區塊124之上表面124a大致共平面。待固化形成填充層202後，可在移除模型時同時移除基底100，也可移除模型後再移除基底100。
參考圖1D，於第一填充層202之上表面202a與第一元件20之上表面20a上形成一導電黏著層204。導電黏著層204之材料例如是：導電性黏膠、銀膏或錫膏等，以塗佈、網印或貼膜方式形成，或以電鍍方式於該處及第二元件30之接觸面形成金屬層，兩者經由熱機製程處理後造成相互擴散，形成介金屬化合物(Intermetallic Compound,IMC)，達到導通效果。
參考圖1E，將第二元件30配置於導電黏著層204上，覆蓋住部份的第一填充層202之上表面202a與部份的第一元件20之銲墊203。第二元件30較佳是與第一元件20部份重疊，而非完全重疊，以暴露出第一、第二元件上的打線銲墊201、301。第一、第二元件20、30可透過導電黏著層204直接達到兩者之間的電性連結。第二元件30例如是一功率元件，如金氧場效電晶體(MOSFET)、絕緣柵雙極電晶體(IGBT)或二極體等或是已經部份封裝完成的封裝體。
參考圖1F，打線形成多個銲線32、34分別連結第一、第二元件20、30與導線架相對應的半蝕刻區塊124。銲線 32之一端連接至第一元件20之銲墊201，而另一端連接至半蝕刻區塊124。銲線34之一端連接至第二元件30之銲墊301，而另一端連接至另一半蝕刻區塊124。
參考圖1G，於第二元件30之接觸墊302上置放一導電塊38位於第二元件30之一端。該導電塊38可以一金屬材質(如銅)所製成，並以如元件20、30相互連接之方式連接，可作為後續電極之用。
參考圖1H，形成第二填充層310配置於第一填充層202之上，包覆第二元件30、銲線32、34、導電塊38與且覆蓋第一元件20及第一填充層202；第二填充層310填滿導線架120側壁126與第二元件30及導電塊38間的空隙。第二填充層310之厚度約與導電塊38厚度大致相等或略低，至少需暴露出部份導電塊38之上表面38a，作為後續電性連結之用。所謂厚度相等也就是第二填充層310之上表面310a約與導電塊38之上表面38a共平面。以此實施例而言，第二填充層310之上表面310a約與導線架側壁部份126之上表面126a大致共平面。第二填充層材料例如為紫外線固化性聚合物、熱固性聚合物、環氧基樹脂(epoxy resin)、聚醯亞胺(polyimide)或苯基環丁烯(benzocyclobutene，BCB)等，可採用灌膠方式或壓合方式來形成。視所包封的元件種類不同，第一、第二填充層可使用相同或不同的材料。而第一、第二填充層所使用的材料更可以是具有高散熱效益的介電材料或更包括一或多種幫助散熱的添加物，如氮化硼顆粒(boron nitride,BN)、二 氧化矽(silica,SiO2)顆粒、氧化鋁(alumina,Al2O3)顆粒等。
圖2A至圖2H繪示依照本發明之另一實施例之一種堆疊式元件模組的製作流程剖面示意圖。
參考圖2A，提供一基底22具有一上表面22a，並設置一第一元件20於其上表面22a上。基底22可以是金屬基底，其材質例如是銅或鋁合金金屬，基底22也可以是印刷電路板、甚或是具金屬線路之陶瓷基底。基底22至少包括一空陷區222，基底22可包括部份連續且部份離散的多個圖案，至少包括一金屬區塊圖案24，其作為第一元件20貼附之位置，亦可幫助散熱。選擇性地，可在金屬區塊圖案24與第一元件20之間形成一黏膠層230，該材料如同前一實施例之導電黏著層204，可以用導電性黏膠、銀膏或錫膏等，以塗佈、網印或貼膜方式形成，或以電鍍方式於該處及第一元件20之接觸面形成金屬層，兩者經由熱機製程處理後造成相互擴散，形成介金屬化合物，達到導通效果。第一元件20例如是功率元件如MOSFET、IGBT或二極體等、可以是晶片的形式甚或是已經部份封裝完成的封裝體。
圖2B，形成第一填充層202配置基底22之上並覆蓋暴露出的上表面22a，且包覆第一元件20。第一填充層材料例如為紫外線固化性聚合物、熱固性聚合物、環氧基樹脂(epoxy resin)、聚醯亞胺(polyimide)或苯基環丁烯(benzocyclobutene，BCB)等，可採用灌膠方式或壓合方式來形成。壓合方式則將所需厚度之介電材料層直接壓合至 基底22之上表面22a上並填滿空陷區222，即形成填充層202。以此實施例而言，第一填充層202之厚度高於第一元件20之厚度；也就是第一填充層202之上表面202a約高於第一元件20之上表面20a。
圖2C，對第一填充層202進行一開口步驟，從第一填充層202上表面202a向下開孔形成第一介層窗206直至第一元件20之上表面20a露出；從第一填充層202上表面202a向下開孔形成第二介層窗208直至基底22之上表面22a露出。第一、第二介層窗可以同時或依序利用機械鑽孔或雷射開孔方式進行。
舉例而言，搭配雷射開孔技術製作介層窗，需控制雷射輸出功率、加工速度與重複加工次數等參數，以達到孔底材料無破壞情形，而使雷射開孔較完整且無須於電氣接墊製作保護層。
圖2D，進行電鍍製程，電鍍一金屬導電物質214覆蓋住第一填充層202之上表面202a並填充至第一、第二介層窗206、208中以形成第一、第二導電插塞216、218，經過圖案化步驟而於第一填充層202之上表面202a上形成第一線路圖案220。該金屬導電物質214的材料例如是銅。第一線路圖案220實際上乃是可作為重佈線路之金屬線路圖案，故亦可視為重佈線路圖案。
參考圖2E，設置一第二元件30於金屬導電物質214上表面上。選擇性地，可在金屬導電物質214與第二元件30之間形成一黏膠層330，可以用導電性黏膠、銀膏或錫 膏等，以塗佈、網印或貼膜方式形成，或以電鍍方式於該處及第二元件30之接觸面形成金屬層，兩者經由熱機製程處理後造成相互擴散，形成介金屬化合物，達到導通效果。第二元件30例如是功率元件如MOSFET、IGBT或二極體等、晶片甚或是已經部份封裝完成的封裝體。第一元件20與第二元件30可為不同功能或材質之元件。
圖2F，形成第二填充層310配置基底22之上並覆蓋金屬導電物質214與暴露出的第一填充層202上表面202a，且包覆第二元件30。第二填充層材料例如為紫外線固化性聚合物、熱固性聚合物、環氧基樹脂(epoxy resin)、聚醯亞胺(polyimide)或苯基環丁烯(benzocyclobutene，BCB)等，可採用灌膠方式或壓合方式來形成。以此實施例而言，第二填充層310之高度高於第二元件30之高度；也就是第二填充層310之上表面310a約高於第二元件30之上表面30a。
圖2G，對第二填充層310進行一開口步驟，從第二填充層310之上表面310a向下開孔形成第三介層窗306直至第二元件30之上表面30a露出；從第二填充層310之上表面310a向下開孔形成第四介層窗308直至金屬導電物質214露出。第三、第四介層窗可以同時或依序利用機械鑽孔或雷射開孔方式進行。
圖2H，進行電鍍製程，電鍍一金屬導電物質314覆蓋住第二填充層310之上表面310a並填充至第三、第四介層窗306、308中以形成第三、第四導電插塞316、318， 經過圖案化步驟而於第二填充層310之上表面310a上形成第二線路圖案320。第二線路圖案320實際上乃是可作為重佈線路之金屬線路圖案，故亦可視為重佈線路圖案。
本實施例所述之介層窗/導電插塞與元件之間的相對配置位置或數目並不限於本發明實施例所述，可視元件之種類或實際產品實際需要調整或變動。同樣地，重佈線路金屬圖案之圖案設計也視上下堆疊元件之電性連接端點或電性要求而變化調整。本發明實施例所述導電插塞實際上也可以是增層導通孔，端視開口大小與導電物質填充度而定，通常以電鍍製程形成。
圖3為本發明之一實施例之一種堆疊式元件模組的剖面示意圖。參照圖3，半導體封裝模組400包括一基底410、至少一第一元件420、至少一第二元件430、至少一填充層440、至少一電極450以及多個銲線460。
基底410設計具有至少一下陷區412、至少一平台區414與位於側邊的外接側壁區塊416。基底410例如是多層印刷電路板或是疊合電路板，可透過壓合金屬板與介電層而製得，更可包括內接線路與金屬導電插塞或貫孔。
參照圖3，第一元件420設置於基底410之下陷區412之上表面412a上，而第二元件430設置於該第一元件420之上表面420a上並覆蓋部份平台區上表面414a。該電極450設置於該第二元件430上表面430a上，該填充層440覆蓋於基底410之上且填滿元件與外接側壁區塊416間的空隙，並包覆銲線460。電極450位於第二元件430上表 面430a上，但至少部份電極450上表面是露出於填充層440，以便外接。電極450實際上也是特定形狀的金屬圖案或線路圖案之一部分，其形狀視產品設計要求而定。
參照圖3，第二元件430與第一元件420部份重疊，而非完全重疊，以暴露出第一、第二元件上的打線銲墊421、431，而下陷區412之深度約與第一元件420厚度相當，使疊於第一元件上之第二元件430可平坦地部份設置於平台區414。多個銲線460分別連結第一、第二元件420、430至相對應的基底410之下陷區412與平台區414。銲線460之一端連接至第一元件420之銲墊421，而另一端連接至下陷區412。銲線460之一端連接至第二元件430之銲墊431之特定區塊，而另一端連接至平台區塊414之特定區塊。
此處，圖3中基底410之下陷區412、平台區414與外接區塊416之功能大致相對應於圖1A中導線架120之一空陷區122、半蝕刻區塊124與側壁區塊126。
第一、第二元件420、430及420/412間可透過導電黏著層470及425直接達到兩者之間的電性連結。導電黏著層425、470材質例如是銀膠或其他適當之膠材。第一、第二元件420、430可獨立分別為一功率元件如MOSFET、IGBT或二極體，或是已經部份封裝完成的封裝體。第一元件420與第二元件430可為不同功能或材質之元件。銲線460例如為金線亦可為如銅線或鋁線。第一、第二元件420、430也可利用固液擴散技術(SLID,solid liquid inter-diffusion)等方法達到彼此電性導通。固液擴散技術，即在接觸面之上下各形成金屬層，經過熱機處理後使其相互擴散，而該層金屬層可包含銅、鎳、錫、銀、金、鈦等元素。
填充層440材料例如為紫外線固化性聚合物、熱固性聚合物、環氧基樹脂(epoxy resin)、ABF膜(Ajinomoto Built-up Film)、聚醯亞胺(polyimide)或苯基環丁烯(benzocyclobutene，BCB)等，可採用灌膠方式或壓合方式來形成。視所包封的元件種類不同，填充層所使用的材料可以是具有高散熱效益的介電材料或更包括幫助散熱的添加物。
圖3所示基底410更包括一外接接觸面418，位於基底410之最底層，外接接觸面418與下陷區412間可具有填充材料415及通孔417，可達到導電及散熱之功效。以第一、第二元件420、430均為功率元件為例，電極450作為射極(emitter)與作為閘極(gate)的外接側壁區塊416位於同一端，外接接觸面418作為集極(collector)位於相對的另一端。
圖4A為本發明之另一實施例之一種堆疊式元件模組的剖面示意圖。圖4B為本發明之例示的堆疊式元件模組的上視示意圖。
參考圖4A，依照本發明之另一實施例，半導體封裝模組500其與半導體封裝模組400主要差異處在於：所有線路均以電鍍通孔型態完成，不包含任何打線製程。半導 體封裝模組500包括一基底510、至少一第一元件520、至少一第二元件530、至少一填充層540、多個導電插塞550以及至少一線路圖案560。
參照圖4A，同樣地，基底510與基底410設計相當，具有至少一下陷區512與至少一平台區514。基底510例如是多層印刷電路板或是疊合電路板(Printed Circuit Board,PCB)，可透過壓合金屬板與介電層而製得，更可包括內接線路與金屬導電插塞或貫孔。由於透過導電插塞連結，基底510可省略側壁部份之設計。
參照圖4A，第一元件520設置於基底510之下陷區512上，而第二元件530設置於該第一元件520上並覆蓋部份平台區上表面514。該填充層540覆蓋於基底510之上且包覆第一、第二元件520、530。第一元件520與基底510之間的連結，及520/530間，可以使用導電黏著層515、570連接，導電黏著層515、570的材料例如為錫膏、銀膠等。當然也可利用導電性連接技術，例如固液擴散技術(Solid Liquid Inter-diffusion,SLID)等完成連接。
參照圖4B，第二元件530較佳是與第一元件520部份重疊，而非完全重疊，以暴露出第一、第二元件上的接觸墊521、531，而下陷區512之深度約與第一元件520厚度相當，使疊於第一元件上之第二元件530可平坦地部份設置於平台區514。
線路圖案560包括中央線路圖案562作為射端以及其周邊的閘極接觸端564。中央線路圖案562可透過多個導 電插塞552與第二元件530相連結，而第一、第二元件上的接觸墊521、531則透過導電插塞556、554與閘極接觸端564電性相連結。由於第一、第二元件乃上下堆疊，故導電插塞556之長度(深度)乃高於導電插塞554、552。如此一來，透過導電插塞550與線路圖案560，第一、第二元件520、530之各電極連接到基底上相對應之對外接點。圖4所示基底510更包括一外接接觸面518，位於基底510之最底層。以功率元件為例，線路圖案562作為射極(emitter)與作為閘極的閘極接觸端564位於同一端，外接接觸面518作為集極(collector)位於相對的另一端。
視產品求而定，透過圖案設計可將最外層之部份線路圖案作為散熱結構以強化散熱效率。
第一、第二元件520、530可透過導電黏著層570直接達到兩者之間的電性連結。導電黏著層570材質例如是錫膏、銀膠等。也可利用固液擴散技術(SLID)等方法，完成兩元件之電性連接。第一、第二元件520、530可獨立分別為一功率元件如MOSFET、IGBT或二極體、晶片或是已經部份封裝完成的封裝體。第一元件520與第二元件530可為不同功能或材質之元件。第一元件520或第二元件530可為一半導體晶片例如是電晶體、射頻(Radio-Frequency,RF)晶片或發光二極體(LED)。導電插塞材質550例如為銅或銅合金。
本發明實施例中，為整合複數元件，提供包含空陷與半蝕刻區塊等設計之導線架或具下陷區與平台區之基底， 以達到內埋之效果，進而降低整體封裝體積，並提升電氣傳輸及轉換效率。
本發明實施例中，元件與基底、元件與元件之間的連結，可以使用導電材料(如錫膏、銀膠等)或導電性連接技術(如固液擴散技術SLID等)完成連接。
本發明實施例中，可利用增層介電層之方式達到重佈線路，拉出電極接點之效果。例如搭配雷射開孔技術製作介層窗，雷射開孔完整且無須於接觸墊製作保護層，輔以電鍍製程於介層窗中填入導電插塞(如銅金屬或合金)。在完成電性導通的同時，透過後續熱處理製程，可於導電插塞與接點處形成具有介金屬化合物，而提高長期可靠度。
此模組於大電流模式底下操作時，可能須加裝散熱結構或模組。本發明之設計可將散熱模組套用於其上，並且因介電層或填充型膠體包覆並保護元件的情況底下，導熱效果理應較無介質之打線模組良好。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
12‧‧‧金屬基底
22、410、510‧‧‧基底
20、420、520‧‧‧第一元件
30、430、530‧‧‧第二元件
24‧‧‧金屬區塊圖案
32、34、460‧‧‧銲線
38‧‧‧導電塊
100‧‧‧基底
101‧‧‧黏著層
101a、20a、22a、202a、310a、126a、412a、420a、430a‧‧‧上表面
120‧‧‧導線架
122、222‧‧‧空陷區
124‧‧‧半蝕刻區塊
126‧‧‧側壁區塊
201、203、301、421、431‧‧‧銲墊
204、425、470、515、570‧‧‧導電黏著層
202、310、440、540‧‧‧填充層
206、208、306、308‧‧‧介層窗
214、314‧‧‧金屬導電物質
216、218、316、318、550、552、554、556‧‧‧導電插塞
220、320、560‧‧‧線路圖案
230、330‧‧‧黏膠層
302、521、531‧‧‧接觸墊
400、500‧‧‧半導體封裝模組
412、512‧‧‧下陷區
414、514‧‧‧平台區
415‧‧‧填充材料
416‧‧‧外接側壁區塊
417‧‧‧通孔
418、518‧‧‧外接接觸面
450‧‧‧電極
562‧‧‧中央線路圖案
564‧‧‧閘極接觸端
圖1A至圖1H繪示依照本發明之一實施例之一種堆疊式功率元件模組的製作流程剖面示意圖。
圖2A至圖2H繪示依照本發明之另一實施例之一種 堆疊式元件模組的製作流程剖面示意圖。
圖3為本發明之一實施例之一種堆疊式元件模組的剖面示意圖。
圖4A為本發明之另一實施例之一種堆疊式元件模組的剖面示意圖。
圖4B為本發明之例示的堆疊式元件模組的上視示意圖。
500‧‧‧半導體封裝模組
510‧‧‧基底
512‧‧‧下陷區
514‧‧‧平台區
518‧‧‧外接接觸面
520‧‧‧第一元件
521、531‧‧‧接觸墊
530‧‧‧第二元件
515、570‧‧‧導電黏著層
540‧‧‧填充層
550、552、554、556‧‧‧導電插塞
560‧‧‧線路圖案
562‧‧‧中央線路圖案
564‧‧‧閘極接觸端

Claims (10)

  1. 一種堆疊式功率元件模組，至少包括：一基底，具有一第一表面與一第二表面；至少一第一元件，位於該基底之該第一表面上並與該基底電性連結；至少一第二元件，位於該至少一第一元件上並與該基底電性連結；至少一填充層，覆蓋於該基底之該第一表面上且包覆該至少一第一元件與該至少一第二元件，該至少一填充層包括多個第一插塞與至少一第二插塞；以及一線路圖案，位於該至少一第二元件之上且位於該至少一填充層上，該線路圖案透過該些第一插塞連接該至少一第二元件，該線路圖案透過該至少一第二插塞連接該至少一第一元件，其中該至少一第二插塞之高度大於每一該至少一第一插塞之高度。
  2. 如申請專利範圍第1項所述堆疊式功率元件模組，更包括至少一電極位於該至少一第二元件上，且該至少一電極表面露出於該至少一填充層。
  3. 如申請專利範圍第2項所述堆疊式功率元件模組，其中該至少一第一元件與該至少一第二元件透過多個銲線分別電性連接至該基底。
  4. 如申請專利範圍第1項所述堆疊式功率元件模組，其中該基底更包含至少一下陷區與一平台區，該至少一第一元件設置於該至少一下陷區，其中該至少一下陷區之深 度約相等於該至少一第一元件之厚度，該至少一第二元件設置於該平台區與該至少一第二元件之上；其中該至少一第一元件與該至少一第二元件之間更設置一導電黏著層，該至少一第一元件與該至少一第二元件透過該導電黏著層電性連接。
  5. 如申請專利範圍第1項所述堆疊式功率元件模組，更包括一重佈線路圖案設置於該至少一第一元件與該至少一第二元件之間。
  6. 如申請專利範圍第1項所述堆疊式功率元件模組，其中該基底是一金屬導線架(Lead Frame)。
  7. 如申請專利範圍第1項所述堆疊式功率元件模組，其中該基底是一疊合線路板(Printed Circuit Board,PCB)，更包括一外接接觸面位於該基底的該第二表面。
  8. 如申請專利範圍第1項所述堆疊式功率元件模組，其中該至少一第一元件或該至少一第二元件分別為功率元件、晶片或是已經部份封裝完成的封裝體。
  9. 如申請專利範圍第1項所述堆疊式功率元件模組，其中該填充層材料包括紫外線固化性聚合物、熱固性聚合物、環氧基樹脂(epoxy resin)、聚醯亞胺(polyimide)或苯基環丁烯(benzocyclobutene，BCB)。
  10. 如申請專利範圍第4項所述堆疊式功率元件模組，其中該導電黏著層的材質包括導電性黏膠、銀膠或錫膏或電鍍金屬造成擴散形成穩定之化合物。
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