TW201140720A - Silicon nitride passivation layer for covering high aspect ratio features - Google Patents

Silicon nitride passivation layer for covering high aspect ratio features Download PDF

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Publication number
TW201140720A
TW201140720A TW100108357A TW100108357A TW201140720A TW 201140720 A TW201140720 A TW 201140720A TW 100108357 A TW100108357 A TW 100108357A TW 100108357 A TW100108357 A TW 100108357A TW 201140720 A TW201140720 A TW 201140720A
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Taiwan
Prior art keywords
gas
layer
nitrogen
substrate
processing
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TW100108357A
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English (en)
Inventor
Nagarajan Rajagopalan
xin-hai Han
Ryan Yamase
Ji-Ae Park
Shamik Patel
Thomas Nowak
David Zheng-Jiang Cui
Mehul Naik
Heung-Lak Park
Ran Ding
Bok Hoen Kim
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Applied Materials Inc
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Publication of TW201140720A publication Critical patent/TW201140720A/zh

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    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C23C16/345—Silicon nitride
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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    • H01L2924/351—Thermal stress

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201140720 ^、發明說明： 【發明所屬之技術領域】 本發明之實施例係關於在高深寬比特徵結構上形成包 括氮切之鈍化層，高深寬比特徵結構係用於在 上 製造電子電路。 土 【先前技術】 雷二:電路(諸如’積體、顯示、記憶體、功率與光致電 電路）變得更密集且更加複雜。這些電路之特徵結構的尺 寸係變得更小好允許更大的磁錄密度橫跨基板。這些特 :結，包括連接器凸塊、互連、半導體或氧化物特徵結 問極、電極、電阻、互連孔與其他。當特徵結構之 ▲度或水平尺寸變得更小時’上述特徵結構之深寬比提 局’這係因為特徵結構之垂直尺寸必須更大以提供相同 的松剖面積。在藉由鈍化層覆蓋特徵結構以保護或電絕 緣特徵結構時’深寬比（特徵結構之高度與寬度的比例） 為具體的問題。 作為實例’如第1A圖與第1B圖所示，鈍化層料 :於覆蓋特徵結構12’以在用其他材料塗覆特徵結構之 刖或之間避免特徵結構12之含_面的氧化。特徵社 構12包括互連13 (第1A圖）與連接器凸塊14 (第1B 圖）°互連13係用於連接基板15上之主動與被動元件。 牛例而言’連接器凸塊14係用於覆晶封裝中以作為積體 201140720 電路晶片與外部環境之間的互連點。連接器凸塊14係形 成於接σ墊上以允，晶粒「翻轉」電路顛倒並直接焊接 至連接器或電路，藉此節省傳統銲線與箔連接器的時間 /、成本互連13與連接器凸塊14兩者係由鈍化層1〇所 覆蓋。 然而隨著互連丨3或連接器凸塊14之深寬比提高至 冋於0.2之數值，逐漸變得難以沉積連續、保形與實質 j不具缺陷的鈍化層10圍繞特徵結構12，特別係特徵 、，口構之倒角（re_entrant c〇rner)17。參照帛ia冑，純化層 10形成缺陷11(例如’接縫16)，其在互連13之角處 分裂打開鈍化層1G。連接器凸塊14上之鈍化層1〇亦可 在連接器凸塊14之基部周圍的角17處形成接縫16。 在晶片封裝、重新分配層（RDL)、或矽穿孔（tsv)銅 或鶴互連孔中’接縫問題時常由倒角.17之幾何元素加以 〜、化舉例而吕，如第1 C圖所示之高深寬比特徵結構 例如矽互連孔18 ’其包括形成通過介電層19之孔， 由導電材料所填充以在下方特徵結構（例如，互連⑺與 上方特徵結構（例如’凸塊14)之間形成連接。當以聽 層1〇塗覆矽互連孔18與上方之連接器凸塊14時，形成 於純化層1G與連接器凸塊Μ切互連孔18之交接處的 倒角17時常出現接縫16。高深寬比特徵結構12之又另 一實例包括鈍化層1G覆蓋之氧化物結構（未顯示氧化 物結構可包括含二氧切結構，諸如形成於碎穿孔中之 氧化物襯墊層、或形成於石夕穿孔之銅支柱頂部上的氧化 201140720 物層，其允許在基板之背側揭示互連孔連接。再者，形 成於鈍化層10中之缺陷11覆蓋上述特徵結構12。 在特徵結構12具有複雜幾何結構之區域（特別係具有 尖銳邊緣與角度之倒角17)處鈍化層1〇中之缺陷n亦可 為其他類型，諸如微裂紋、髮絲裂縫等等。然而，並不 明白如何形成具有這些深寬比之特徵結構12且維持這 些特徵結構之幾何結構與其他尺寸，同時避免缺陷出現 於上述純化層10中。 因此，儘管發展出多種圍繞特徵結構沉積鈍化層之方 法，但由於包括這些與其他缺失之多種原因，仍持續需 要進一步改善鈍化層之沉積。 【發明内容】 、在基板之特徵結構上形成包括氮化矽層之鈍化層的方 法包括在處理區中提供具有複數個特徵結構之基板。在 第ϋ中’將包括含矽氣體與含氤氣體之介電沉積氣 體導入處理區’並經充能以沉積氮化矽層於特徵結構 亡。在第二階段巾’將成份不同於介電沉積氣體之處理 ^體導入處理區，並經充能以處理氮切層。可複數個 次執行第一階段與第二階段。 方法可包括初步清潔階段，其包括提供包括含氫氣體 之清潔氣體進入處理區並充能清潔氣體以形成包括含氣 物種之經充能清潔氣體，其清除基板之特徵結構上的原 201140720 生氧化物薄膜。 又另一形式中’初步浸泡階段包括提供包括矽烷之浸 泡氣體進入處理區，並維持基板於約1 00至約240。(：之 溫度下以沉積附著層於基板之特徵結構上。 又另一形式中’方法包括在特徵結構上沉積共形概 裡，共形襯裡的厚度大於約1 〇 〇埃且拉伸應力係至少約 lOOMPa。可藉由下述沉積共形襯裡：（1)將襯裡氣體導入 處理區’襯裡氣體包括（i)SiH4、NH3與N2 ; (ii)三石夕烧胺 (trisilyamine)、NH3 與 N2 ; (iii)SiH4 或 N2 ;或（W)三矽烷 胺或N2化學物；及（2)充能襯裡氣體以形成電漿。 【實施方式】 如第2A圖至第2C圖所示，可利用沉積與處理製程將 鈍化層20沉積於基板22上以形成連續、共形與實質上 不具缺陷之塗層於基板22之特徵結構24上。舉例而言， 基板22可為半導體晶圓、化合物半導體或介電質。半導 體晶圓包括單一或少數大晶體的矽、鍺或矽鍺。示範性 化合物半導體包括砷化鎵。適當介電質包括玻璃面板或 顯示器且可包括硼磷矽玻璃、磷矽玻璃、硼矽玻螭、與 磷矽玻璃等材料。 純化層20可為單層（如第2A圖所示）或複數個層 20a-d(如第2B圖所示）。舉例而言，鈍化層2〇可為單一 介電層25、或者各自包括介電層25a、b之複數個層2〇a、 201140720 :。提供純化層20以藉由降低這些材料與外部 應速率來鈍化特徵結構24之下方材料之 兄之反 而言，包括含金屬材料、戋甚 * 面。舉例 特徵結構上沉積之純化A 金屬材料所構成之 表面上形成原生氧化物薄膜。舉例而言，介電層可= :矽(Sl3N4)、二氧化矽⑻⑹或其他上述材料 a ’介電層沉積厚度係小於1GGG埃或甚至5⑽埃。 ^鈍化層20亦可包括其他層2〇c，例如附著層 係：積於介電層25下以附著介電層25至特徵結構24: 奉露表面28。附著層27可由與介電層“相同材料、介 電材料之變化或不同材料所構成。舉例而言，當介電層 乃包括氮化矽層時，附著層27可為富含矽之氮化矽層。 .鈍化層20可進—步包括另一部件層2〇d’例如共形概 裡29，其係形成於介電層25下。共形襯裡29可沉積於 附著層27上。共形襯裡29用以促進附著與階梯覆蓋。 適當的共形襯裡29包括以SiHd TSA作為矽前驅物製 成之Si3N4薄膜。 利用其他習知處理將整個鈍化層20沉積於已經形成 於基板22上之特徵結構24上。特徵結構24可具有自基 板22之平坦面向外延伸之不同形狀與橫剖面輪廓。舉例 而言’特徵結構24可包括互連13、連接器凸塊14、石夕 互連孔18、氧化物結構或這些或其他形狀與結構之組 合’某些實施例係提供於第2A圖至第2C圖。鈍化層2〇 提供下方特徵結構24的共形覆蓋，即便下方特徵結構 201140720 24為高度比寬度之比例大於〇 2、或甚至大於5、或甚至 大於10之问冰寬比特徵結構％。舉例而言，可沉積鈍 化層20以覆蓋包括含金屬材料之特徵結構24，諸如第 2A圖之互連13、第2B圖之連接器凸塊14、或第2。圖 之連接器凸塊14與介電層19中之互連孔18。此應用中， 鈍化層20避免或降低這些特徵結構24之含金屬表面的 氧化。 現將參照示範性處理與示範性處理腔室以處理基板Μ 來描述鈍化層20之製造。具有選擇性步驟之示範性處理 係顯不於第3圖之流程圖中。可藉由將基板22置於處理 腔室4〇之處理區42中來執行本文所述之任何處理，而 適虽腔室的不形式係顯示於第4圖中。雖然處理與處 理腔至40之不範形式係描述於第3圖與第4圓中，但應 當理解可應用其他處理，且熟悉技術人士亦清楚這些處 巧執行:其他處理腔室中。因此，本文所述之處理與 腔室之示範形式不應用來限制本發明之中請專利範圍。 、選擇陡地如第3圖之流程圖所示，在沉積純化層μ :基板22之月”可樂於執行初步清潔階段以清潔特徵結 :24之暴露表面(特別係那些包括含金屬材料之表面)。 二特徵構24係由金屬或含金屬材料所構成時（例如， 互連13或連接器凸塊14)，特徵結構Μ之暴露表面變 :受氣化以形成原生氧化物薄膜。清潔處理移除形成於 • '口才冓24之表面上的原生氧化物薄膜或其他處理沉 積物’以避免暴露於含氧環境中。清潔處理可清潔包括 201140720 含金屬材料（諸如，鋁、銅、 甘 十甘、 鎢或其之合金與化合物 或其他材料）之特徵結構24的表面。 清潔處理之一形式令，包灰 ^ . 3氫氣體之清潔氣體係用 來移除形成於特徵結構24之 <辰面上的原生氧化物。清潔 處理暴露基板22至包括含盡帝胳& 虱電漿物種之經充能清潔氣 其係藉由輕接能量至適當含氫氣體（諸如，H2、或 N2 與 NH3、或 h2〇、或 SiH )而 ^ ^ ' ，叩加以形成0含虱氣體之適 當體積流率係約1〇〇 sccm至 i q 18升/分鐘。咸信含氫電 渡物種與形成於特徵結構24上之原生氧化物薄膜的氧 成分化學反應’以形成可排出之揮發經物種或水蒸汽， 藉此自特徵結構24之表面移除原生氧化物薄膜。因此， 經充能之含氫游離基團與特徵結構24上之原生氧化物 4膜專-性父互作用並*會非所欲地傷害周圍層之结 構。 ’ 示範性清潔氣體組成包括（或實質上由H2組成）體積流 率W0G至約3_咖（例如，約则s叫之&。另 實例中’仴潔氣體包括體積流率約5〇至約3〇〇 (例如’約160 sccm)之冊3與體積流率約ι〇〇〇升/分鐘 至30,000升/分鐘（例如，约18，_升/分鐘）之义的混合 物又另f例中，清潔氣體包括體積流率約則至約 3000 sccm (例如，約刪_)之H2與體積流率約5〇 至約300 seem (例如，的1 „ 、 V列如約160 seem)之ΝΗ;的混合物。這 些實例中’基板22係置於處理區42中，且將清潔氣體 組合物導入腔室40並維持在約15至約8〇托耳（或甚至 201140720 9.0托耳）之壓力下。接著在約50至約700瓦特（例如， 〇瓦特）之功率水平下將RF能量輕接至處理區42附近 之處理電極44a、b以自清潔氣體形成電锻。處理電極 44可維持在約50毫米（2〇〇密爾）至約15〇毫米（6〇〇密爾） 之間距下。將基板10之溫度維持在約^至約， 例如400〇 C。 在清潔處理之後，可執行選擇性初步浸泡階段以沉積 附著層27於特徵結構24上。沉積時，&附著層形成最 終鈍化層20的一部分。此處理之一形式巾，基板22上 ^特徵結構24係暴露於包括矽烷之浸泡氣體以沉積附 著層（例如，富含矽之氮化矽薄層）。富含矽之氮化矽薄 層的厚度係約1 〇埃至約1 〇〇埃。 示範性浸泡處理中，將基板22傳送至處理區42並維 持在約100〇C至約24〇π(例如，約18〇。〇之溫度下。接 著將包括矽烷、氨與氮之浸泡氣體導入處理區42，並讓 基板22浸泡於溫度下之富含矽氣體中。浸泡氣體之適當 組成包括：體積流率約200至約8〇〇sccm (例如，約5〇〇 seem (例如，約45 0 seem)之矽烷；流率約200至約8〇〇 seem)之氨；及流率約4000至約i2,〇〇〇 sccm (例如’約 8000 SCCm)之氮。將浸泡氣體維持在約1至約5托耳（例 如’2.2托耳）之壓力下。可執行浸泡處理達約5至3〇 秒（例如，約10秒）。浸泡處理過程中，並不施加RF能 量至電極44a、b ;反之，讓基板22浸泡於溫度下之浸 泡氣體中以形成富含矽之氮化矽薄層。特徵結構24包括 201140720 由銅構成之連接器凸塊14時，浸泡處理特別適用。 選擇性襯裡處理中，將共形襯裡29直接沉積於特徵結 構24上或沉積於浸泡處理中形成之附著層上。共形襯裡 29亦形成鈍化層2〇之一部分並讓上方層以較大的共形 性沉積特徵結構24之輪廓。一形式中，共形襯裡“的 内U卩拉伸應力係至少約1〇〇MPa，由薄膜厚度與應力測量 /、斤里須]其利用光譜糖圓偏振或單一波長橢圓偏 振，例如 KLA-Tencor FX-100(KLA-Tencor，San J〇se，
CaHf〇rnia)。咸信共形襯裡29藉由降低特徵結構24之暴 露表面與上方之鈍化層20間之介面處的應力梯度來減 少缺陷1卜由小於0.14之低黏滯係數的電漿物種⑽如， 三胺矽烷）形成共形襯裡29。低黏滯係數物種降低特徵結 構24之暴露表面處的表面能量，讓共形觀裡μ覆蓋特 徵結構24之底角30處的倒角式輪廓，因此避免這些底 角30處的高應力集中而造成接縫。一形式中，共形襯裡 29係厚度例如小於約1〇〇埃之薄層。可藉由將包括含矽 氣體與含氮氣體之襯裡氣體導人處理區42並以任一上 述處理條件（諸如’流率、壓力、電聚功率等）以電聚充 能襯裡氣體來沉積共形襯裡29。襯裡氣體之適當組成包 括含石夕氣體（包括石夕院）與含氮氣體（包括氨與氮之混合 物）。另一形式中，襯栢齑舻,, 视裡亂體之另—組成包括含石夕氣體（包 括二梦烧胺（TSA))盘合氣洛鹏/七t # 3氮就體（包括氮或氨與氮之混合 物卜又另—形式中’觀裡氣體僅包括含石夕氣體（諸如， ㈣或三㈣胺）’或僅包括含氮氣體（例如，氮）。各個 12 201140720 貫例中’藉由施加至平杆革纪 〇〇, — 千板反應态（例如，PECVD胪 至）之RF功率形成之電聚充能槪裡氣體。 在選擇性清潔與襯裡處理後，將純化層Μ之介電層 共形地沉餘特徵結構。沉㈣料允許在特 徵結構24(例如，高深寬比特徵結構26)之底肖3〇處沉 積均勻且連續並實質缺少缺陷11的介電層25。 形式中’將包括敗化石夕層之純化層2〇 ;冗積於基板 22上。此處理中’將基板22置於腔室之處理區42 中並在沉積處理過程中加熱至相#低溫度。低沉積溫度 係重要的用來沉積與特徵結構24(特別係高深寬比特徵 結構26)之形狀共形的鈍化層2〇。共形意謂著鈍化層2〇 依循下方特徵結構24之輪磨且在特徵結構24之整個暴 露表面與特徵結構24間之間隔32上具有相當均勾的厚 度 形式中，介電沉積處理過程中，將基板22加熱至 約180oC至約550。〇或甚至160〇c至約42〇〇c之溫度。 這些溫度遠低於先前技術之溫度（通常超過6〇〇〇c或甚至 700〇〇。 在第一沉積階段中，將包括含矽氣體與含氮氣體之介 電沉積氣體導入處理區42。含矽氣體係包括矽之氣體， 其可為在氣體或水蒸汽流動中提供之含石夕化合物。含石夕 氣體可為矽烷、二矽烷、三甲基矽（TMS)，三（二曱基胺） 矽烷（TDMAS)、（雙（叔丁基氨基）矽烷（BTBAS)、二氯矽 燒（DCS)或其之混合物。一形式中，含矽氣體包括矽烷 (S1H4)。適當的矽烷流率係約5〇至約2000 seem、或約 13 201140720 400至約lOOOsccm。含氮氣體可為氨（NH3)、氮（N2)或其 之混合物。一形式中，含氮氣體包括氨與氮之混合物。 氨的適當流率係約100至約1000 sccm、或甚至約4〇〇 至約800 seem。氮氣不僅作為氮原子之來源且亦作為稀 釋氣體以控制處理區42中形成之電漿的能量與性質。相 對於含矽氣體或含氮氣體而言，以相當大的體積添加稀 釋氣體。稀釋氣體用以控制電漿中經充能物種比反應物 種之比例，並亦可藉由透過大量稀釋氣體分子（相對於反 應氣體分子數量）間之較大數量的碰撞而傳送能量以用 於分解電漿中之額外物種。一實例中，稀釋氣體可為氮。 氮可作為氮化石夕沉積中含氮氣體物種的來源與經充能分 子的來源以產生並維持電漿。氮的適當流率係約至 約25，_ secm (例如，約8_至約12，_似⑷。 -實施例中’介電沉積氣體包括矽烷、氨與氮之混合 有利的疋上述介電沉積氣體之組成在沉積層中提 供較高的氮比珍之比例，這造成約18至約或甚至約 U8至約K98的較高折射率。較佳形式中，介電沉積氣 體包括我、氨與氮之混合物’ SUN:之體積比例 ，約！十8至肖2:1:20。這些比例中，發現介電沉積氣體 k供較共形的覆蓋係因為電漿中較高的胺物種造成較低 的黏滞係數。在處理區42或遠端區域（未顯示）中充能介 電沉積氣體以活化處理氣體物種以沉積材料於基板22 上。-形式中’藉由耦接RF能量至處理區仏附近之處 理電極44、b以充能介電沉積氣體而在處理區42中形成 14 201140720 電漿。為了產生電漿’電極功率水平通常維持在約5〇〇 至約1600瓦特、或甚至約8〇〇至約15〇〇瓦特下。適當 的電極間距係約5毫米（200密爾）至約2〇毫米（8〇〇 ^ 爾）。 本發明沉積處理藉由控制導入處理區42中之介電沉 積氣體的壓力而在比傳統處理低至少約丨〇〇。c的溫度下 沉積。樂見低壓的沉積氣體以提高沉積之鈍化層2〇中特 定物種的濃度，例如提高包括氮化矽之鈍化層2〇中之氮 濃度。再者，在低沉積壓力下提高離子撞擊分量產生較 密集的鈍化層20。介電沉積氣體的適當壓力係約15托 耳至約6托耳、或甚至約2至約4托耳。 介電沉積階段之一實例中，將由氮化矽構成之介電層 25沉積於特徵結構24(例如，覆晶基板上之連接器凸塊） 上。連接器凸塊係深寬比約〇·2至約1〇之高深寬比特徵 結構26。沉積處理中，將基板22維持在18〇qc之溫度 下。將包括流率820 sccm之矽烷 '流率59〇 sccm之氨 與之流率ίο升/分鐘氮的介電沉積氣體導入處理區42。 將介電沉積氣體維持在3.5托耳之壓力下。在1〇〇〇功率 水平下施加RF功率至間隔維持在u毫米（45〇密爾）之 處理電極44a、b。 介電沉積階段之另一實例中，將包括氮化矽之介電層 25沉積在特徵結構24(其係連接器凸塊）上。沉積處理 中，將基板22維持在400°C之溫度下，並將介電沉積氣 體維持在4·2托耳之壓力下。其餘條件相同於實施例i ^ 15 201140720 包括氮化矽之沉積鈍化層20的厚度可小於ι〇〇〇埃或 甚^ 500埃。有利的是’薄石夕層提供下方特徵結構Μ(包 括尚深寬比特徵結構26)較高的共形覆蓋。 在沉積氮切之介電層25後，進—步在電I處理階段 中處理沉積之鈍化層20。此處理階段中，將處理氣體導 入處理區42 ^處理氣體可為非反應性氣體，例如惰性氣 體。適當的惰性氣體包括氦或氬。上述或其他惰性氣體 的適當流率係約2,000 seem至約2M⑽似爪。舉例而 言’適當的非反應性氣體包括含氮氣體，諸如氨、氮或 其之混合物。-形式令’非反應性氣體包括氨或氮或其 之混合物。非反應性氣體的適當流率係約2,〇〇〇 s⑽至 約20’_ seem。舉例而言，將流率約5，嶋3峨至約 ，Sccm且包括氨與氮之處理氣體導入腔室4〇並維 持在5托耳之壓力下。藉由麵接能量於處理腔室中 之處理電極44a、b之間而充能預先選擇之處理氣體以形 成電漿來處理沉積之氮化矽層。可藉由耦接功率水平約 75至約I，600瓦特之RF能量至電極來充能處理電極 44a' b。咸信處理製程中’氫原子被逐出沉積之鈍化層 20。因為濕氣之故，沉積層2〇中氫的存在係不樂見的。 因此’藉由處理沉積之鈍化層2G來移除氫且處理氣體包 括用以密化薄膜之含氮氣體。 執行多個«的沉積與處理製程以增強沉積之純化廣 對缺陷形成的抗性’特別係當介電層25沉積於高深 寬比特徵結構26上^多循環處理中，纟自執行複數次 16 201140720 的沉積與處理階段。多循環處理增強沉積之鈍化層2〇抵 抗在高深寬比特徵結構26之底角30處形成缺陷（例如， 接縫）之能力。多循環處理中，停止或改變進入處理區 之介電沉積氣體，並藉由改變介電沉積氣體之組合而開 始或發動處理氣體之流動以達成處理氣體之組成。舉例 而言’處理氣體可包括含氮氣體（諸如，上述之氨與氮戋 其之混合物）且缺少含矽氣體。藉由簡單地停止介電沉積 氣體之含矽氣體的流動同時持續含氮氣體之流動以轉換 介電 >儿積氣體至處理氣體、停止矽烷之流動同時持續氨 與氮之流動並充能氨與氮以形成電漿來執行處理階段。 此形式有利地用來密化薄膜。 亦發現沉積之鈍化層20的折射率（n)(例如，氮化矽層 的折射率）影響沉積層中底角3〇與特徵結構之其他幾何 過渡區處的缺陷U水平，特別係高深寬比特徵結構26。 咸信折射率係沉積之鈍化層2〇中氮含量的反向測量。富 :氣的鈍化層20提供較低的Si_H含量，這接著提供： 定的/專膜it步確定包括氮化石夕之所欲鈍化層的折 射率係高於丨.88、或甚至K92。—實財，制633加 波長下的橢圓偏振測量折射率，先前所述之 Κ"Α_Τ_〇Γ薄膜測量設備。因…形式中，處理條件 亦可經設定以沉積折射率⑻低力1>88之氮化㈣，這係 利用橢圓偏振在633 nm波長下測量。 折射率控制處理之第 折射率的適當處理條件 一實例中’取得低於 如下··（1)基板溫度係 1 · 8 8之所欲 180°C > (2) 17 201140720 氣體組成包括流率820 seem之石夕烧、流率590 seem之 氨與流率8000 seem之氮’（3)腔室氣體壓力係2.2托耳， 及（4)電極功率水平係1080瓦特且電極間距係640密爾 (1 6.3毫米）。第二實例中’所有的處理條件係相同於第 一貫例，除了將妙烧之流率維持在820 seem並將氨之流 率維持在590 seem。 亦發現相對於蝕刻熱氧化物之氮化矽之沉積鈍化層2 〇 之濕蝕刻速率比值WERR影響沉積層中之缺陷丨丨水平。 熱氧化物係藉由熱處理沉積之二氧化梦，例如在8 〇 〇。C 至1200°C之高溫下生成於垂直或水平擴散熔爐或快速 熱處理器中。測定之WERR係0.3至約5 2。此影響特徵 結構（特別係高深寬比特徵結構26)之底角3〇與其他幾何 過渡區處#完整性。因此，沉積處理條件係經設定以沉 積相對熱氧化物蝕刻鈍化層2〇之濕蝕刻速率比值werr 小於5.2的氮化石夕層。 又另一方法中，藉由沉積在層之整個厚度具有 —，，乂1¾ 乃 Λ 度的純化層20來降低沉積於特徵結構24(例如，高深 比特徵結構26)上之純化層2G中的缺陷n數目。舉例 言，可藉由在沉積處理過程中控制一或多個氣體之流 來沉積包括具有應力梯度之氮切的純化層2〇。此形 中。儿積之鈍化層2G包括層中♦比氮之比例逐漸變化 階梯變化的氮化石夕。純化層2〇在層2〇之整個厚度中 :至少一第一與第二的矽比氮的比例。這係藉由在沉; 處理過程中改變介電沉積氣體之組成以具有自高流率」 201140720 低流率的第一氣體改變來完成《舉例而言，可利用包括 含矽氣體成分（包括矽烧（SiH4))、氮氣成分（包括氨（NH3)) 與稀釋氣體成分（包括氮（N2))之處理氣體沉積氮化矽。首 先’應用包括含矽成分比含氮成分之第一比例的介電沉 積氣體，並在處理區中產生處理氣體之電漿。接著，應 用包括含矽成分比含氮成分之第二比例的處理氣體，並 在處理區中產生處理氣體之電漿。含矽成分比含氮成分 之第一比例係小於約1〇〇:1，而含矽成分比含氮成分之第 二比例係至少約1。舉例而言，可在沉積處理過程中改 變矽烷比氨的比例於約1:1至約6:1之間。 另一开> 式中，可藉由控制施加至基板22附近之一對處 理電極44a、b的RF功率來沉積包括具有應力梯度之氮 化矽的鈍化層20 *此處理中，將處理氣體導入處理區 42，處理氣體包括本文所述之含矽成分與含氮成分。藉 由施加第一功率水平之能量至處理區42附近之電極= 在處理H42中產生處㊣氣體之電之後，#由改變施 加至電極44a、b之能量置第二功率水平來沉積具有矽比 氮之第二比例的氮化矽。一形式中，第一功率水平比第 二功率水平至少高出約1〇〇瓦特。舉例而言第一功率 水平可包括低於約200瓦特，而第二功率水平包括至少 約5〇0瓦特。此處理中’沉積於基板22上之氮化矽中的 矽比氮之比例影響沉積層之應力。 另一形式中’包括氮切之鈍化層2G包括複數個分離 的氮化碎子層’其各自具有不同的應力水平以提供具有 19 201140720 逐漸或階梯式增加各個層之應力的層。舉例而言，鈍化 層20之應力可由第一應力增加至第二應力（至少低於第 一應力100 MPa)。第一應力可為約600至約1〇〇〇 MPa， 而第二應力可為約500至約900 MPa。一形式中，第一 應力係800 MPa而第二應力係7〇〇 MPa。處理區42中之 氣體壓力的變化改變處理區42中形成之電漿的密度。較 岔集的電漿在某一侷限空間體積中具有較大數目的氣體 離子與物種。較密集的電漿沉積之鈍化層20比較不密集 的電漿所沉積之鈍化層20密集。較密集的鈍化層2〇具 有較尚的應力水平，並因此造成之鈍化層2〇包括具有不 同密度之不同層的多層結構。 上述形式t，包括氮化矽層之沉積鈍化層2〇的組成梯 度中，矽比氮之比例在層之整個厚度中變化。舉例而言， 鈍化層20的組成梯度中，矽比氮之比例在整個厚度中變 化至少約40%。氮化矽層的組成梯度亦可為矽比氮之比 例在整個厚度中變化由約〇 4至約1 5。 又進-步形式中，鈍化層2〇係藉由接續沉積與餘刻掉 沉積之氮化矽層而沉積之層。舉例而言，此處理可蝕刻 掉-部分的沉積層以改變特徵結構24之底角30處的倒 角式輪靡。此形式中，#由將基板22置入處理腔室40 之處理區42中並執行沉積與同時之蝕刻處理，並在沉積 ，化層20達某—厚度後導人經充能之㈣氣體（例如， ㈣電漿中之氟基化學物），以便可部分㈣銅凸塊之側 與底部以改變底角之倒角式輪廓。可執行多個循環的 20 201140720 沉積與敍刻處理以改變底角之倒角式輪廓成圓滑輪廟， 因此可沉積不具缺陷之鈍化層20。 可用於執行上述處理之基板處理腔室4 〇的實施例係 描述於第4圖中。提供腔室4〇以描述示範性腔室；然而， 熟悉技術人士清楚亦可應用其他腔室。因此，本發明之 範圍不應限制於本文所述之示範性腔室。一般而士，處 理腔室40係適合處理基板22 (例如，矽晶圓）之電聚_輔 助化學氣相沉積（PE-CVD)腔室，適當腔室係Appiied Materialspanta Clara，Calif0rnia)i Pr〇ducer@ SE 型腔 至。腔至40包括封圍處理區42之封圍壁48，其包括頂 部52、側壁54與底壁56。腔室4〇亦可包括襯裡%未顯 示），其内襯處理區42周圍之封圍壁48的至少一部分。 為了處理300毫米矽晶圓，腔室4〇體積通常為約2〇,〇〇〇 至約3〇,〇〇〇立方公分，且更通常為約24，咖立方公分。 處理循環過程巾，降低基板支撐件58並藉由基板傳送 器64(例如，機械臂）傳送基板22通過入口埠62且置於 基板支撐件58上。基板支樓件58可移動於負載與㈣ 之較低位置以及處理基板22之可調整的上方位置之 間。基板支撐件58可包括封閉之電極…以自導入腔室 處理氣體產生„。可藉由加熱器68加熱基板支 撐件58,加熱器68可為電阻式加熱元件（如圖所示）、加 熱燈（未顯示）、或電衆本身。基板支樓件58通常包括陶 瓷結構’纟具有接收表面以接收基板22並保護電極… 與加熱器68免於腔室環境。使用中，將射頻(rf)電壓施 21 201140720 加至電極44a並將直流電（DC)電壓施加至加熱器68。基 板支樓件58中之電極44a亦可用來靜電夾持基板22至 支撐件58。基板支撐件58亦可包括一或多個環（未顯 示）’其至少部分地環繞基板支撐件58上之基板22的周 邊。 在將基板22負載於基板支撐件58上後，提高支撐件 58至較接近氣體分配器72之處理位置，以於其間提供 所欲之間隔間隙距離ds。間隔距離可為約2毫米約12毫 米。氣體分配器72係位於處理區42上以均勻地分散處 理氣體橫跨基板22。氣體分配器72可分別地輸送形成 本文所述之任何處理氣體的兩個獨立流的第一氣體與第 二氣體或氣體混合物（或分別流中之沉積氣體與處理氣 體）至處理區42’而無須在將其導入處理區42之前混合 氣體流。或者’氣體分配器可在提供預先混合之處理氣 體至處理區42之前預先混合處理氣體。氣體分配器72 包括面板74’面板74具有孔76好讓處理氣體通過其中。 面板74通常係由金屬所製成，以對其應用電壓或電位而 藉此作為腔室40中之電極44a。適當面板74可由具有 陽極化塗層之鋁所製成。 基板處理腔室40亦包括第一與第二氣體供應器80a、 b以輸送處理氣體至氣體分配器72，氣體供應器80a、b 各自包括氣體源82a、b、一或多個氣體管道84a、b與一 或多個氣體閥86a、b。一形式中，第一氣體供應器80a 包括第一氣體管道84a與第一氣體閥86a ’以自氣體源 22 201140720 82a輸送介電沉積氣體至氣體分配器72之第—入口 78a而第一氣體供應器8〇b包括第二氣體管道8外與第 二氣體閥86b，以自第二氣體源82b輸送處理氣體至氣 體分配器72之第二入口 78b。 可藉由耦接電磁能（例如，高頻率電壓能量）至處理氣 體而充能處理氣體以自處理氣體形成電漿。為了充萨介 電沉積氣體’電壓施加於⑴第一電極44a，立 八j马氣體 分配器72、頂部52或腔室側壁54與（ii)支撐件58中之 電極44b之間。橫跨成對電極44a、b施加之電壓將能量 耦接至處理區42中之處理氣體。—般而言，施加至 44a、b之電壓係震盪於射頻下之交流電壓。一般而言， 射頻覆蓋約3kHz至約300 GHz之範園。盔7 +也 祀固為了本應用之 用途’低射頻係小於約1 MHz，且争佔或从， 且旯隹為約1〇〇 KHz至 1 MHz (例如，約300 KHz)。再者，盔7丄士 > , ;丹香為了本應用之用途， 高射頻係約3MHz至約60MHz，且f祛i0 又住马約13 · 5 6 MHz。 在約1 0 W至約1 000 W之功率走巫丁收押 刀半水千下將選擇之射頻電壓 施加至第一電極44a，而第二雷炻 叫乐一電極44b通常係接地的。 然而，取決於欲沉積之材料類型， 了應用特定射頻範圍 與施加電壓的功率水平。 腔室4〇亦包括氣體排出裝置％以自腔室40移除用過 的處理氣體與副產物並維持處理區42中之處理氣體的 預定壓力。一形式中’氣體排出裝置％包括抽吸通道 92,其自處理區42接收用過的處理氣體；排出埠94; 節流閥96 ;及一或多個排出爷 徘出泵98，以控制腔室40中之 23 201140720 :理氣體壓力。排出泵98可包括_或多個渦輪分子泵、 低溫系、粗略系、與具有超過一個功能之 腔室 7此心，，且。式功能泵。 (未,g 可包括通過腔室40之底壁56的入口埠或管 入口-不k輸送淨化氣體進人腔t 4G。淨化氣體通常由 ^向上流動通過基板支樓件58並到達抽吸通道。淨 t氣體係用來j早古蔓其^ 4基板支料58之表面與其他腔室部 處理過程中免於不欲之沉積。淨化 所欲方式影響處理氣體之流動。 、,、° ，以 ^提料制ϋ 1G2以控㈣室4Q之運作與運作參數。 列而吕’控制器102可包括處理器與記憶體。處理器 订腔室控制軟體，例如儲存於記憶體中之電腦程式。 a己憶體可為硬碟驅動機、唯獨記憶體、快閃記憶體或其 2類型的記憶體l 1G2亦可包括其他部件，諸如 :碟驅動機與卡架。卡架可包含單板電腦、類比與數位 二’輸出板、介面板與步進馬達控制器板。腔室控制軟 "括指令組’其命令特定處理之時程、氣體混合物、 腔室壓力、腔室溫度、微波功率水平、高頻率功率水平、 支撐件位置與其他參數。 腔室40亦包括功率供應器1〇4以輸送功率至腔室切 中的不同腔室部件，諸如基板切件58 _之第一電極 44a與第二電極44b。為t 马了輸送功率至處理電極44a、b， •功率供應器1〇4包括射頻電麼源，其提供具有所選射頻 與所欲之可選擇功率水平的電塵。功率供應器刚 括單-射頻電塵源，或提供高與低射頻兩者的多重電髮 24 201140720 源。功率供應器104亦可包括RF[配電路。功率供應器 Π)4可進-步包括靜電充電源’以提供靜電電荷 為靜電夾盤之基板支撐件58中的電極。當加熱器Μ係 用於基板支撐件58中時，功率供應器1〇4亦包括加熱器 功率源，其提供適當可控制的電壓至加熱器68 ^當施加 DC偏麼至氣體分配器72或基板支標件58時，功率供應 器104亦包括DC偏壓電壓源，其連接至氣體分配器^ 之面板74的傳導金屬部分。功率供應器ι〇4亦可包括其 他腔室部件(例如，腔室4〇之馬達與機器人)的功率源 基板處理腔室4〇亦包括溫度感應器（未顯示），例如執 電偶或干涉儀，以偵測腔室4〇中之表面（諸如，部件表 面或基板22表面）之溫度。溫度感應器能夠反應其之數 據至腔室控制器102,腔室控制器1〇2可應用溫度數據 藉由控制基板支撑件58中之電阻式加熱^件來控制處 理腔室40之溫度。 發現藉由本文所述方法沉積且包括一或多個介電層 25、附著層27與共形襯裡29之鈍化層20實質上不具有 缺陷（例如，傳統沉積方法中出現於底角3〇處的接縫）。 再者:在形狀複雜、高深寬比特徵結構26(例如，第Μ :所不之互連13)上沉積連續且共形塗層的鈍化層2〇。 二地’如第2Β圖所示’沉積於連接器凸塊14上之鈍 2〇亦形成具有均句厚度橫跨連接器凸塊14之圓形 启 面28的平滑且連續層。再者，連接器凸塊“之 _ °附近的底角30不具有任何裂縫或接縫16。第％圖 25 201140720 顯不/儿積於向深寬比特徵結構26(包括連接器凸塊丨*與 夕互連孔1 8)上之鈍化層2〇的又另一實例。再者，發現 在位於填充石夕互連孔18上之連接器凸塊14的介面令底 角30處不具有裂縫缺陷。 咸信傳統沉積處理中形成之缺陷係因為特徵結構Μ 之熱膨脹造成這些區域的熱應力所造成。高深寬比特徵 、:構26在高度方向中具有大尺寸變化，且再者，在特徵 «‘。構24之較大高度相對於較小寬度之間尺寸變化中有 明顯的差異°進—步相信藉由其之當前方法沉積之鈍化 層20提供不具缺陷之共形塗層係'因為薄膜之較高密 度，其反應於其之折射率與WERR比。再者，亦相信沉 積之純化層2G均勻地與下方特徵結構24(諸如，互連13 或連接器凸塊14)之複雜幾何結構共形係因為不同浸 泡、沉積與處理與共形襯裡沉積處理中產生之氣體或； 漿物種的低黏滞係數。 隨後照片顯示沉積於特徵結構24上且包括氮化石夕之 介電層25的鈍化層20缺少缺陷。舉例而言，第5圖係 顯示沉積於包括連接器凸塊14之特徵結構24上純化層 20之底角30處缺少接縫的掃描電子顯微照片，純化層 20包括氮化矽之介電層25。再者，職顯微照片亦顯示 緊密跟隨下方特徵結構24之橫剖面輪廊的純化層之 平滑且共形輪廓。此實施例中，在4〇〇〇c之沉積溫度下 沉積由氮化矽之介電層25構成之鈍化層2〇。再者：應 用多循環的沉積與處理製程以形成氣化石夕之介電層Μ。 26 201140720 此實例中，執行100次循環的沉積電漿處理以產生鈍化 層20 〇 作為另一實例，第6圖係顯示沉積於包括銅凸塊之高 深寬比特徵結構26上且沿著由氮化矽構成之鈍化層 的底角30缺少接縫之掃描電子顯微照片。此照片進一步 描繪在高深寬比特徵結構26上形成不具有缺陷之鈍化 層20。此實例中，在丨8〇。c之沉積溫度下沉積包括氮化 物之介電層25以提供高於1.88之高折射率的沉積層， 其係利用橢圓偏振在633 nm波長下測量。 又另一實例中，第7圖顯示具有包括氮化矽之介電層 25之鈍化層20的包括銅凸塊之高深寬比特徵結構26的 掃描電子顯微照片。在180。〇之沉積溫度下且厚度1〇〇〇 埃之氮化矽的共形襯裡29上沉積氮化矽層。8£]^顯微照 片亦顯示緊密跟隨下方特徵結構24之橫剖面輪廓的鈍 化層20之平滑且共形輪廓。 因此，可見即便在特徵結構係高深寬比特徵結構％ 時，藉由其之當前方法沉積之鈍化層2〇在特徵結構Μ 之角與邊緣提供實質不具缺陷之共形塗層。又再者，沉 積之鈍化層20與具有央銳或倒角之下方特徵結構24(諸 如互連13或連接器凸塊！ 4)的幾何結構共形係因為電 漿中形成之氣態電漿物種的較佳黏滯係數，以沉積鈍化 層20之氮化矽層以及其他層。 雖然顯示與描述本發明之示範性實施例， 士可設計出包括本發明且亦位於本發明之範^的^ 27 201140720 貫施例。再者’參照圖式中之示範性實施例顯示詞彙「下 方」、「上方」、「底部」、「頂部」、「上」、「下」、「第一」 與第一」與其他相關或位置詞彙，且該些詞彙係通用 的因此’隨附之申請專利範圍不應限制於本文用來描 述本發明之較佳形式、材料或空間配置的敘述。 【圖式簡單說明】 參’、、、隨後之描述、隨附申請專利範圍與附圖（描繪本發 明之實施例）可更清楚理解本發明之這些特徵結構、態樣 與優點。然而，需理解各個特徵結構可通用於本發明， 而非僅於特定圖式的内容中，且本發明包括這些特徵結 構之任何組合，其中： 第1A圖（先前技術）係基板之示意橫剖面圖，其顯示覆 蓋尚深寬比特徵結構（互連）之鈍化層之角處的接縫； 第1B圖（先前技術）係上方鈍化層之角處具有接縫之基 板上連接器凸塊的示意橫剖面圖； 第1C圖（先則技術）係具有包括互連孔之高深寬比特徵 之基板的示意橫剖面圖，並顯示鈍化層之角處的接縫； 第2A圖係基板上包括互連之高深寬比特徵的示意橫 剖面圖，且顯示提供互連之底倒角處不具有接縫之共形 塗層的鈍化層； 第2B圖係基板上連接器凸塊的示意橫剖面圖，且顯示 沉積於連接器凸塊上具有㈣沉積之共形鈍化層； 28 201140720 第2C圖係互連孔與上方之連接器凸塊的示意橫剖面 圖’其顯示連接器凸塊與互連孔上均勾鈍化層之沉積； 第3圖係用以在基板之特徵結構上沉積具有子層以 化層之處理示範性形式之流程圖； 第4圖係適合在基板上形成且處理鈍化層、執行初步 清潔與浸泡處理並沉積應力共形襯裡之基板處理腔室之 實施例的示意圖； 第5圖係掃描電子顯微照片，其顯示沉積於包括連接 器凸塊之高深寬比特徵上之氮化矽鈍化層的角落處缺少 缺陷； 第6圖係掃描電子顯微照片，其顯示沿著具有相當高 折射率之氮化矽鈍化層的角落缺少接縫；及 第7圖係包括沉積於薄共形襯裡上之氮化石夕純化層之 间深寬比特徵的掃描電子顯微照片，其顯示純化層之角 處缺少接缝或裂縫。 【主要元件符號說明】 10 、 20 、 20a 、 20b 、 20c 11 缺陷 12、24 特徵結構 14 連接器凸塊 16 接縫 18 矽互連孔 2〇d 鈍化層 13 互連 15、22 基板 17 倒角 19、25、25a、25b 介電層 29 201140720 26 高深寬比特徵結構 27 附著層 28 暴露表面 29 共形襯裡 30 底角 32 間隔 40 處理腔室 42 處理區 44a、 44b 處理電極 48 封圍壁 52 頂部 54 侧壁 56 底壁 58 基板支撐件 62 入口埠 64 基板傳送器 68 加熱器 72 氣體分配器 74 面板 76 孔 78a 第一入口 78b 第二入口 80a 第一氣體供應器 80b 第二氣體供應器 82a 第一氣體源 82b 第二氣體源 84a 第一氣體管道 84b 第二氣體管道 86a 第一氣體閥 86b 第二氣體閥 90 氣體排出裝置 92 抽吸通道 94 排出埠 96 節流閥 98 排出泵 102 控制器 104 功率供應器 30

Claims (1)

  1. 201140720 七、申請專利範圍： 1· -種在-基板之數個特徵結構上形成—純化層之方 法，該純化層包括一氮化石夕層，而該方法包括： ⑷在-處理區中提供—具有複數個特徵結構之基 板； (b) 在-第-階段中，將—包括—切氣體與一含氮 氣體之介電沉積氣體導入該處理區，並充能該介電沉積 氣體以沉積一氮化矽層於該些特徵結構上； (c) 在第一階段中，將一組成不同於該介電沉積氣 體之處理氣體導入該處理區，並充能該處理氣體以處理 該氮化矽層；及 (d) 執行複數次該第一階段與該第二階段。 2.如申請專利範圍第1項所述之方法，其中該處理氣體 包括一含氮氣體。 3·如申請專利範圍第1項所述之方法，其中（c)包括藉 由停止該介電沉積氣體之含石夕氣體的流動同時持續該含 氮氣體之流動來形成該處理氣體。 4·如申請專利範圍第1項所述之方法，包括導入一包括 矽烷之含矽氣體與一包括氨與氮之含氮氣體。 31 201140720 包括提供比例約 5·.如申請專利範圍第4項所述之方法 1:1:8 至約 2:1:2〇 之 SiH4:NH3:N2。 t如申請專利範圍第1項所述之方法，其中（b)包括設 疋數個處理條件以沉積一折射率”小_ U8之氮化石夕 層’利用橢圓偏振在633 nms長下測量該折射率。 7·如申請專利範圍第】項所述之方法，其中⑻包括設 疋數個處理條件以沉積—氮切層，相對於㈣一氧化 物層㈣該氮切之鈍化層的㈣料㈣值職汉小 於 5.2。 8. 如申請專利範圍第}項所述之方法，包括維持該基板 在一約180°C至約55(Γ(：之溫度下。 9. 如申請專利範圍第」項所述之方法，包括提供一具有 複數個高深寬比特徵結構之基板，該複數個高深寬比特 徵結構包括下列任一者： (〇數個包括一含金屬材料之互連或連接器凸塊； (ii) 數個石夕互連孔；或 (iii) 數個氧化物結構。 10 ·如申明專利範圍第i項所述之方法，包括一初步清潔 階段’該初步清潔階段包括⑴提供—包括一含氫氣體之 32 201140720 凊潔氣體進入該處理區，及（ii)充能該清潔氣體以形成一 包括含氫物種之經充能清潔氣體，其清除該基板之數個 特徵結構上的一原生氧化物薄臈。 • 如申請專利範圍第1〇項所述之方法，其中該含嚴氣 體包括⑴ h2，（ii) N2 與 nh3，（iii) h2〇，或（iv) SiH4。 12. 如申請專利範圍第10項所述之方法，其中提供該清 潔氣體之體積流率係約100 sccm至約18升/分鐘。 13. 如申請專利範圍第1〇項所述之方法，其中該清潔氣 體包括： (1) 體積流率約500至約3000 sccm之h2 ; (2) 體積流率約50至約300 seem之NH3與體積流率 約1000升/分鐘至30,000升/分鐘之n2 ;或 (3) 體積流率約500至約3000 seem之H2與體積流率 約 50 至約 300 seem 之 NH3。 14.如申睛專利範圍第1〇項所述之方法，其中在一約5〇 至約700瓦特之功率下*RF能量耦接至該處理區附近之 數個處理電極來充能該清潔氣體。 15 ·如申請專利範圍第1項所述之方法，包括一初步浸泡 階段，該初步浸泡階段包括⑴提供—包括矽烷之浸泡氣 33 201140720 體進入該處理區，及（ii)將該基板維持在一約1〇〇至約 240 C之溫度下以沉積一附著層於該基板之該些特徵結 構上。 16.如申請專利範圍第15項所述之方法，其中該浸泡階 4又包括下列至少一者： (1) 提供一包括矽烷、氨與氮之浸泡氣體； (2) 將該浸泡氣體維持在一約丨至約5托耳之壓力 下；或 (3) 執行該浸泡階段達約5至約30秒。 17·如申請專利範圍第16項所述之方法，其中該浸泡氣 體包括體積流率約200至約800 seem之石夕烧、流率約200 至約800 sccm之氨、及流率約4000至約12,〇〇〇 sccm之 氮。 18.如申請專利範圍第i項所述之方法，包括藉由下列步 驟沉積一共形襯裡於該些特徵結構上： (1) 將一包括（i) SiH4、NH3 與 N2 ; (ii)三矽烷胺、NH3 與A ; (in) SiH4或& ;或（iv)三矽烷胺或n2化學物之 襯裡氣體導入該處理區；及 (2) 充能該襯裡氣體以形成一電漿好沉積一共形襯裡 於該基板之該些特徵結構上，該共形襯裡的厚度大於約 100埃且拉伸應力至少約i00MPa。 34 201140720 19. 如申請專利範圍第is項所述之方法，包括沉積一共 形襯裡’該共形襯裡包括一氮化矽層，且該氮化矽層具 有一通過該層之厚度的應力梯度。 20. 如申請專利範圍第μ項所述之方法，包括藉由下列 沉積一共形襯裡：在該沉積處理過程中控制該s出4之流 率由一尚流率至一低流率，並改變施加至該處理區附近 之一對處理電極的RF功率施加速率。 21. 如申請專利範圍第18項所述之方法，包括沉積一襯 裡，該襯裡包括複數個具有不同應力水平的分離氮化矽 層。 22.如申請專利範圍第18項所述之方法，包括藉由依序 沉積-氣化石夕層並部分蝕刻掉該沉積之氮化石夕層 一氮化石夕層。 23·如申請專利範圍第22項所 一 唄m遮之方法，包括蝕刻掉診 沉積之層以改變該些特徵結構 ^ K 底角處的倒角式蛤 廓。 询 35
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US20110223765A1 (en) 2011-09-15
WO2011115997A2 (en) 2011-09-22
CN102804350A (zh) 2012-11-28
WO2011115997A3 (en) 2012-04-12
KR20130050918A (ko) 2013-05-16
US8563095B2 (en) 2013-10-22
KR101911469B1 (ko) 2019-01-04

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