TW201025437A - Through wafer via and method of making same - Google Patents

Through wafer via and method of making same Download PDF

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Publication number
TW201025437A
TW201025437A TW98125346A TW98125346A TW201025437A TW 201025437 A TW201025437 A TW 201025437A TW 98125346 A TW98125346 A TW 98125346A TW 98125346 A TW98125346 A TW 98125346A TW 201025437 A TW201025437 A TW 201025437A
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Taiwan
Prior art keywords
substrate
conductive
trench
wafer
additional
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TW98125346A
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English (en)
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TWI479554B (zh
Inventor
Han-Yi Ding
Alvin Jose Joseph
Anthony Kendall Stamper
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Ibm
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Publication of TWI479554B publication Critical patent/TWI479554B/zh

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

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201025437 六、發明說明： 【發明所屬之技術領域】 本發明有關積體電路晶片的領域，尤其有關積體電路晶 片中使用的晶圓穿孔及製造該晶圓穿孔的方法。 【先前技術】 為增加使用積體電路晶片之裝置的密度，需要對積體電 路曰曰片的頂面及底面均能提供互連。這需要從積體電路晶片 Φ 的頂面到底面，形成適於載送高頻及DC信號的晶圓穿孔。 許夕現有的穿孔方案不是在與現有積體電路製程的整合上 有困難’就是造成積體電路晶片的正面及底面之間令人無法 接文的信號傳播降級。因此，本技術中需要克服上述缺點及 限制。 【發明内容】 本發明之第一方面為一種結構，包含：一半導體基板， 其具有一頂面及一對置底面；及一晶圓穿孔陣列，其包含至 少一個導電晶圓穿孔及至少一個非導電晶圓穿孔，該晶圓穿 孔陣列之每一晶圓穿孔自該基板之該頂面延伸到大於至該 基板之該底面的中途及直到該基板之該底面之間。 本發明之第二方面為一種方法，包含：形成一包含至少 一個導電晶圓穿孔及至少一個非導電晶圓穿孔的晶圓穿孔 陣列通過具有一頂面及一對置底面的半導體基板，該晶圓穿 孔陣列的每一晶圓穿孔自該基板之該頂面延伸到大於至該 基板之該底面的中途及直到該基板之該底面之間。 201025437 g本發明之第三方面為一種方法，包含：（a)形成一第一溝 渠及一第二溝渠於一半導體基板中，該第一及該第二溝渠分 別自該基板之一頂面朝該基板之一對置底面延伸一小於該 基板之一厚度的距離；(b)同時以一介電材料完全填充該第一 溝渠及形成該介電材料之一襯料於該第二溝渠的侧壁上；(c) 以一導電材料填充該第二溝渠中的剩餘空間；及(d)自該基板 之該底面薄化該基板以形成該基板的一新底面，該第一溝渠 Φ 的該介電材料及第二溝渠的該襯料及導電材料在基板的該 新底面中暴露。 本發明之第四方面為一種通過半導體基板的信號傳輸 線，該基板具有一頂面及一對置底面，包含：一導電晶圓穿 孔，其自該基板之該頂面延伸至該基板之該底面，該導電穿 孔的侧壁與該基板電絕緣；及一非導電穿孔，其自該基板之 該頂面延伸到大於至該基板之該底面的中途及直到該基板 參 之該底面之間，該非導電穿孔靠近該導電晶圓穿孔並以該基 板之一區域與該導電晶圓穿孔分開。 【實施方式】 用語「晶圓穿孔」定義封裝之積體電路或晶片中自基板 頂面延伸穿過基板到達基板對置底面的結構。根據本發明具 體實施例的晶圓穿孔可為導電或非導電。雖然在下文的描述 中，將導電及非導電（即，絕緣)的穿孔說明及圖解為從晶片 頂面延伸到底面’但可將本發明實施於以下情況：導電穿孔 完全延伸穿過晶片，而非導電穿孔僅局部延伸穿過晶片，因 4 201025437 為非導電穿孔的一個用途是隔離而非在晶片頂面及底面之 間傳遞電仏號。導電穿孔包括至少一個導電元件並可包括非 導電元件。非導電穿孔包括至少一個非導電元件並可包括完 全被非導電元件包圍的導電元件。晶圓穿孔的「晶圓」源於 以下事實·穿孔在從稱為「晶圓」的半導體基板分割積體電 路之前形成。用語「三維裝置」定義的裝置為：包含二或多 個因堆疊在彼此上方而電連接及實體接觸的個別基板。 圖1A至1〇為圖解製造本發明具體實施例之晶圓穿孔 陣列之初始步驟的截面圖。在圖1A中，半導體基板〗⑻具 有頂面105。在頂面1〇5上形成的是第一介電層11(^在第 一介電層110的頂面115上形成的是第二介電層12〇。第一 及第二介電層110及120僅是舉例說明，且形成在基板1〇〇 的頂面105之上的可以只有一個介電層或多於兩個介電 層。在一範例中’基板1〇〇為塊狀矽基板。在一範例中，第 一介電層110是二氧化矽及第二介電層12〇是氮化矽。 在圖1B中，將溝渠125及130蝕刻通過第一及第二介 電層110及120並進入基板1〇〇中。溝渠125及130可使用 光微影/餘刻製程來形成。示範性光微影/餘刻製程包含：（1) t成光阻層於第一介電層120上，(2)透過圖案化光罩使光阻 層曝光於光化輻射及顯影光阻的曝光或未曝光區域，形成開 口於光阻層中；（3)使用例如反應性離子蝕刻(RIE)製程，触 刻穿過弟一及第二介電層；（4)移除圖案化的光阻層，及(5) 使用第一及第二介電層中的圖案作為圖案化硬遮罩，使用例 如RIE製程蝕刻基板1〇〇。雖然在圖1B中顯示溝渠ι25及 5 201025437 130被姓刻成相同深度’但溝渠125及130可被敍刻成不同 深度。例如，一般稱為「波希(Bosch)」矽蝕刻製程的蝕刻製 程將蝕刻具有寬(W2)開口的溝渠比具有窄開口 (W1)的溝渠 深。請參見圖5。蝕刻溝渠130比較深將造成圖6的結構。 因此，溝渠125及130可分別從105延伸到大於至基板1〇〇 之底面的中途及直到基板100之底面之間。 然而，如果基板100是絕緣體上矽(SOI)基板(即，具有 埋藏氧化物層或BOX層的>6夕基板)且埋藏氧化物層頂面位置 與基板100之頂面105距離D1，則就算使用「波希」蚀刻 製程’溝渠125及130仍將被钱刻成相同的深度，因為Βοχ 層將當作姓刻停止層。在一範例中，BOX層包含二氧化石夕。 溝渠125及130延伸至基板100中離基板之頂面1〇5距 離D卜溝渠125具有寬度W1及溝渠130具有寬度W2。 W2大於wi。在一範例中，W1約1微米至約3微米。在一 範例中，W2約3微米至1〇微米。在一範例中，D1約5〇 微米至2〇〇微米。在一範例中，W1約2微米、W2約5微 米及D1約150微米。由於溝渠125及13〇可延長於圖式平 面中及平面外（即，從上方看時為長方形），W1及W2的寬 度為溝渠125及13〇的最小寬度(即，長方形的短邊）。 在圖1C中，多晶矽層135係沈積於第二介電層12〇的 ，面140、溝渠125及130的側壁145及底部150上。在— j中’多晶石夕層135包含摻雜^^型或p型的多晶石夕。在 例中’多晶判135包含摻雜硼的多晶石夕。多晶石夕層 6 201025437 135具有厚度ή。在一範例辛，ή約〇 8微米至約2.4微米。 在圖1D中，執行氧化，將多晶矽層135(見圖lc)轉換 成二氧化矽層155。二氧化矽層155具有厚度T2。二氧化矽 層155完全填充溝渠125，但未完全填充溝渠130，因為溝 渠丨3〇的寬度W2大於二氧化矽層155的厚度T2的兩倍。 二氧化矽層共形地覆蓋溝渠130的側壁及底部。在一範例 中’T2約等於W1的一半。在一範例中，氧化多晶梦層(見 圖ic)以形成二氧化矽層155係使用高壓氧化(ΗΙρ〇χ)製程 來執行。 摻雜硼的多晶矽(即，圖1C的層135)的ΗΙΡΟΧ為較佳， 因為摻雜硼的多晶矽的高氧化率及ΗΙΡ〇χ在深溝渠中形成 均勻氧化物厚度的能力。 或者，圖1D所示結構可用以下方式形成：氧化(如，在 熔爐中）圖1Β中溝渠125及130的侧壁及底部，或沈積(如， 利用化學汽相沈積(CVD)或原子層沈積(ALD))氧化物於溝 125及130的側壁及底部上。或者，任何合適介電質，諸 如氮化石夕、氧化銘，或多個介電質的組合均很合適。 在圖1Ε中，多晶石夕層170形成於二氧化石夕層I%的頂 面Π5上且完全填充溝渠130中的剩餘空間。在一範例中， 多晶矽層170包含本徵(即，未摻雜的）多晶矽。在第二範例 中’用任何已知摻雜物，諸如磷、砷、或硼，對多晶石夕進行 7 201025437 原地摻雜。 中執行化學機械研磨(CMP)以從二氧化石夕層 ㈣湛除多晶石夕層Μ’因此二氧化石夕層155的頂面175 圃：中多晶矽層Μ的頂面共面。或者，可採用CMP 1丄〜、化贿製程的任何組合以使晶圓平坦化，如本技 ❹
在圖1G中，執行多晶矽凹陷製程自介電層155的頂 面175及溝渠130的上方區域移除所有多晶珍層170。多晶 石夕層170在凹陷製程之後留在溝渠130中的頂面低於基板 100的頂* 105。多晶石夕凹陷製程可使肖RIE、濕式餘刻、 或RIE蝕刻及濕式蝕刻的組合來執行。在較佳具體實施例 中，此凹陷延伸於介電層110下方，以有助於用層185使溝 渠封頂’如圖II所示。 在圖1H中，介電層185形成於二氧化矽層155的頂面 175上及溝渠丨3〇中。介電層185完全填充溝渠130中因圖 1F的多晶矽凹陷蝕刻所造成的空間。或者，介電層ι85填 充溝渠130中形成的空間，致使空隙在圖u所示平坦化之 後不會延伸至表面1〇5。在一範例中，介電層185包含TEOS 氧化物（即’使用四乙氧基矽烷前驅物以CVD形成的氧化 物）、矽烷氧化物(即，使用矽烷前驅物以CVD形成的氧化 物）、或任何使用LPCVD (即，低壓CVD)或HDPCVD (即， 高密度電漿CVD)或任何其他已知方法沈積的介電質。 8 201025437 在圖II中’執行CMP及/或其他蝕刻以自基板1〇〇的 頂面105上方移除介電層185、二氧化矽層155、第二介電 層120，在溝渠130中留下介電層185的帽蓋。二氧化矽層 155亦可留在溝渠125中。在CMp之後，溝渠125中二氧 化矽層155的頂面、溝渠no中二氧化矽層155的邊緣、溝 渠中介電層185的頂面、及基板1〇〇的頂面1〇5全部共面或 大體上共面。雖然顯示完全移除基板1〇〇之上的所有層，但 亦可執行局部移除或選擇性局部移除。 在圖1J中，新的第一介電層190及新的第二介電層195 形成於基板100的頂面1〇5。二氧化矽層155留在溝渠125 中，及二氧化矽層155、多晶矽層170、及介電層185留在 為’I電層190及195所保護的溝渠13〇中。介電層190及 195的用途是為了有助於形成積體電路結構，諸如淺溝渠隔 離（STI)、深溝渠電容器、金氧半導體場效電晶體 (MOS^ET)、雙極接面電晶體、二極體、變容二極體、薄膜 參 電阻器、M0S電容器等，如本技術中已知。或者，可採用 任何已知的方法及結構組合來形成積體電路結構。 在圖1K中，在基板100中結合新的第一及第二介電層 190及195(賴U)，利耽微影/侧製程形成STI200,類 似於上文所述，後續為TEOS CVD，其後為CMP。 接下來，執行額外光微影/敍刻製程/沈積製程，以形成 FET 205及溝渠電容器21〇。順2〇5及清渠電容器為可在 製造中此時形成的频電路裝置範例。其他可在此時形成的 9 201025437 裝置包括雙極電晶體、雙極互補金氧半導體矽鍺（BiCM0S SiGe)電晶髏、二極體，金氧半導體（m〇S)電容器、及電 阻器。FET 205包括源極/汲極215、閘極介電質22〇、閘極 電極225、及矽化物接點230。溝渠電容器210包括内板235 及介電層238。在形成閘極介電層22〇之前，移除新的第一 及第一介電層190及195 ;及在形成石夕化物層230之後，在 基板100的頂面105上方形成層間介電層24(^舉例而言， 層間介電層240包含下方介電層245及上方介電層25〇。層 ❿ 間介電層240可為單層或可包括多於兩層。在一範例中，下 方介電層245包含氮化石夕，及上方介電層250包含蝴礙石夕酸 鹽玻璃(BPSG)。 在圖1K及後續的圖il至1〇中，為清楚之故，顯示下 方介電層245未覆蓋FET 205的閘極225。實際上，下方介 電層245也覆蓋FET 205的閘極225。 瞟在圖1L中’使用上文所述光微影/蝕刻製程，在FET2〇5 的矽化物層230上方，形成穿過下方及上方介電層245及 250 的開口 255。 在圖1M中，在開口 255中形成矽化物層230的導電間 柱接點265 ’及在接點265及上方介電層25〇上形成保護層 270。例如利用在上方介電層25〇上方形成完全填充開口 255 的導電層(如，利用蒸發、濺鍍或沈積），其後再利用CMP， 即可形成接點265。然後形成保護層270。接點265可單獨 包含以下針對晶圓穿孔蕊芯275 (見圖】〇)及晶圓穿孔接點 10 201025437 280(見圖l〇)所述的任何材料組合^在一範例中，保護層27〇 為介電層。在一範例中，保護層27〇包含氮化矽。 應明白，許多其他間柱接點265在此時形成於基板1〇〇 中的其他裝置。應明白，還存有許多形成及金屬化間柱接點 265的其他方法。應明白，有許多方法及結構可用來形成積 體電路裝置的間柱接點，如本技術中已知。 在圖1N中，使用上文所述的光微影/姓刻製程，在溝渠 130上方’形成穿過保護層27〇及上方及下方介電層245及 250的開口 132。然後，執行rjE以自溝渠13〇移除介電層 185 (見圖1L)。接下來，使用R!E蝕刻、濕式蝕刻或濕式及 RIE的組合，自溝渠130移除多晶矽層17〇(見圖iL)。注意， 在這些多晶矽層170蝕刻期間，介電層155保護基板1〇〇 (當 基板100是矽時)不受蝕刻。為避免蝕刻基板1〇〇，在溝渠 130上方的開口 132不得超出介電層155,及在一較佳具體 實施例中，開口 132被對準致使開口 132落在層155内（即， 當層270、250及240被蝕刻時，開口完全落在層ι85上， 見圖1M)’致使當多晶矽層170在層185被蝕刻之後在開口 132中暴露時，介電層155在多晶矽層170被蝕刻的情况下 不在開口中暴露。 在圖10中，晶圓穿孔蕊芯275形成於溝渠130中，及 (與晶圓穿孔蕊芯275)—體形成的晶圓穿孔接點280形成於 溝渠130上方保護層270 (見圖in)及層間介電層240中的開 口中。例如，利用在上方介電層250上方形成完全填充溝渠 201025437 130及保護層270(見圖1N)與層間介電層24〇中之開口的導 電層(如’利用蒸發、賤錢或沈積），及其後利用CMp，可形 成晶圓穿孔蕊芯275及晶圓穿孔接點28〇β在圖1〇中，CMp 已完全移除所有保護層270 (見圖1Ν)ο或者，保護層27〇 的薄化層可在CMP之後保留。晶圓穿孔接點28〇及間柱接 點265的頂面與上方介電層25〇的頂面共面。 在一範例中，晶圓穿孔蕊芯275及晶圓穿孔接點28〇包 含金屬。在一範例中，晶圓穿孔蕊芯275及晶圓穿孔接點 280包含鶴(W)或鎮及I化鈦(τίΝ)。在一範例中，晶圓穿孔 游芯275及晶圓穿孔接點280包含第一沈積的氮化鈦共形層 及第二沈積的鎢層。在一範例中，晶圓穿孔蕊芯275及晶圓 穿孔接點280包含第一沈積的氮化鈦共形層、第二沈積的共 形鈦(Ti)層及第三沈積的鎢層。鈦、氮化鈦及鎢可使用CVD 來沈積。 在一範例中’晶圓穿孔蕊芯275及晶圓穿孔接點280包 含鎢或鎢及氮化钽(TaN)。在一範例中，晶圓穿孔蕊芯275 及晶圓穿孔接點280包含第一沈積的氮化组共形層及第二 沈積的鎢層。在一範例中，晶圓穿孔蕊芯275及晶圓穿孔接 點280包含第一沈積的氮化鈕共形層、第二沈積的共形鈕(Ta) 層及第三沈積的鎢層。鈕及氮化鈕及鎢可使用CVD來沈積。 其他可用於晶圓穿孔蕊芯275及晶圓穿孔接點280的冶 金組合包括銅(Cu)、釕(Ru)、Ta及TaN的組合。這些組合包 括以下組合，每一組合按形成順序為：Ta/Cu、TaN/Cu、 12 201025437
Ru/Cu ' TaN/Ta/Cu/ ' TaN/Ru/Cu > Ta/Ru/Cu ' Ru/Ta/Cu ' Ru/TaN/Cu、TaN/Ta/Ru/Cu。 應明白，間柱接點265可由形成晶圓穿孔蕊芯275及晶 圓穿孔接點280的相同或不同材料形成。同樣地，間柱接點 可由上文針對晶圓穿孔蕊芯275及晶圓穿孔接點280所列的 任何材料組合形成。應明白，許多晶圓穿孔蕊芯275及晶圓 穿孔接點280可在此時形成。應明白，還存有許多形成及金 ® 屬化晶圓穿孔蕊芯275及晶圓穿孔接點280的其他方法。例 如’可使用電鍍銅代替鎢’及可使用鈕或氮化鈕代替氮化 鈦。亦應明白，如圖2A至2J所圖解及如上文所述，藉由從 底部薄化基板100,可形成晶圓穿孔。晶圓穿孔蕊芯275與 基板100為二氧化矽層155所電隔離。晶圓穿孔蕊芯275及 二氧化矽層155在溝渠130之側壁上的部分將成為導電晶圓 穿孔(晶圓穿孔蕊芯275為導電部分及二氧化矽層為非導電 刀）。在溝渠125中的二軋化發層155將成為非導電晶圓 ❹ 穿孔。 圖Μ至2J為圖解完成製造根據本發明具體實施例之晶 圓穿孔陣列及使用根據本發明具體實施例之晶圓穿孔陣列 製造三維裝置的截面圖。 在圖2Α(未按比例繪製）中，形成於一組層間介電層3〇〇 中的是對應的（widng)及穿孔3〇5。可選端子概整31〇形 成於該組層間介電層3〇〇的頂面315且與該組層間介電芦 300的最上方層間介電層中的最上方佈線3()5電接觸。該^ 201025437 層間介電層的最下謂電層巾的舞制柱接點265 及集成的接點區域280實體接觸及電接觸。在圖2A中未圖 解該組層間介電層3〇〇的個別層間介電層。將操作基板325 附著於該組層間介電層300的頂面315。操作晶圓325係使 用-層黏著劑來附著(未顯示）。在—範例中，操作基板325 為石央晶圓。 在圖2B中基板1〇〇自底部薄化(例如，利用研磨）， 以形成離溝渠125及130距離D2的新底面32〇。在一範例 中D2約5微米至約5〇微米。在一範例中，D2約2〇微米。 在薄化之後，基板100的厚度為D3。在一範例中，出約5〇 微米至約200微米。在一範例中，D3約170微米。 在圖2C中’執行對料選擇性的哑或濕式侧，使 基板100的底面320 (見圖2B)凹陷，因此溝渠125及13〇 的填充材料突出於新頂面320A之上。 在圖2D中，執行CMp以移除突出於頂面(見圖 2^：)之上的二真充材料，以形成晶圓穿孔陣列33〇。在圖犯的 範例中母曰曰圓穿孔陣列330包括兩個非導電晶圓穿孔 =及一個導電穿孔·。在晴之後，導電晶圓穿孔 袅芯275及—礼化矽層155 (見圖2C)在基板1〇〇的底面32〇 處暴露。 在0 2E中，在—氧化石夕上方執行對優先餘刻石夕有選擇 201025437 性的RIE或濕式蝕刻，以使頂面32〇A(見圖2D)凹陷低於晶 圓穿孔陣列330的底部’及以形成基板1〇〇的新底面335。 在圖2F中，在基板底面335及晶圓穿孔陣列330之上 形成介電層340。在一範例中’介電層340為電漿增強化學 汽相沈積(PECVD)氧化石夕。 在圖2G中’執行CMP以自晶圓穿孔陣列330的底面 移除介電層340。介電層340留在介電層34〇的底面335上， 且介電層340填充在晶圓穿孔陣列33〇間在每一晶圓穿孔陣 列之個別晶圓穿孔125A及130A間的任何空間。晶圓穿孔 125A及130A的底面為共面或大體上與介電層的頂面 350共面。 或者，可繼續在圖2B中圖解及上文所述的背面研磨製 私·，直到圖2D的非導電晶圓穿孔125A及導電晶圓穿孔 130A直接形成(跳過圖2C的製程）’或在研磨及移除晶圓穿 孔及表面320A(見圖2D)之任何研磨損壞的「清除」CMp之 後形成。此替代方案有利於應用在溝渠125蝕刻至基板1〇〇 中明顯不如溝渠130 (見圖2A)深時。如果溝渠13〇被蝕刻得 明顯比溝渠125深(見圖5)，則研磨將暴露導電穿孔13〇A而 非非導電穿孔125A，如圖6所示。 注意’晶圓穿孔125A包含僅填充有絕緣體的第一溝 渠，及晶圓穿孔130A包含具有僅由包圍導電蕊芯的介電襯 201025437 料組成之填料的第二溝渠。 在圖2H中，導電襯墊345形成於晶圓穿孔陣列330上 介電層340的頂面350上，及導電焊料凸塊355形成於襯墊 345上。在一範例中，襯墊345及焊料凸塊355係由透過圖 案化光阻層電鍍或由透過金屬遮罩蒸發而形成。如果襯墊 345係以鍍敷形成，將首先沈積薄的電晶種層，其在移除光 阻層之後以RIE或濕式钱刻移除。 在圖21中’在晶片切割之前或之後，移除操作晶圓325 (見圖2G)。移除操作晶圓325的示範方法係使黏著劑曝光於 紫外線輻射下，如本技術中所熟知。在一較佳具體實施例 中’在切割之後移除操作晶圓325，使造成薄化晶圓破裂的 可能性降到最低。 圖2J為在焊料回焊步驟之前的分解圖。在圖2J中，使 含有電組件的上方基板360以導電焊料凸塊365對準端子襯 墊31〇，及基板1〇〇以焊料凸塊355對準具有導電襯墊375 及含有電組件(未顯示)的下方基板37〇β此配置允許在熔化 2料凸塊、對基板100、360及37〇 一起進行電線配線、及 完成製程的退火之前，三個組件的自我對準。電組件範例包 括但不限於：電晶體、二極體、電阻器、電容器、電感器及 雖然在圖2J中圖解襯墊至焊料凸塊的連接，但⑴在基 201025437 板360及基板100之間、（ii)在基板100及基板370之間、 或(iii)在基板360及基板100之間及在基板1〇〇及基板370 之間’也可以使用其他連接類型，諸如襯墊至襯墊的連接。 雖然在基板360上顯示焊料凸塊及在基板1〇〇上顯示襯塾， 但襯墊可形成於基板360上及焊料凸塊可形成於基板1〇〇 上。雖然在基板100上顯示焊料凸塊及在基板370上顯示槻 墊’但襯墊可形成於基板1〇〇上及焊料凸塊可形成於基板 370上。基板360可以佈線或拉片接合取代。如果交換基板 ❹ 1⑻的焊料凸塊及襯墊，則基板370可以佈線或拉片接合取 代。 圖3A至3D為根據本發明具體實施例之晶圓穿孔的示 範平面圖。在圖3A中，單一晶圓穿孔陣列330A由以下組 成：以二氧化矽層155填充的非導電晶圓穿孔125A，及由 w入在導電穿孔區域275及基板1〇〇之間的二氧化碎層155 組成的單一導電晶圓穿孔130A。 在圖3B中，晶圓穿孔陣列330B由以下組成：兩個以 二氧化矽層155填充的非導電晶圓穿孔125A，其在由介入 在導電穿孔區域275及基板1〇〇之間的二氧化石夕層155組成 的導電晶圓穿孔130A的對侧上。 在圖3C中’晶圓穿孔陣列33〇c包含：四個以二氧化 矽層155填充的非導電晶圓穿孔丨25A，其在由介入在導電 穿孔區域275及基板1〇〇之間的二氧化矽層ι55組成的導電 晶圓穿孔130A四側的每一侧上。 201025437 在圖3D中，晶圓穿孔陣列330D由以下組成：七個以 二氧化矽層155填充的非導電晶圓穿孔125A，及由介入在 導電穿孔區域275及基板100之間的二氧化矽層155組成的 兩個導電晶圓穿孔130A。晶圓穿孔125A中的三個位在兩個 晶圓穿孔130A之間。晶圓穿孔125A中的四個位置與前三 個晶圓穿孔125Α及兩個晶圓穿孔130的組合所形成之四側 的每一側對置。晶圓穿孔陣列330Β、330C及330D用作共 參 面波導。 、 在圖3Α、3Β、3C及3D的每一個圖式中，每個晶圓穿 孔125Α及130Α為基板1〇〇的一個區域所包圍。本發明本 具體實施例的晶圓穿孔包括：至少一個導電元件，其從基板 頂面延伸穿過基板到達基板底面；及至少一個非導電（即， 介電質或絕緣體)元件，也是從基板頂面延伸穿過基板到達 基板底面。 應明白’具有不同數量及組態的晶圓穿孔125Α及130Α 的許多其他晶ΒΙ穿孔陣列也是可行的，且不限於在圖3Α、 3Β、3C及3D中所示的數量及組態。 ，4Α至4D為使用根據本發明具體實施例之晶圓穿孔 :模型的平面圖。在圖4Α、4Β、4C及4D中，G代表 且連接至接地的導電體填充溝渠；8代表未與 ί埴吞接至^號源的導電體填充溝渠；1代表電絕緣 一、，木’ IG代表連接至接地且與基板絕緣的導電體填 201025437 圖4A、4B、4C及4D的結構係模型化為用於特性阻 傳播損失及纽介電⑽的錢波導。低_損失及小 的有效介電常數為較佳。此模型基於：相對介電常數U 9 及導電率7.41 Siemens/公尺的石夕基板；針對G、圯、s及岱 結構之導電體，導電率丨細？ Siemens/公尺_ ;及針對i、 IG及IS結構的絕緣體，相對介電常數41的二氧化矽。 俯視圖中G及S結構的尺寸為5〇x3微米。俯視圖中IG 及1s結構的尺寸為52x5微米(具包圍之絕緣體丨微米厚的G 及s結構）。俯視圖中〗結構的尺寸為52χ5微米 。在 Ansoft HFSS-3D全波EM模擬軟體上執行模擬。表工給出圖4A、 4B、4C及4D中每一結構的模擬結果。
表I 案例 特性阻抗 傳播損 失 (dB/mm) 案例1的 傳播損 失〇/〇 有效Er 圖4A 22.61+j〇.96 1.329 100 12 136 圖4B 24.〇8+j〇71 1.062 ^--—_ 70 Q 1 (Λ ΠΟΊ 圖4C 27.〇7+j〇.37 0.777 58.5 ------- 1U. ILL 8.4657 圖4D 28.42+j〇.23 0.635 47.8 7.7056 19 201025437 根據模擬可以得到以下結論。對於共面波導，絕緣晶圓 穿孔具有較低特性阻抗、較少傳播損失、較低有效介電常數 及對於較少潛在不合意耦合的信號傳播為較佳。原因是，矽 有損，但二氧化碎沒有。矽的較高介電常數引起比較低介電 常數二氧化矽之寄生電容高的寄生電容。 因此’接地結構可使用如在本發明具體實施例中之直接 接觸基板的晶圓穿孔(G結構），只要晶圓穿孔上的電壓夠 低’致使幾乎沒有或沒有任何電流傳導通過基板。對於信號 結構’為降低通過基板的信號傳導，諸如本發明第二及第三 具體實施例中的絕緣導體(IS結構)為較佳。 圖5為圖解圖！8所示結構之替代結構的截面圖。在圖 5中，溝渠130B從頂面1〇5延伸至基板1〇〇中距離D3，而 溝渠125從頂面1〇5延伸至基板1〇〇距離〇2，如上文參考 圖1B所述。D3大於D2,而〇2等於m (見圖1B)。 圖6為圖解圖21所示結構之替代結構的截面圖。如果 圖1B的結構以圖5的結構取代，則產生圖6的結構❶在圖 6中，導電穿孔130B接觸襯墊345,而非導電穿孔125B (在 此障況中為誤稱，其為局部穿孔)未接觸襯墊345。基板 及介電層340的區域介於非導電穿孔及襯墊345之間。 _因此，本發明具體實施例提供將晶圓穿孔整合至現有積 體電路製程的結構及方法，其在積體電路“正面及底面之 20 201025437 間具有良好的信號傳播。 上述本發明具體實施例的說明是為了瞭解本發明。應明 白’本發明不限於本文所述的特定具體實施例’而是在不脫 離本發明範疇下，能夠進行各種修改、重新配置及替換，正 如本技術人士所明白的。因此，以下申請專利範圍是用來涵 蓋此種在本發明精神及範疇之内的修改及變更。 【圖式簡單說明】 本發明的特色如隨附的申請專利範圍所述。然而，要完 全瞭解本發明本身，請在連同附圖一起閱讀時，參考解說性 具體實施例的詳細說明，圖式中： 圖1A至1〇為圖解製造本發明具體實施例之晶圓穿孔 陣列之初始步驟的截面圖； 圖2A至2J為圖解完成製造根據本發明具體實施例之晶 圓穿孔陣列及使用根據本發明具體實施例之晶圓穿孔陣列 ® 製造三維裝置的截面圖； 圖3A至3D為根據本發明具體實施例之晶圓穿孔的平 面圖； 圖4A至4D為使用根據本發明具體實施例之晶圓穿孔 之波導模型的平面圖； 圖5為圖解圖1B所示結構之替代結構的截面圖；及 圖6為圖解圖21所示結構之替代結構的截面圖。 【主要元件符號說明】 半導體基板 100 201025437
105 110 115 120
125、130、130B
125A、125B
130A、130B 132 、 255 135 、 170 140 145 150 155 175 185 、 340 190 195 200 205 210 215 220 225 230 235 238 半導體基板頂面 第一介電層 第一介電層頂面 第二介電層 溝渠 非導電晶圓穿孔 導電穿孔 開口 多晶矽層 第二介電層頂面 溝渠侧壁 溝渠底部 二氧化矽層 二氧化矽層頂面 介電層
新的第一介電層 新的第二介電層 淺溝渠隔離(STI) FET 溝渠電容器 源極/汲極 閘極介電質 閘極電極 矽化物接點 内板 介電層 22 201025437 240、300 層間介電層 245 下方介電層 250 上方介電層 265 導電間柱接點 270 保護層 275 晶0穿孔.游芯 280 305 晶圓穿孔接點 對應的佈線及穿孔 φ 310 315 可選端子襯墊 層間介電層之集合的頂面 320 新底面 320Α 新頂面 325 330 330Α、330Β、330C、330D 操作基板 晶圓穿孔陣列 晶圓穿孔陣列 335 345 、 375 基板的新底面 導電襯墊 W 350 介電層頂面 355 ' 365 導電焊料凸塊 360 上方基板 370 下方基板 23

Claims (1)

  1. 201025437 七、申請專利範圍： 1.一種結構，其包含： 一半導體基板，其具有-頂面及一對置底面；及 一晶圓穿孔陣列，其包含至少一個導電晶圓穿孔及至少一 個非導電晶圓穿孔，該晶Η穿孔陣列之每—晶圓穿孔分別延伸 到大於至該基板之該底面的中途及直到該基板之該底面之間。 2.如申請專利範圍» 1項所述之結構，其中該至少一個非導電 孔包含-僅填充有-絕緣體的第—溝渠，及該至少一個導電 穿孔包含一具有一填料的第二溝渠，且該填料僅由一包圍一導 電蕊芯之介電襯料組成。 3·如申請專利範圍第2項所述之結構，其中該蕊芯包含⑴鑛、 ⑼銅、（iii)結合鈦、氮化鈦或鈦及氮化鈦的鎢、（iv)結合鋁及氮 化鈕的鎢、（v)結合鈦、氮化鈦及釕中一或多個的銅、或(vi)結 合组、氮化组及釕中一或多個的銅。 i 4. 如申請專利範圍第2項所述之結構，更包括： 一導電間柱接點，在該基板之該頂面處對該至少一個導電 晶圓穿孔；及 一導電背面襯墊，實體接觸且電接觸該至少一個導電晶圓 穿孔’該背面襯墊靠近該基板之該底面。 5. 如申請專利範圍第4項所述之結構，其中該背面襯墊與該至 少一個非導電晶圓穿孔實體接觸。 24 201025437 6.如申請專利範圍第4項所述之結構，更包括：一在該基板之 該底面上的絕緣層、延伸穿過該絕緣層的該至少一個導^晶圓 穿孔及該至少-個非導電晶圓穿孔、在該絕緣層上的該背:概 藝。 7.如申請專概邮4獅述之結構’其巾關柱接點與該導 電為芯一體形成。 © 8·如申請專利範圍第4項所述之結構，更包括： 一組佈線層，形成於該基板之該頂面之上的； 一導電正面襯勢，在該等佈線層之—頂面上，該正面概塾 藉由該組佈線層中的佈線而電連接至該間柱接點。 9. 如申請專利範圍第8項所述之結構，更包括： ①-在該背面襯墊上的焊料凸塊，⑻一在該正面概塾上的 焊料凸塊，（iii)-在該背面襯墊上的第一焊料凸塊及一在該正 & 面襯墊上的第二焊料凸塊。 10. 如申請專利範圍第1項所述之結構，更包括： -或多個裝置’至少局部形成於該基板中； 該-或多個裝置選自由以下組成的群組：場效電晶體、雙 極電aa體、雙極互補金氧半導體石夕鍺（BiCM〇s siGe )電晶體、 二極體、電阻器及電容器。 η. —種方法，其包含： 形成-晶圓穿孔陣列，其中該晶圓穿孔陣列包含至少一個 25 201025437 導電晶圓穿孔及至少一個非導電晶圓穿孔穿孔，通過具有一頂 面及一對置底面的半導體基板，且該晶圓穿孔陣列的每一晶圓 穿孔分別延伸到大於至該基板之該底面的中途及直到該基板 之該底面之間。 ι 12. 如申請專利触第η項所述之方法，其中該至少一個非導 電穿孔包含-僅填充有'絕緣體的溝渠，及該至少—個導電穿
    孔包含一具有一填料的溝渠，且該填料僅由一包圍一導電蕊芯 之介電襯料組成。 ^〜 13. 如申請專利範圍第12項所述之方法，更包括： 形成一至該蕊芯的導電間柱接點； 形成一絕緣層於該基板的該底面上；及 形成一導電背面襯墊於該絕緣層上，該至少一個導電晶圓 穿孔及該至少-個非導電晶圓穿孔延伸穿過舰緣層，該背面 襯塾實體麵及f接觸妓且實體接繼介電襯料及該絕 *Ηβ 〇
    14. 一種方法，其包含： ⑻形成-第-溝渠及一第二溝渠於一半導體基板中，該第 -及該第二溝渠分別自該基板之—頂面_基板之一對置底 面延伸一小於該基板之一厚度的距離； 介電神^全填充該第—賴及形成該 材料之一襯料於該第二溝渠的側壁上； (c)以-導電材料填充該第二溝渠中的剩餘空間；及 (Φ自該基板之該絲薄化該基板以形成絲板的一新底 26 201025437 :基材料及第二溝渠的該襯料及導電材料 14項所述之方法’其梢包括： 渠的該側壁ίΓΓ層於該第—溝渠的侧壁上以及於該第二溝 0 _層以形成該介電材料於該第—溝渠中及形 ❹ ❿ 成—電材料_襯料於該第二溝渠的該側壁上。 如申π專利範_ 14項所述之方法，其中胸摻雜該多晶 hy 〇 π.如申請專利範圍第μ項所述之方法，挪)及⑹之間更包括： W用多晶石夕填充該第二溝渠中的剩餘空間⑼使該多晶石夕 低於該基板的該頂面，㈣用—額外介電材料填充在該多 ί石夕上方的該溝渠及(iv)自該第二溝渠移除鮮晶魏該額外 介電材料。 18.如申請專利範圍第17項所述之方法，在⑽及⑻之間 括： 形成一或多個裝置，至少局部位在該基板中； 形成一層間介電層於該基板的該頂面上； 形成一穿過該層間介電層到達該額外介電材料的第一開 口及形成一穿過該層間介電層到達該一或多個裝置中至少一 個的第二開口；及 其中(c)同時填充該第二溝渠、該第一開口及第二開口。 27 201025437 Utr專她圍第18項所述之方法’其枚-或多個裝置 ，自由以下組成的群組··場效電晶體、雙極電晶體脱麵 SiGe電晶體、二極體、電阻器及電容器。 申明專利範圍第14項所述之方法，在⑻及⑼之間更包括： 形成一組佈線層於該基板的該頂面之上，·及
    形成-導電正面襯該等佈線層的—頂面上該正面概 塾電以該組佈線層中的佈線連接至該間柱接點。 21.如申請專利範圍第20項所述之方法，更包括： (e)形成-導電背面襯塾，實體接觸且電接觸該第二溝渠之 該導電材料’該背Φ缝靠近該基板的該底面。 •如申明專利範圍第21項所述之方法，其中該背面襯塾實體 接觸該第一溝渠的該介電材料。 23. 如申請專利範圍第21項所述之方法，在⑼及⑻之間更包括: 形成一絕緣層於該基板的該底面上，該第一溝渠的該介電 材料延伸穿過·緣層及魏料，及該第二溝渠的該導電材料 延伸穿過該絕緣層，該背面襯墊形成於該絕緣層上。 24. 如申凊專利範圍第21項所述之方法，更包括： ω形成一焊料凸塊於背面襯墊上，（ii)形成一焊料凸塊於該 f面襯墊上，（iii)形成一第一焊料凸塊於背面襯墊上及形成一 弟一焊料凸塊於該正面概塾上。 28 201025437 25·如申請專利範園第14項所述之方法，其中(d)包括： 研磨該基板的該底面以形成該基板的一新底面； 化予姓刻該基板的該新底面以暴露該第一溝渠的該介電 材料及該第二溝渠的該襯料；及 化學機械拋光以暴露該第二溝渠的該導電材料。 26.—種穿過一半導體基板的信號傳輸線，該基板具有一頂面及 ❿ 一對置底面，包含： 一導電晶圓穿孔，其自該基板之該頂面延伸至該基板之該 底面，該導電穿孔的側壁與該基板電絕緣；及 一非導電穿孔，其自該基板之該頂面延伸到大於至該基板 之該底面的中途及直到該基板之該底面之間，該非導電穿孔靠 近該導電晶圓穿孔並以該基板之一區域與該導電晶圓穿孔分 開。 _ 27.如申請專利範圍第26項所述之信號傳輸線，更包括： 一額外非導電穿孔，其從該基板的該頂面延伸到大於至該 基板之該底面的中途及直到該基板之該底面之間，該額外非導 電穿孔布置在該導電穿孔與該非導電穿孔對置的一侧上，該額 外非導電穿孔靠近該導電晶圓穿孔並與該導電晶圓穿孔為該 基板的一額外區域所分開。 28.如申請專利範圍第26項所述之信號傳輸線，更包括： 第一、第二及第三額外非導電穿孔，其從該基板的該頂面 延伸到大於至該基板之該底面的中途及直到該基板之該底面 29 201025437 電穿孔及該第―、第二及第三額外非導電穿孔布 置在該導電穿孔的相應第一、第二、第三及第四侧上，該第一 侧與該第二側對置，該第三侧與該第四侧對置；該第一、第二 及第三額外非導電穿孔與該導電穿孔為該基板的相應第一 二及第三額外區域所分開。 29.如申請專利範圍第26項所述之信號傳輸線，更包括： 一額外導電晶®穿孔’其自該基板之該頂©延伸至該基板 之該底面，該額外導電穿孔的側壁與該基板電絕緣；
    「或多個内部非導電穿孔，其從該基板之該頂面延伸到大 於至該基板之該底面的令途及直到該基板之該底面之間，該一 或多個内部料電穿孔介人在該導電穿孔及該額外導電穿孔 之間，該一或多個内部非導電穿孔在該導電穿孔與該非導電 孔對置的一側上； 一額外非導電穿孔，其從該基板之該頂面延伸到大於至該 基板之該底面的中途及直到該基板之該底面之間，該額外非導 電穿孔布置在該額外導電穿孔與該一或多個内部非導電穿孔 對置的一側上；及 第一及第二外部非導電穿孔，其從該基板之該頂面延伸到 大於至該基板之該底面的中途及直到該基板之該底面之間，該 第一及第二外部非導電穿孔布置在由該導電穿孔、該一或多個 内部非導電穿孔及該額外導電穿孔所組成之一蕊芯群組的不 同側上。 30.如申請專利範圍第26項所述之信號傳輸線，更包括： 第一及第二額外導電晶圓穿孔，其自該基板之該頂面延伸 30 201025437 至該基板之該底面’該額外導電穿孔的侧壁與該基板電絕緣； 第一之一或多個内部非導電穿孔，其從該基板之該頂面延 伸到大於至該基板之該底面的中途及直到該基板之該底面之 間，該第一之一或多個非導電穿孔介入在該導電穿孔及該第一 額外導電穿孔之間，該第一之一或多個内部非導電穿孔在該導 電穿孔與該額外非導電穿孔對置的一側上； 第二之一或多個内部非導電穿孔，其從該基板之該頂面延 伸到大於至該基板之該底面的中途及直到該基板之該底面之 參 間，該第二之一或多個非導電穿孔介入在該第一額外導電穿孔 及該第一額外導電穿孔之間，該第二之一或多個内部非導電穿 孔在該導電穿孔與該額外非導電穿孔對置的一側上； 一額外非導電穿孔’其從該基板之該頂面延伸到大於至該 基板之該底面的中途及直到該基板之該底面之間，該額外非導 電穿孔布置在該第二額外導電穿孔與該第二之一或多個内部 非導電穿孔對置的一侧上；及 第一及第二外部非導電穿孔，其從該基板的該頂面延伸到 珍大於至該基板之該底面的中途及直到該基板之該底面之間，該 第一及第二外部非導電穿孔布置在由該導電穿孔、該第一之一 或多個内部非導電穿孔、該第一額外導電穿孔、該第一之一或 多個内部非導電穿孔、及該額外導電穿孔組成的一蕊芯群組的 不同侧上。 31
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI570804B (zh) * 2014-08-25 2017-02-11 A method of forming a notch at the bottom of the hole during the etching process, and a method of forming the hole

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8166651B2 (en) * 2008-07-29 2012-05-01 International Business Machines Corporation Through wafer vias with dishing correction methods
US8384224B2 (en) * 2008-08-08 2013-02-26 International Business Machines Corporation Through wafer vias and method of making same
US8138036B2 (en) 2008-08-08 2012-03-20 International Business Machines Corporation Through silicon via and method of fabricating same
US8299566B2 (en) * 2008-08-08 2012-10-30 International Business Machines Corporation Through wafer vias and method of making same
US8329578B2 (en) 2009-03-27 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Via structure and via etching process of forming the same
FR2957717B1 (fr) * 2010-03-22 2012-05-04 St Microelectronics Sa Procede de formation d'une structure de type metal-isolant-metal tridimensionnelle
FR2958076B1 (fr) * 2010-03-24 2012-08-17 St Microelectronics Sa Procede de formation de vias electriques
US8541305B2 (en) * 2010-05-24 2013-09-24 Institute of Microelectronics, Chinese Academy of Sciences 3D integrated circuit and method of manufacturing the same
US20110291287A1 (en) * 2010-05-25 2011-12-01 Xilinx, Inc. Through-silicon vias with low parasitic capacitance
US8519542B2 (en) * 2010-08-03 2013-08-27 Xilinx, Inc. Air through-silicon via structure
US9064712B2 (en) 2010-08-12 2015-06-23 Freescale Semiconductor Inc. Monolithic microwave integrated circuit
FR2968129A1 (fr) 2010-11-30 2012-06-01 St Microelectronics Sa Dispositif semi-conducteur comprenant un condensateur et un via de connexion électrique et procédé de fabrication
FR2968130A1 (fr) * 2010-11-30 2012-06-01 St Microelectronics Sa Dispositif semi-conducteur comprenant un condensateur et un via de connexion electrique et procede de fabrication
EP2463896B1 (en) * 2010-12-07 2020-04-15 IMEC vzw Method for forming through-substrate vias surrounded by isolation trenches with an airgap and corresponding device
FR2970120A1 (fr) * 2010-12-31 2012-07-06 St Microelectronics Crolles 2 Via traversant isole
US8643191B2 (en) 2012-01-26 2014-02-04 International Business Machines Corporation On-chip radial cavity power divider/combiner
JP5561190B2 (ja) * 2011-01-31 2014-07-30 富士通株式会社 半導体装置、半導体装置の製造方法及び電子装置
TWI459520B (zh) * 2011-01-31 2014-11-01 Xintec Inc 轉接板及其形成方法
US8975751B2 (en) 2011-04-22 2015-03-10 Tessera, Inc. Vias in porous substrates
US8298944B1 (en) * 2011-06-01 2012-10-30 Texas Instruments Incorporated Warpage control for die with protruding TSV tips during thermo-compressive bonding
KR101828490B1 (ko) 2011-08-30 2018-02-12 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그 제조방법
FR2980917B1 (fr) * 2011-09-30 2013-09-27 St Microelectronics Crolles 2 Procede de realisation d'une liaison traversante electriquement conductrice
JP2013115382A (ja) * 2011-11-30 2013-06-10 Elpida Memory Inc 半導体装置及びその製造方法
US20130313710A1 (en) * 2012-05-22 2013-11-28 Micron Technology, Inc. Semiconductor Constructions and Methods of Forming Semiconductor Constructions
US8816383B2 (en) * 2012-07-06 2014-08-26 Invensas Corporation High performance light emitting diode with vias
US9704829B2 (en) * 2013-03-06 2017-07-11 Win Semiconductor Corp. Stacked structure of semiconductor chips having via holes and metal bumps
US9105701B2 (en) * 2013-06-10 2015-08-11 Micron Technology, Inc. Semiconductor devices having compact footprints
US9666521B2 (en) * 2013-08-08 2017-05-30 Invensas Corporation Ultra high performance interposer
TWI676279B (zh) 2013-10-04 2019-11-01 新力股份有限公司 半導體裝置及固體攝像元件
US9443764B2 (en) 2013-10-11 2016-09-13 GlobalFoundries, Inc. Method of eliminating poor reveal of through silicon vias
US9123738B1 (en) 2014-05-16 2015-09-01 Xilinx, Inc. Transmission line via structure
CN108028280B (zh) * 2015-09-25 2023-04-04 英特尔公司 制作背侧金属的接触部的卷绕源极/漏极方法
JP2016029731A (ja) * 2015-10-02 2016-03-03 セイコーエプソン株式会社 回路基板及びセンサー
US10164358B2 (en) * 2016-09-30 2018-12-25 Western Digital Technologies, Inc. Electrical feed-through and connector configuration
US9887195B1 (en) 2016-10-19 2018-02-06 Raytheon Company Coaxial connector feed-through for multi-level interconnected semiconductor wafers
US10168475B2 (en) 2017-01-18 2019-01-01 Juniper Networks, Inc. Atomic layer deposition bonding for heterogeneous integration of photonics and electronics
CN112164688B (zh) * 2017-07-21 2023-06-13 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
FR3077927B1 (fr) 2018-02-13 2023-02-10 St Microelectronics Crolles 2 Sas Capteur d'images a eclairement par la face arriere
US11246218B2 (en) 2018-03-02 2022-02-08 Intel Corporation Core layer with fully encapsulated co-axial magnetic material around PTH in IC package substrate
KR20200093110A (ko) 2019-01-25 2020-08-05 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR20210002773A (ko) * 2019-06-25 2021-01-11 삼성전자주식회사 3차원 반도체 메모리 장치 및 그 제조 방법
KR20210010180A (ko) 2019-07-19 2021-01-27 삼성전자주식회사 반도체 장치 및 반도체 패키지
CN112951770B (zh) * 2021-04-15 2022-06-10 长鑫存储技术有限公司 存储器的制作方法及存储器
CN113394184B (zh) * 2021-06-09 2022-06-17 武汉新芯集成电路制造有限公司 半导体器件及其制造方法

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4702795A (en) * 1985-05-03 1987-10-27 Texas Instruments Incorporated Trench etch process
US4666556A (en) * 1986-05-12 1987-05-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
US5933748A (en) * 1996-01-22 1999-08-03 United Microelectronics Corp. Shallow trench isolation process
TW363245B (en) * 1997-03-06 1999-07-01 United Microelectronics Corp Manufacturing method of semiconductor component
JP3920399B2 (ja) * 1997-04-25 2007-05-30 株式会社東芝 マルチチップ半導体装置用チップの位置合わせ方法、およびマルチチップ半導体装置の製造方法・製造装置
US5998292A (en) * 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
JP2002043502A (ja) * 2000-07-25 2002-02-08 Toshiba Corp マルチチップ半導体装置、ならびにマルチチップ半導体装置用チップ及びその製造方法
US7271491B1 (en) * 2000-08-31 2007-09-18 Micron Technology, Inc. Carrier for wafer-scale package and wafer-scale package including the carrier
US6406934B1 (en) * 2000-09-05 2002-06-18 Amkor Technology, Inc. Wafer level production of chip size semiconductor packages
JP2002289623A (ja) * 2001-03-28 2002-10-04 Toshiba Corp 半導体装置及びその製造方法
JP3725453B2 (ja) * 2001-07-27 2005-12-14 株式会社東芝 半導体装置
EP1351288B1 (en) * 2002-04-05 2015-10-28 STMicroelectronics Srl Process for manufacturing an insulated interconnection through a body of semiconductor material and corresponding semiconductor device
US6836020B2 (en) * 2003-01-22 2004-12-28 The Board Of Trustees Of The Leland Stanford Junior University Electrical through wafer interconnects
US6841883B1 (en) * 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US6897125B2 (en) * 2003-09-17 2005-05-24 Intel Corporation Methods of forming backside connections on a wafer stack
US7345350B2 (en) * 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
US7005388B1 (en) * 2003-12-04 2006-02-28 National Semiconductor Corporation Method of forming through-the-wafer metal interconnect structures
US7276787B2 (en) * 2003-12-05 2007-10-02 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same
US6943106B1 (en) * 2004-02-20 2005-09-13 Micron Technology, Inc. Methods of fabricating interconnects for semiconductor components including plating solder-wetting material and solder filling
US7005371B2 (en) * 2004-04-29 2006-02-28 International Business Machines Corporation Method of forming suspended transmission line structures in back end of line processing
US20050248002A1 (en) * 2004-05-07 2005-11-10 Michael Newman Fill for large volume vias
JP4568039B2 (ja) * 2004-06-30 2010-10-27 ルネサスエレクトロニクス株式会社 半導体装置およびそれを用いた半導体モジュール
JP2006019455A (ja) * 2004-06-30 2006-01-19 Nec Electronics Corp 半導体装置およびその製造方法
JP2006030660A (ja) * 2004-07-16 2006-02-02 Shinko Electric Ind Co Ltd 基板、半導体装置、基板の製造方法、及び半導体装置の製造方法
TWI250596B (en) * 2004-07-23 2006-03-01 Ind Tech Res Inst Wafer-level chip scale packaging method
JP4365750B2 (ja) * 2004-08-20 2009-11-18 ローム株式会社 半導体チップの製造方法、および半導体装置の製造方法
JP2008511981A (ja) * 2004-09-02 2008-04-17 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ タングステンを用いたコンタクト形成及び深溝分離充填
US7098070B2 (en) * 2004-11-16 2006-08-29 International Business Machines Corporation Device and method for fabricating double-sided SOI wafer scale package with through via connections
JP4795677B2 (ja) * 2004-12-02 2011-10-19 ルネサスエレクトロニクス株式会社 半導体装置およびそれを用いた半導体モジュール、ならびに半導体装置の製造方法
JP4961668B2 (ja) * 2005-01-11 2012-06-27 富士電機株式会社 半導体装置の製造方法
WO2006080337A1 (ja) * 2005-01-31 2006-08-03 Nec Corporation 半導体装置およびその製造方法と、積層型半導体集積回路
US7545045B2 (en) * 2005-03-24 2009-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy via for reducing proximity effect and method of using the same
TW200644165A (en) * 2005-05-04 2006-12-16 Icemos Technology Corp Silicon wafer having through-wafer vias
US7215032B2 (en) * 2005-06-14 2007-05-08 Cubic Wafer, Inc. Triaxial through-chip connection
JP4869664B2 (ja) * 2005-08-26 2012-02-08 本田技研工業株式会社 半導体装置の製造方法
US7488680B2 (en) * 2005-08-30 2009-02-10 International Business Machines Corporation Conductive through via process for electronic device carriers
US7772115B2 (en) * 2005-09-01 2010-08-10 Micron Technology, Inc. Methods for forming through-wafer interconnects, intermediate structures so formed, and devices and systems having at least one solder dam structure
US7563714B2 (en) * 2006-01-13 2009-07-21 International Business Machines Corporation Low resistance and inductance backside through vias and methods of fabricating same
JP2010500766A (ja) * 2006-08-10 2010-01-07 アイスモス・テクノロジー・リミテッド ウエハ貫通ビアを備えたフォトダイオードアレイの製造方法
US7759731B2 (en) * 2006-08-28 2010-07-20 Advanced Analogic Technologies, Inc. Lateral trench MOSFET with direct trench polysilicon contact and method of forming the same
KR100826979B1 (ko) * 2006-09-30 2008-05-02 주식회사 하이닉스반도체 스택 패키지 및 그 제조방법
US7879711B2 (en) * 2006-11-28 2011-02-01 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked structures and methods of fabricating stacked structures
US8030731B2 (en) * 2007-03-28 2011-10-04 Advanced Analogic Technologies, Inc. Isolated rectifier diode
US7965540B2 (en) * 2008-03-26 2011-06-21 International Business Machines Corporation Structure and method for improving storage latch susceptibility to single event upsets
TWI368314B (en) * 2008-04-25 2012-07-11 Nanya Technology Corp Recess channel transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI570804B (zh) * 2014-08-25 2017-02-11 A method of forming a notch at the bottom of the hole during the etching process, and a method of forming the hole

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