TW200516861A - Delay-locked loop circuit - Google Patents

Delay-locked loop circuit

Info

Publication number
TW200516861A
TW200516861A TW093131541A TW93131541A TW200516861A TW 200516861 A TW200516861 A TW 200516861A TW 093131541 A TW093131541 A TW 093131541A TW 93131541 A TW93131541 A TW 93131541A TW 200516861 A TW200516861 A TW 200516861A
Authority
TW
Taiwan
Prior art keywords
signal
tin
generate
receives
coarse lock
Prior art date
Application number
TW093131541A
Other languages
English (en)
Other versions
TWI316331B (en
Inventor
Phil-Jae Jeon
Doh-Young Kim
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200516861A publication Critical patent/TW200516861A/zh
Application granted granted Critical
Publication of TWI316331B publication Critical patent/TWI316331B/zh

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/10Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
TW093131541A 2003-10-31 2004-10-18 Delay-locked loop circuit TWI316331B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020030076990A KR100540930B1 (ko) 2003-10-31 2003-10-31 지연동기루프 회로

Publications (2)

Publication Number Publication Date
TW200516861A true TW200516861A (en) 2005-05-16
TWI316331B TWI316331B (en) 2009-10-21

Family

ID=34545679

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093131541A TWI316331B (en) 2003-10-31 2004-10-18 Delay-locked loop circuit

Country Status (5)

Country Link
US (1) US7084682B2 (zh)
JP (1) JP4322193B2 (zh)
KR (1) KR100540930B1 (zh)
CN (1) CN100530970C (zh)
TW (1) TWI316331B (zh)

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US7355905B2 (en) 2005-07-01 2008-04-08 P.A. Semi, Inc. Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage
KR100682830B1 (ko) 2005-08-10 2007-02-15 삼성전자주식회사 락 검출기 및 이를 구비하는 지연 동기 루프
CN1983815B (zh) * 2005-12-13 2011-06-01 上海华虹Nec电子有限公司 一种延时锁定环电路
KR100715154B1 (ko) * 2005-12-21 2007-05-10 삼성전자주식회사 락킹속도가 향상되는 락킹루프회로 및 이를 이용한클락락킹방법
KR100709474B1 (ko) * 2005-12-21 2007-04-18 주식회사 하이닉스반도체 외부 환경 변화에 무관하게 안정된 내부 클록 신호를발생하는 dll
KR100756136B1 (ko) * 2006-03-23 2007-09-05 엘지전자 주식회사 광대역 주파수 동작범위를 갖는 지연고정루프 회로 및 그위상고정방법
US7336112B1 (en) * 2006-08-21 2008-02-26 Huaya Microelectronics, Ltd. False lock protection in a delay-locked loop (DLL)
KR100807113B1 (ko) * 2006-09-29 2008-02-26 주식회사 하이닉스반도체 반도체 메모리 장치 및 그의 구동방법
US7675332B1 (en) 2007-01-31 2010-03-09 Altera Corporation Fractional delay-locked loops
KR100937716B1 (ko) * 2007-04-30 2010-01-20 고려대학교 산학협력단 지연 고정 루프 기반의 주파수 체배 장치 및 방법
KR100886354B1 (ko) 2007-05-17 2009-03-03 삼성전자주식회사 다중 위상 클럭신호를 사용하는 통신 시스템 및 통신 방법
JP4434253B2 (ja) * 2007-10-16 2010-03-17 ソニー株式会社 クロック信号生成回路、表示パネルモジュール、撮像デバイス及び電子機器
KR100973222B1 (ko) * 2007-12-26 2010-07-30 주식회사 동부하이텍 타이밍 제어를 위한 지연동기 루프 장치
JP2009278528A (ja) * 2008-05-16 2009-11-26 Elpida Memory Inc Dll回路、および半導体装置
US8008954B2 (en) 2008-10-03 2011-08-30 Micron Technology, Inc. Multi-phase signal generator and method
US7911245B2 (en) * 2008-10-03 2011-03-22 Micron Technology, Inc. Multi-phase signal generator and method
US7872924B2 (en) 2008-10-28 2011-01-18 Micron Technology, Inc. Multi-phase duty-cycle corrected clock signal generator and memory having same
US7969219B2 (en) * 2008-11-26 2011-06-28 Texas Instruments Incorporated Wide range delay cell
KR100996175B1 (ko) * 2008-12-26 2010-11-24 주식회사 하이닉스반도체 반도체 장치
JP5588254B2 (ja) * 2009-08-04 2014-09-10 キヤノン株式会社 遅延同期ループ回路
CN101714874B (zh) * 2009-11-11 2012-03-28 钰创科技股份有限公司 具省电功能的延迟锁相回路
IT1397376B1 (it) * 2009-12-30 2013-01-10 St Microelectronics Srl Regolazione di una linea di ritardo programmabile ad anello pseudo-chiuso
US8373470B2 (en) * 2010-10-11 2013-02-12 Apple Inc. Modular programmable delay line blocks for use in a delay locked loop
US8368444B2 (en) * 2010-10-11 2013-02-05 Apple Inc. Delay locked loop including a mechanism for reducing lock time
KR101738875B1 (ko) * 2011-02-16 2017-05-24 삼성디스플레이 주식회사 코오스 로킹 검출기 및 이를 포함하는 지연 로킹 루프
CN102651647B (zh) * 2011-02-23 2015-01-07 联咏科技股份有限公司 延迟锁相回路及时脉信号产生方法
CN102761331B (zh) * 2011-04-27 2014-09-17 智原科技股份有限公司 延迟锁相回路
KR101197462B1 (ko) * 2011-05-31 2012-11-09 주식회사 실리콘웍스 오동기 록 방지 회로, 방지 방법 및 그를 이용한 지연고정루프
CN102571081B (zh) * 2011-12-31 2014-08-13 上海贝岭股份有限公司 一种延迟锁定环电路
CN103312317B (zh) * 2013-06-14 2016-01-20 电子科技大学 快速锁定的延迟锁相环
KR102193681B1 (ko) * 2014-01-28 2020-12-21 삼성전자주식회사 Dll을 이용한 ilpll 회로
US9503104B2 (en) * 2014-06-11 2016-11-22 Texas Instruments Incorporated Low power loss of lock detector
CN105071799A (zh) * 2015-08-21 2015-11-18 东南大学 一种采用新型错误锁定检测电路的延迟锁相环
KR102581085B1 (ko) * 2018-12-24 2023-09-21 에스케이하이닉스 주식회사 딜레이 셀 및 이를 포함하는 딜레이 라인
CN111697965B (zh) * 2019-03-14 2023-03-24 澜起科技股份有限公司 高速相位频率检测器
KR20210081753A (ko) * 2019-12-24 2021-07-02 에스케이하이닉스 주식회사 반도체 장치 및 이의 테스트 방법
US11088696B2 (en) * 2019-12-31 2021-08-10 Texas Instruments Incorporated Charge pump
CN115580138B (zh) * 2022-10-17 2024-02-23 上海川土微电子有限公司 一种高对称性总线传输架构

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US5642082A (en) * 1996-06-20 1997-06-24 Altera Corporation Loop filter level detection circuit and method
JPH11205102A (ja) * 1998-01-13 1999-07-30 Mitsubishi Electric Corp 遅延同期回路
US6326826B1 (en) 1999-05-27 2001-12-04 Silicon Image, Inc. Wide frequency-range delay-locked loop circuit
JP4522623B2 (ja) 2001-09-17 2010-08-11 ルネサスエレクトロニクス株式会社 遅延制御装置
NL1021440C2 (nl) * 2001-09-28 2004-07-15 Samsung Electronics Co Ltd Vertragingsvergrendelde lus met meervoudige fasen.
KR100423012B1 (ko) * 2001-09-28 2004-03-16 주식회사 버카나와이어리스코리아 오(誤)동기 방지 기능을 가진 지연 동기 루프 회로

Also Published As

Publication number Publication date
KR100540930B1 (ko) 2006-01-11
CN1612483A (zh) 2005-05-04
JP2005136964A (ja) 2005-05-26
KR20050041730A (ko) 2005-05-04
JP4322193B2 (ja) 2009-08-26
CN100530970C (zh) 2009-08-19
US7084682B2 (en) 2006-08-01
TWI316331B (en) 2009-10-21
US20050093598A1 (en) 2005-05-05

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees