WO2002091578A3 - Phase-locked loop system - Google Patents

Phase-locked loop system Download PDF

Info

Publication number
WO2002091578A3
WO2002091578A3 PCT/CA2002/000570 CA0200570W WO02091578A3 WO 2002091578 A3 WO2002091578 A3 WO 2002091578A3 CA 0200570 W CA0200570 W CA 0200570W WO 02091578 A3 WO02091578 A3 WO 02091578A3
Authority
WO
WIPO (PCT)
Prior art keywords
phase
pll
loop
applications
phase detection
Prior art date
Application number
PCT/CA2002/000570
Other languages
French (fr)
Other versions
WO2002091578A2 (en
Inventor
Ghartemani Masoud Karimi
Original Assignee
Ghartemani Masoud Karimi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ghartemani Masoud Karimi filed Critical Ghartemani Masoud Karimi
Priority to AU2002252890A priority Critical patent/AU2002252890A1/en
Publication of WO2002091578A2 publication Critical patent/WO2002091578A2/en
Publication of WO2002091578A3 publication Critical patent/WO2002091578A3/en

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A new structure for phase-locked loop (PLL) system is disclosed. As with conventional PLLs, the present invention consists of phase detection, loop filter and voltage-controlled oscillator units. An alternative phase detection structure, inspired by concepts from adaptive filtering and dynamical systems theory, is presented which substantially enhances the performance of the loop in terms of stability and dynamic performance. Presented phase detection scheme obviates the need for sophisticated loop filters, so much so that a first order filter suffices for most applications. In addition to the normal function of a PLL, the present system directly generates estimates of the amplitude, phase and frequency of the input signal. This feature extends the range of applications of the system beyond well-known applications of PLL in various disciplines of electrical engineering.
PCT/CA2002/000570 2001-05-09 2002-04-22 Phase-locked loop system WO2002091578A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002252890A AU2002252890A1 (en) 2001-05-09 2002-04-22 Phase-locked loop system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CA 2346136 CA2346136A1 (en) 2001-05-09 2001-05-09 Enhanced phase-locked loop (pll) system
CA2,346,136 2001-05-09

Publications (2)

Publication Number Publication Date
WO2002091578A2 WO2002091578A2 (en) 2002-11-14
WO2002091578A3 true WO2002091578A3 (en) 2003-04-03

Family

ID=4168962

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2002/000570 WO2002091578A2 (en) 2001-05-09 2002-04-22 Phase-locked loop system

Country Status (3)

Country Link
AU (1) AU2002252890A1 (en)
CA (1) CA2346136A1 (en)
WO (1) WO2002091578A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8090332B2 (en) 2007-12-12 2012-01-03 Qualcomm, Incorporated Tracking filter for a receiver
ITTO20080368A1 (en) * 2008-05-15 2009-11-16 Selex Communications Spa DIGITAL PHASE RING RING
ES2546948T3 (en) * 2008-11-07 2015-09-30 Vestas Wind Systems A/S Electrical network monitoring system and related method
US8868364B2 (en) 2011-04-29 2014-10-21 Analog Devices, Inc. Apparatus and method for real time harmonic spectral analyzer
US8907655B2 (en) 2011-04-29 2014-12-09 Analog Devices, Inc. System and method for detecting a fundamental frequency of an electric power system
EP2940440A1 (en) 2014-04-30 2015-11-04 Bombardier Transportation GmbH Identification of the presence of a potentially damaging resonant vibration state of a mechanical device
CN108418579B (en) * 2018-04-08 2024-02-13 中船重工(武汉)凌久电气有限公司 Output sine wave phase-locking phase-shifting device and sine phase-locking phase-shifting algorithm
CN112152609B (en) * 2020-08-21 2024-05-28 中车株洲电力机车研究所有限公司 Phase-locked loop, method for controlling synchronization of grid voltage information and power electronic device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4495475A (en) * 1982-01-08 1985-01-22 Litton Systems, Inc. Residual mode phase locked loop
EP0645881A1 (en) * 1993-09-29 1995-03-29 STMicroelectronics Limited Demodulation of FM audio carrier

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4495475A (en) * 1982-01-08 1985-01-22 Litton Systems, Inc. Residual mode phase locked loop
EP0645881A1 (en) * 1993-09-29 1995-03-29 STMicroelectronics Limited Demodulation of FM audio carrier

Also Published As

Publication number Publication date
CA2346136A1 (en) 2002-11-09
AU2002252890A1 (en) 2002-11-18
WO2002091578A2 (en) 2002-11-14

Similar Documents

Publication Publication Date Title
TW200701648A (en) Phase and frequency detection circuits
WO2002073806A3 (en) Pll cycle slip compensation
WO2001001577A8 (en) Adjustable bandwidth phase locked loop with fast settling time
WO2002091578A3 (en) Phase-locked loop system
JP2003133950A (en) Voltage controlled oscillator with input changeover switch and pll control oscillator
JP2003133949A5 (en)
KR970055330A (en) AM radio receiver
US6064273A (en) Phase-locked loop having filter with wide and narrow bandwidth modes
WO2021150457A8 (en) Frequency domain-based clock recovery
CN101106556A (en) FM decoding chip, stereo decoding system and method
WO2003019783A3 (en) Phase-locked loop with analog phase rotator
US20070237277A1 (en) Method and Integrated Circuit for Controlling an Oscillator Signal
US5432855A (en) Stereo and dual audio signal identifying system
RU2214043C2 (en) Frequency synthesizer
Telba et al. Simulation technique for noise and timing jitter in phase locked loop
JP2002509684A (en) Phase frequency detector with instantaneous phase difference output
Osa et al. Phase-locked loop design for on-chip tuning applications
JP3712141B2 (en) Phase-locked loop device
JPS5938760Y2 (en) band pass filter
US7298220B2 (en) Method and apparatus for creating a multiple loop VCO
JP2007104132A (en) Active filter in pll circuit
Torkzadeh et al. Analysis of jitter peaking and jitter accumulation in re-circulating delay-locked loops
KR20230055101A (en) Phase locked loop and operation method thereof
RU2222099C1 (en) Synchro-phase demodulator
KR100987072B1 (en) Apparatus and method for improving phase noise of phase locked loop

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG US UZ VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP