IT1397376B1 - Regolazione di una linea di ritardo programmabile ad anello pseudo-chiuso - Google Patents

Regolazione di una linea di ritardo programmabile ad anello pseudo-chiuso

Info

Publication number
IT1397376B1
IT1397376B1 ITMI2009A002358A ITMI20092358A IT1397376B1 IT 1397376 B1 IT1397376 B1 IT 1397376B1 IT MI2009A002358 A ITMI2009A002358 A IT MI2009A002358A IT MI20092358 A ITMI20092358 A IT MI20092358A IT 1397376 B1 IT1397376 B1 IT 1397376B1
Authority
IT
Italy
Prior art keywords
pseudo
adjustment
delay line
closed ring
programmable delay
Prior art date
Application number
ITMI2009A002358A
Other languages
English (en)
Inventor
Sandre Guido De
Luca Bettini
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to ITMI2009A002358A priority Critical patent/IT1397376B1/it
Priority to US12/977,093 priority patent/US8278986B2/en
Publication of ITMI20092358A1 publication Critical patent/ITMI20092358A1/it
Application granted granted Critical
Publication of IT1397376B1 publication Critical patent/IT1397376B1/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H03K2005/00071—Variable delay controlled by a digital setting by adding capacitance as a load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00084—Fixed delay by trimming or adjusting the delay
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00097—Avoiding variations of delay using feedback, e.g. controlled by a PLL
    • H03K2005/00104—Avoiding variations of delay using feedback, e.g. controlled by a PLL using a reference signal, e.g. a reference clock
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00123—Avoiding variations of delay due to integration tolerances
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00143—Avoiding variations of delay due to temperature

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
ITMI2009A002358A 2009-12-30 2009-12-30 Regolazione di una linea di ritardo programmabile ad anello pseudo-chiuso IT1397376B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
ITMI2009A002358A IT1397376B1 (it) 2009-12-30 2009-12-30 Regolazione di una linea di ritardo programmabile ad anello pseudo-chiuso
US12/977,093 US8278986B2 (en) 2009-12-30 2010-12-23 Trimming of a pseudo-closed loop programmable delay line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITMI2009A002358A IT1397376B1 (it) 2009-12-30 2009-12-30 Regolazione di una linea di ritardo programmabile ad anello pseudo-chiuso

Publications (2)

Publication Number Publication Date
ITMI20092358A1 ITMI20092358A1 (it) 2011-06-30
IT1397376B1 true IT1397376B1 (it) 2013-01-10

Family

ID=43726143

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI2009A002358A IT1397376B1 (it) 2009-12-30 2009-12-30 Regolazione di una linea di ritardo programmabile ad anello pseudo-chiuso

Country Status (2)

Country Link
US (1) US8278986B2 (it)
IT (1) IT1397376B1 (it)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8386829B2 (en) 2009-06-17 2013-02-26 Macronix International Co., Ltd. Automatic internal trimming calibration method to compensate process variation
US9312022B1 (en) * 2015-01-06 2016-04-12 Micron Technology, Inc. Memory timing self-calibration
KR20190073796A (ko) * 2017-12-19 2019-06-27 삼성전자주식회사 지연 제어 회로
US10840895B1 (en) * 2019-09-06 2020-11-17 International Business Machines Corporation Fine-grained programmable delay and pulse shaping circuit
EP3998705B1 (en) * 2020-09-18 2024-07-10 Changxin Memory Technologies, Inc. Delay circuit and delay structure
CN114204919A (zh) * 2020-09-18 2022-03-18 长鑫存储技术有限公司 延时电路和延时结构
CN115549655A (zh) * 2021-06-29 2022-12-30 澜起电子科技(昆山)有限公司 延迟装置及延迟控制方法
CN114374377A (zh) * 2022-01-11 2022-04-19 长鑫存储技术有限公司 延时电路

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5336940A (en) * 1992-08-07 1994-08-09 Vlsi Technology, Inc. Delay-compensated output pad for an integrated circuit and method therefor
US5650739A (en) * 1992-12-07 1997-07-22 Dallas Semiconductor Corporation Programmable delay lines
US6229364B1 (en) * 1999-03-23 2001-05-08 Infineon Technologies North America Corp. Frequency range trimming for a delay line
US6748549B1 (en) * 2000-06-26 2004-06-08 Intel Corporation Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock
US7026850B2 (en) * 2001-05-21 2006-04-11 Acuid Corporation Limited Programmable self-calibrating vernier and method
US20030179842A1 (en) * 2002-03-22 2003-09-25 Kane Michael G. Digital pattern sequence generator
KR100540930B1 (ko) * 2003-10-31 2006-01-11 삼성전자주식회사 지연동기루프 회로
US7034589B2 (en) * 2004-02-26 2006-04-25 Silicon Integrated Systems Corp. Multi-stage delay clock generator
US7336112B1 (en) * 2006-08-21 2008-02-26 Huaya Microelectronics, Ltd. False lock protection in a delay-locked loop (DLL)
US8219343B2 (en) * 2008-04-24 2012-07-10 Realtek Semiconductor Corp. Method and apparatus for calibrating a delay chain
US7872494B2 (en) * 2009-06-12 2011-01-18 Freescale Semiconductor, Inc. Memory controller calibration

Also Published As

Publication number Publication date
US20110156785A1 (en) 2011-06-30
US8278986B2 (en) 2012-10-02
ITMI20092358A1 (it) 2011-06-30

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