TW200402133A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- TW200402133A TW200402133A TW092114249A TW92114249A TW200402133A TW 200402133 A TW200402133 A TW 200402133A TW 092114249 A TW092114249 A TW 092114249A TW 92114249 A TW92114249 A TW 92114249A TW 200402133 A TW200402133 A TW 200402133A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
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- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
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- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002219909A JP2004063767A (ja) | 2002-07-29 | 2002-07-29 | 半導体装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW200402133A true TW200402133A (en) | 2004-02-01 |
Family
ID=30437667
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW092114249A TW200402133A (en) | 2002-07-29 | 2003-05-27 | Semiconductor device |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6841870B2 (enExample) |
| JP (1) | JP2004063767A (enExample) |
| KR (1) | KR20040011348A (enExample) |
| CN (1) | CN1472808A (enExample) |
| DE (1) | DE10324598A1 (enExample) |
| TW (1) | TW200402133A (enExample) |
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| TWI225291B (en) * | 2003-03-25 | 2004-12-11 | Advanced Semiconductor Eng | Multi-chips module and manufacturing method thereof |
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| KR100587081B1 (ko) * | 2004-06-30 | 2006-06-08 | 주식회사 하이닉스반도체 | 개선된 열방출 특성을 갖는 반도체 패키지 |
| KR100593703B1 (ko) * | 2004-12-10 | 2006-06-30 | 삼성전자주식회사 | 돌출부 와이어 본딩 구조 보강용 더미 칩을 포함하는반도체 칩 적층 패키지 |
| US20060202317A1 (en) * | 2005-03-14 | 2006-09-14 | Farid Barakat | Method for MCP packaging for balanced performance |
| KR101141707B1 (ko) * | 2006-02-24 | 2012-05-04 | 삼성테크윈 주식회사 | 반도체 패키지 및 그 제조 방법 |
| KR100780691B1 (ko) * | 2006-03-29 | 2007-11-30 | 주식회사 하이닉스반도체 | 폴딩 칩 플래나 스택 패키지 |
| KR100766502B1 (ko) * | 2006-11-09 | 2007-10-15 | 삼성전자주식회사 | 반도체 소자 패키지 |
| KR100851108B1 (ko) * | 2007-01-22 | 2008-08-08 | 주식회사 네패스 | 웨이퍼 레벨 시스템 인 패키지 및 그 제조 방법 |
| KR100885918B1 (ko) * | 2007-04-19 | 2009-02-26 | 삼성전자주식회사 | 반도체 디바이스 스택 패키지, 이를 이용한 전기장치 및 그패키지의 제조방법 |
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| US8102666B2 (en) * | 2008-08-19 | 2012-01-24 | Stats Chippac Ltd. | Integrated circuit package system |
| US7691674B1 (en) * | 2009-06-20 | 2010-04-06 | Stats Chippac Ltd. | Integrated circuit packaging system with stacked device and method of manufacturing thereof |
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| US8952516B2 (en) | 2011-04-21 | 2015-02-10 | Tessera, Inc. | Multiple die stacking for two or more die |
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| US8304881B1 (en) | 2011-04-21 | 2012-11-06 | Tessera, Inc. | Flip-chip, face-up and face-down wirebond combination package |
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| US8841765B2 (en) * | 2011-04-22 | 2014-09-23 | Tessera, Inc. | Multi-chip module with stacked face-down connected dies |
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| JP5887414B2 (ja) | 2011-10-03 | 2016-03-16 | インヴェンサス・コーポレイション | 平行な窓を有するマルチダイのワイヤボンドアセンブリのスタブ最小化 |
| EP2766928A1 (en) | 2011-10-03 | 2014-08-20 | Invensas Corporation | Stub minimization with terminal grids offset from center of package |
| TWI501254B (zh) | 2011-10-03 | 2015-09-21 | 英帆薩斯公司 | 用於具有正交窗之多晶粒導線結合總成之短線最小化 |
| US8659143B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization for wirebond assemblies without windows |
| US8436477B2 (en) | 2011-10-03 | 2013-05-07 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate |
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| JP2015523742A (ja) * | 2012-08-02 | 2015-08-13 | テッセラ,インコーポレイテッド | 2以上のダイにおける複数ダイ・フェースダウン・スタッキング |
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| KR102190382B1 (ko) * | 2012-12-20 | 2020-12-11 | 삼성전자주식회사 | 반도체 패키지 |
| US9123600B2 (en) * | 2013-02-27 | 2015-09-01 | Invensas Corporation | Microelectronic package with consolidated chip structures |
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| US9123555B2 (en) | 2013-10-25 | 2015-09-01 | Invensas Corporation | Co-support for XFD packaging |
| US9281296B2 (en) | 2014-07-31 | 2016-03-08 | Invensas Corporation | Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design |
| US10453785B2 (en) * | 2014-08-07 | 2019-10-22 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming double-sided fan-out wafer level package |
| US9691437B2 (en) | 2014-09-25 | 2017-06-27 | Invensas Corporation | Compact microelectronic assembly having reduced spacing between controller and memory packages |
| US9484080B1 (en) | 2015-11-09 | 2016-11-01 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
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| KR200485491Y1 (ko) | 2017-03-30 | 2018-01-16 | 오승아 | 학습용 간이 정수장치 |
| KR20180130043A (ko) * | 2017-05-25 | 2018-12-06 | 에스케이하이닉스 주식회사 | 칩 스택들을 가지는 반도체 패키지 |
| KR102647423B1 (ko) * | 2019-03-04 | 2024-03-14 | 에스케이하이닉스 주식회사 | 와이어 본딩 연결 구조를 가지는 반도체 패키지 및 이를 포함하는 반도체 패키지 구조물 |
| CN117577634A (zh) * | 2022-08-08 | 2024-02-20 | 长鑫存储技术有限公司 | 三维堆叠封装结构及其形成方法 |
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| KR0177395B1 (ko) | 1995-04-27 | 1999-05-15 | 문정환 | 반도체소자를 칩 상태로 장착시켜서 된 전자회로 보드 및 그 제조방법 |
| JP2000349228A (ja) | 1999-06-09 | 2000-12-15 | Hitachi Ltd | 積層型半導体パッケージ |
| TW415056B (en) * | 1999-08-05 | 2000-12-11 | Siliconware Precision Industries Co Ltd | Multi-chip packaging structure |
| US6265763B1 (en) * | 2000-03-14 | 2001-07-24 | Siliconware Precision Industries Co., Ltd. | Multi-chip integrated circuit package structure for central pad chip |
-
2002
- 2002-07-29 JP JP2002219909A patent/JP2004063767A/ja active Pending
-
2003
- 2003-03-07 US US10/382,497 patent/US6841870B2/en not_active Expired - Lifetime
- 2003-05-27 KR KR1020030033615A patent/KR20040011348A/ko not_active Ceased
- 2003-05-27 TW TW092114249A patent/TW200402133A/zh unknown
- 2003-05-29 CN CNA031381928A patent/CN1472808A/zh active Pending
- 2003-05-30 DE DE10324598A patent/DE10324598A1/de not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| KR20040011348A (ko) | 2004-02-05 |
| DE10324598A1 (de) | 2004-02-26 |
| CN1472808A (zh) | 2004-02-04 |
| US20040016999A1 (en) | 2004-01-29 |
| JP2004063767A (ja) | 2004-02-26 |
| US6841870B2 (en) | 2005-01-11 |
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