CN1472808A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN1472808A
CN1472808A CNA031381928A CN03138192A CN1472808A CN 1472808 A CN1472808 A CN 1472808A CN A031381928 A CNA031381928 A CN A031381928A CN 03138192 A CN03138192 A CN 03138192A CN 1472808 A CN1472808 A CN 1472808A
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China
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mentioned
semiconductor chip
substrate
peristome
conductive pattern
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CNA031381928A
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English (en)
Inventor
���ǻ���
三角和幸
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication of CN1472808A publication Critical patent/CN1472808A/zh
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Abstract

提高BOC结构多芯片组件的可信度，同时提供一种小型高密度的组件。包括：第一导电图案，设在基片4的一个面上；第二导电图案，设在基片4的另一个面上；至少两个第一半导体芯片2、3，安装在基片4的一个面上，并连接在第一导电图案上；第二半导体芯片1，安装在相邻的第一半导体芯片2、3上，并横跨在上面；以及第一配线，穿过相邻的第一半导体芯片2、3之间及基片4的开口部4a，一端连接在第二半导体芯片1的与基片4对置的面上，另一端连接在第二导电图案上。

Description

半导体装置
发明领域
本发明涉及半导体装置，尤其涉及在基片上安装多个半导体芯片的半导体装置。
现有技术
作为高速DRAM等的组件，有一种BOC(板载芯片)结构的组件被人们所知。图15是BOC结构组件的剖面略图。在BOC结构组件中使用中央设有开口部101a的基片101。半导体芯片102的倒置联结在基片101上，使得基片101的中心联结点102a与开口部101a的位置对应。半导体芯片102与基片101通过金丝103进行电连接，金丝103穿过开口部101a，引线接合在中心联结点102a与基片101背面的引脚101b上。
图16示出图15的组件用树脂密封之前从底部看开口部101a的周边平面图。从中心联结点102a引出的金丝103连接在基片101的引脚101b上，引脚101b连接在图15所示的设有球形凸粒104的图案等上。然后如图15所示，用密封树脂105将半导体芯片102的背面和开口部101a的周边密封。
图17表示基片型组件的剖面略图。在基片型组件中，中心联结点102a朝上，半导体芯片102联结在基片101上。而且，与中心联结点相连接的金线103在半导体芯片102的上面引出，连接到位于半导体芯片102外侧的基片101上的联结引脚上。
图18是使用BOC结构的多芯片组件的截面图。该多芯片组件的结构是将图17所示的半导体芯片102联结在图15所示的半导体芯片102上，并将两个设有中心联结点102a的半导体芯片102倒置粘接联结在一起。如图18所示，上方半导体芯片102的中心联结点102a通过金丝103连接在基片101的上面。另外，连接在下方半导体芯片102的中心联结点102a上的金丝103穿过开口部101a后连接在基片101的下面。
可是，在图18所示的多芯片结构中，由于重叠了两个半导体芯片102，上方半导体芯片102的中心联结点102a的位置变高，所以若要将中心联结点102a与基片101连接，金丝103需要足够长。由于金丝103只由两端的引线接合部分支撑，所以全长如果变长，引线接合的中间容易坍塌(金丝流动)。因此，有时会产生相邻金丝103之间的短路或金丝103与半导体芯片102边缘之间的短路。
另外，因为连接下方半导体芯片102的金丝103的引线长度比连接上方半导体芯片102的金丝103长，所以尤其是在高速工作时上方半导体芯片102与下方半导体芯片102之间相互产生的信号时序差很明显。因此，器件工作的可信度受到了影响。
本发明的目的是解决上述问题，提高BOC结构多芯片组件的可信度，同时提供一种小型高密度的组件。
发明内容
本发明的半导体装置是在基片上安装了多个半导体芯片的半导体装置，包括：第一导电图案，设在上述基片的一个面上；第二导电图案，设在上述基片的另一个面上；至少两个第一半导体芯片，安装在上述基片的一个面上，连接在上述第一导电图案上；第二半导体芯片，安装在相邻的上述第一半导体芯片上并横跨在上面；以及第一配线，穿过相邻的上述第一半导体芯片之间及设在上述基片上的开口部，一端连接在上述第二半导体芯片的与上述基片对置的面上，另一端连接在上述第二导电图案上。
另外，还具有多个第一联结点，设在上述第二半导体芯片的与上述基片对置的面上，分别连接在多条上述第一配线上。上述开口部沿着相邻的上述第一半导体芯片之间的缝隙延伸，多个上述第一联结点沿着上述开口部延伸的方向配置。
另外，多个上述第一联结点沿着上述第二半导体芯片的中心线配置。
另外，具有将上述第一半导体芯片与上述第一导电图案电连接的第二配线。
此外，将连接有多个上述第2配线的多个联结点设置在上述第1半导体芯片表面的周边。
另外，在上述基片的上述第二配线与上述第一导电图案的连接部附近，设有将上述第一导电图案与上述第二导电图案连接的通孔。
另外，具有凸粒，设在上述第一半导体芯片与上述第二半导体芯片之间，将上述第一半导体芯片与上述第二半导体芯片电连接。
另外，上述第二半导体芯片具有在多个上述第一联结点的两侧按一定间隔配置的多个第二联结点，上述第一半导体芯片是将与上述第二半导体芯片相同的芯片沿着上述第一联结点与上述第二联结点之间的交界分割后获得的。
另外，具有穿过上述开口部，一端连接在上述第一半导体芯片，另一端连接在上述第二导电图案上的第三配线。
另外，上述第一半导体芯片的连接多个上述第三配线的多个上述第二联结点，设在该芯片表面的周边。
另外，在上述第一半导体芯片与上述基片的一个面之间具有将上述第一半导体芯片与上述第一导电图案电连接的凸粒。
另外，具有由上述第二导电图案构成的分别连接在多个上述第一配线上的多个用于联结的图案、以及至少与上述多个用于联结的图案中的两个连接的第三配线。
另外，上述第三配线至少连接在两个隔着上述开口部对置的上述用于联结的图案上。
另外，具有：多个用于联结的图案，由上述第二导电图案构成，分别连接在多个上述第一配线上；连接图案，由上述第二导电图案构成，至少与上述多个用于联结的图案中的两个连接；上述连接图案设在上述用于联结的图案与上述开口部的边缘之间。
另外，具有：多个用于联结的图案，由上述第二导电图案构成，分别连接在多个上述第一配线上；多个导电珠，固定在上述第二导电图案上，沿着上述开口部配置；上述用于联结的图案形成在上述多个导电珠的配置区域与上述开口部的边缘之间的区域内，1个或多个上述用于联结的图案位于上述开口部的延伸方向上的相邻的两个上述珠之间。
另外，具有：密封树脂，充填相邻的上述第一半导体芯片之间及上述开口部，以宽于上述开口部的宽度形成在上述另一个面上，覆盖上述用于联结的图案。接近上述导电珠部分的上述密封树脂的宽度比覆盖上述用于联结的图案部分的宽度窄。
另外，上述接近导电珠部分的上述密封树脂的宽度比上述覆盖用于联结的图案部分的宽度窄0.2mm以上。
另外，至少一个上述第一半导体芯片是假芯片。
另外，本发明的半导体装置是在基片上安装了半导体芯片的半导体装置，包括：导电图案，设在上述基片的一个面上；半导体芯片，安装在上述基片的另一个面上；第一配线，穿过设在上述基片上的开口部，一端连接在上述半导体芯片的与上述基片对置的面上，另一端连接在上述导电图案上；多个用于联结的图案，由上述导电图案构成，分别连接在多个上述第一配线上；以及第二配线，与上述多个用于联结的图案中的至少两个连接。
另外，上述第二配线至少连接在两个隔着上述开口部对置的上述用于联结的图案上。
另外，本发明的半导体装置是在基片上安装了半导体芯片的半导体装置，包括：导电图案，设在上述基片的一个面上；半导体芯片，安装在上述基片的另一个面上；配线，穿过设在上述基片上的开口部，一端连接在上述半导体芯片的与上述基片对置的面上，另一端连接在上述导电图案上；多个用于联结的图案，由上述导电图案构成，分别连接在多个上述配线上；以及连接图案，由上述导电图案构成，至少与上述多个用于联结的图案中的两个连接；上述连接图案设在上述用于联结的图案与上述开口部的边缘之间。
另外，本发明的半导体装置是在基片上安装了半导体芯片的半导体装置，包括：导电图案，设在上述基片的一个面上；半导体芯片，安装在上述基片的另一个面上；配线，穿过设在上述基片上的开口部，一端连接在上述半导体芯片的与上述基片对置的面上，另一端连接在上述导电图案上；多个用于联结的图案，由上述第二导电图案构成，分别连接在多个上述配线上；以及多个导电珠，固定在上述导电图案上，沿着上述开口部配置；上述用于联结的图案形成在上述多个导电珠的配置区域与上述开口部边缘之间的区域上，一个或多个上述用于联结的图案位于上述开口部的延伸方向上的相邻的两个上述珠之间。
另外，具有：密封树脂，充填上述开口部，以宽于上述开口部的宽度形成在上述另一个面上，覆盖上述用于联结的图案。接近上述导电珠部分的上述密封树脂的宽度比覆盖上述用于联结的图案部分的宽度窄。
另外，上述接近导电珠部分的上述密封树脂的宽度比上述覆盖用于联结的图案部分的宽度窄0.2mm以上。
附图说明
图1是本发明实施方案1的半导体装置的剖面略图；
图2是本发明实施方案1的变形例1的剖面略图；
图3是本发明实施方案1的变形例2的剖面略图；
图4是本发明实施方案1的变形例3的剖面略图；
图5是本发明实施方案1的变形例4的剖面略图；
图6是本发明实施方案1的变形例5的剖面略图；
图7是本发明实施方案2的半导体芯片的平面图；
图8是表示图7的半导体芯片与切割后获得的半导体芯片的配置状态的简化图；
图9是表示图7的半导体芯片与利用切割半导体芯片后获得的半导体芯片构成的BOC结构多芯片组件的剖面略图；
图10是表示图7的半导体芯片与利用切割半导体芯片后获得的半导体芯片构成的BOC结构多芯片组件的剖面略图；
图11是对应于基片开口部宽度的密封树脂与导电珠的位置关系的简化图；
图12是对应于基片开口部宽度的密封树脂与导电珠的位置关系的模型图；
图13是实施方案3的半导体装置的基片开口部附近的放大平面图；
图14是实施方案3的半导体装置的基片4的下面的平面图；
图15是以往的BOC结构组件的剖面略图；
图16是将基片开口部周边详细表示的平面图；
图17是基片类型组件的剖面略图；
图18是以往的利用BOC结构的多芯片组件的模型图。
发明的实施方案
下面根据附图详细说明若干个实施方案。本发明不局限于以下的实施方案：
实施方案1
图1是本发明实施方案1的半导体装置的剖面略图。该半导体装置由BOC结构的多芯片组件构成，具有半导体芯片1、半导体芯片2、半导体芯片3，以及基片4。基片4是在上下两面上形成了指定的导电图案的配线基片，半导体芯片1、2、3与配置在基片4上的导电图案电连接。
基片4的中央附近设有开口部4a，半导体芯片2及半导体芯片3分别配置在开口部4a的两侧。半导体芯片1、2、3都为中心脚联结点规格的芯片。半导体芯片2、3联结在基片4上，其形成了用作电极的中心联结点2a、3a的芯片表面朝上。半导体芯片1联结在半导体芯片2、3上，其中心联结点1a朝下配置且位于开口部4a上。基片4的下面固定了用于安装的导电珠7。
半导体芯片2、3的中心联结点2a、3a由金丝5以引线接合的方式连接在基片4的上面的联结引脚上。半导体芯片1的中心联结点1a由金丝6通过引线接合连接在基片4的下面的联结引脚上。金丝6从中心联结点1a穿过半导体芯片2和半导体芯片3之间，再穿过开口部4到达基片4的下面的联结引脚上。
基片4上的半导体芯片1、2、3由密封树脂8密封。基片4的下面由密封树脂9密封，半导体芯片2与半导体芯片3之间以及开口部4a充填了密封树脂9。另外，基片4的下面的联结引脚和金丝6也被密封树脂9覆盖。
连接半导体芯片1和基片4的联结引脚时，将半导体芯片1联结在半导体芯片2、3的上面后将基片4上下颠倒，利用金丝6将半导体芯片1的中心联结点1a与基片4引线接合。
如此，在开口部4a的两侧配置半导体芯片2和半导体芯片3，将金丝穿过半导体芯片2与半导体芯片3之间和开口部4a，可以最大限度地缩短金丝6的配线长度。由此，金丝6两端引线接合部的距离变短，可以稳固地支撑金丝6，从而可以抑制引线接合部之间产生金丝6的坍塌(金丝流动)。因此，可以抑制相邻的金丝6之间的短路以及金丝6与半导体芯片2、3的边缘之间的短路，提高半导体装置的可信度。
另外，缩短从半导体芯片1到基片4的配线的引线有利于芯片的高速工作。另外，因为可以使金丝6与金丝5的长度相同，所以可以抑制半导体芯片1与半导体芯片2、3之间产生信号的时序差。
另外，因为不用将金丝引到半导体芯片1的外侧，所以可以缩小半导体芯片1的外侧空间。因此，可以构成小型高密度的BOC结构多芯片组件。
另外，在图1中示出了在基片4上安装了两个半导体芯片2、3的例子，但也可以将3个以上的半导体芯片排列配置在基片4上。同样，虽然在图1中的半导体芯片2、3上安装了一个半导体芯片1，但也可以在半导体芯片2、3上安装两个以上的半导体芯片。
变形例1
图2是实施方案1的变形例的剖面略图。在变形例1中，将图1所示的半导体芯片2、3换成了设有周边联结点2b、3b式样的半导体芯片。通过将半导体芯片2、3换成周边联结点式样的芯片，可以使用除了高速DRAM以外的微型计算机及其他各种半导体芯片，从而可以提高半导体装置结构的自由度。此时，如图2所示，可以在基片4a的周边设置通孔4b，在基片4的背面设置追加的导电珠7，通过通孔4b将导电珠7与连接金丝5的联结引脚直接连接。由此，可以通过追加的导电珠7使半导体芯片2、3的输入和输出独立，还可以缩短从基片4的背面到半导体芯片2、3的配线路径。
变形例2
图3是本发明实施方案1的变形例2的剖面略图。在变形例2中，利用凸粒10将半导体芯片1和半导体芯片2、3电连接。在半导体芯片1的下面设有用于连接凸粒的周边联结点(在图3中未示出)，通过凸粒10将半导体芯片2、3的中心联结点与半导体芯片1的用于连接凸粒的联结点连接。
在变形例2中，因为不需设置图1中的金丝5，所以可以消除金丝坍塌、金丝流动等的产生因素。另外，不需要在基片4的上面设置用于连接金丝的配线图案。由此，可以进一步减少半导体芯片1、2、3之间的工作速度差，抑制给各半导体芯片的信号产生时序差。另外，在图3中的半导体芯片2、3是中心联结点式样的芯片，但也可以是中心联结点式样以外的芯片。
变形例3
图4(a)和图4(b)是实施方案1的变形例3的剖面略图。在变形例3中，至少将半导体芯片2、3中的一个换成了实际上不进行工作的假芯片11。
在图4(a)中，将图1所示的实施方案1的半导体芯片3换成了假芯片11。在图4(b)中，将图2所示的变形例1的半导体芯片3换成了假芯片11。
根据变形例3的器件结构，即使在半导体芯片1的下方不需要配置两个半导体芯片时，也可以通过配置假的半导体芯片来支撑支撑半导体芯片1的下部。因此，可以不受器件结构上的限制，实现实施方案1的结构。
变形例4
图5是实施方案1的变形例4的剖面略图。图5是将图1所示半导体装置基片4的开口部4a的周边详细示出的平面图，是用树脂将组件密封前的仰视图。如图5所示，从中心联结点1a引出的金丝6连接在基片4的联结引脚4b上，联结引脚4b连接在配置了导电珠7的图案等上。在该结构的变形例4中，利用金丝11以引线接合方式将隔着开口部4a对置的联结引脚4b之间连接起来。由此，可以提高基片4的配线引线的自由度，即使在基片4上设有开口部4a时也能在基片4上设置所需的配线路径。另外，可以使导电珠7的连接外部的配线引线容易进行。
变形例5
图6是实施方案1的变形例5的剖面略图。图6与图5一样，也是表示图1所示半导体装置基片4的开口部4a周边的平面图，是用树脂密封组件前的仰视图。另外，在变形例5中，利用金丝12以引线接合方式将排列配置的指定的联结引脚4b之间连接。在变形例5中，即使由于空间问题而很难进行基片4的配线引线时，也可以提高配线引线的自由度，通过金丝12以引线接合方式在基片4上设置所需的配线路径。
变形例6
图6表示上述变形例5的同时也表示变形例6。在变形例6中，利用开口部4a与联结引脚4b之间的空间形成了连接图案4c，利用连接图案4c将指定的联结引脚4b之间连接起来。在变形例6中，即使由于空间等问题很难进行基片4的配线引线时，也可以通过形成连接图案4c，在基片4上设置所需的配线路径。
另外，上述变形例4～6即使用于图15所示的通常BOC结构的芯片上，也能够提高配线引线的自由度。
实施方案2
下面根据图7～图10说明本发明的实施方案2。在实施方案2中，可以利用同一工艺制造实施方案1中的半导体芯片1、2、3。
图7是半导体芯片1的平面图。半导体芯片1是在中央形成了中心联结点1a的DRAM等大容量芯片，图中示出的是512兆位(MB)的芯片。将半导体芯片1沿图7所示的两条点划线Y切割，即可分割成两个半导体芯片。分割后的一方成为实施方案1中的半导体芯片2，另一方成为半导体芯片3。分割后半导体芯片2和半导体芯片3的容量同为256兆位。另外，半导体芯片1的容量为1千兆(GB)时，分割后半导体芯片2和半导体芯片3的容量同为512兆位。为了在分割后能够作为单体来使用，在形成晶片的阶段就在半导体芯片1的中心联结点1a的两侧和外边缘的一部分设置了联结点1b。切割后联结点1b成为图2所示的周边联结点2b、3b。
图8是表示图7所示的半导体芯片1和通过切割获得的半导体芯片2、3的配置状态模型图。如图所示，因为通过切割获得的半导体芯片2、3的大小约为半导体芯片1的一半，所以在半导体芯片2、3的平面区域上可以正好配置半导体芯片1。
图9及图10是利用图8所示半导体芯片1、2、3构成的BOC结构多芯片组件的剖面略图。如图9及图10所示，半导体芯片2、3联结在了基片4上的开口部4a的两侧，半导体芯片1联结在了半导体芯片2、3上。在图9中，由于半导体芯片2、3的周边联结点与基片4通过凸粒13连接，可以缩短配线路径，因此适用于高速工作的器件上。另外，在图10中，半导体芯片2、3的周边联结点2b、3b与基片4的下面通过金丝14电连接。
根据实施方案2可以利用同一晶片工艺制造半导体芯片1、半导体芯片2以及半导体芯片3。所以可以大幅度地降低半导体装置的制造成本。
实施方案3
下面根据图11～图14说明本发明实施方案3。在实施方案3中，即使实施方案1所述半导体装置的基片4的开口部4a的宽度变宽，也可以利用传递模完好地形成密封树脂9。
在有的半导体装置结构中，由于电路结构及其它因素需要加宽基片4的开口部4a的宽度。另一方面，由于配置在基片4背面的导电珠7的位置受基片4背面的图案配置和与其连接部件的联结点位置等制约，即使加宽开口部4a的宽度有时也不能变更导电珠7的位置。此时，开口部4a的宽度有时会对密封树脂9的密封产生制约。
首先根据图11及图12说明加宽开口部4a宽度时密封树脂9与导电珠7的位置关系。在此，图11(a)及图12(a)是表示半导体装置的下面的平面图，图11(b)是图11(a)的沿I-I’线的剖面图，图12(b)是图12(a)的沿I-I’线的剖面图。图11所示的是开口部4a的宽度充分窄时的情形。此时，由于开口部4a的边缘与沿开口部4a配置的导电珠7之间存在充分的空间，如图11(b)所示，在用树脂密封时可以充分获得成形模具15与基片4的接触区域(模具的压料L)。因此，可以向成形模具15与基片4之间的空间16注入密封树脂9将联结引脚4b完好地密封。
图12是表示加宽开口部4a的宽度使开口部4a的边缘接近导电珠7的情形。此时，由于开口部4a与导电珠7之间的空间变小，联结引脚4b与导电珠7接近，使模具的压料L不足。
根据实施方案3，即使是图12所示的情形，也可以将联结引脚4b相对于导电珠7配置在恰当的位置，来获得模具的压料L。
图13是在实施方案3所涉及半导体装置的基片4的开口部4a附近的放大平面图，表示用密封树脂密封前的状态。如图13所示，导电珠7沿开口部4a的边缘配置，联结引脚4b配置在导电珠7的排列区域与开口部4a的边缘之间。多个联结引脚4b配置在沿开口部4a的边缘方向的相邻导电珠7之间。
由此可以在导电珠7与联结引脚4b之间设置充足的空间，并在该空间上获得模具的压料L。此时，如图13的阴影线部分所示，模具压料L的区域为将导电珠与联结引脚4b之间曲折的区域。然后通过将成形模具15接在模具压料L上，将密封树脂9充填在比模具压料L更接近开口部4a的区域M中。
图14是实施方案3的半导体装置的模型图，是基片4的下面的平面图。如图13所示，由于设定了模具压料L的区域，使形成的密封树脂9的宽度在接近导电珠7的位置和覆盖联结引脚4b的位置不同。此时，在形成密封树脂9时，最好使在覆盖联结引脚4b的位置的宽度D1与接近导电珠7的位置的宽度D2之差在0.2mm以上。由此，可以利用密封树脂9完好地覆盖配置在相邻导电珠7之间的联结引脚4b。
根据实施方案3，即使在基片4的开口部4a的宽度加宽使联结引脚4b与导电珠7接近时，也能获得模具压料L，利用密封树脂9覆盖联结引脚4b。因此，如图10所示，例如利用金丝14连接半导体芯片2、3的周边联结点2b、3b与基片4的背面的联结引脚4b时，需要加宽开口部4a的宽度使金丝6与金丝14都能穿过，在这种情形下也能获得模具压料L，用树脂进行密封。
再有，实施方案3也同样适用于在附图15所示的半导体装置中开口部增加的情形，通过获得模具压料L，实现用密封树脂9将联结引脚可靠密封。
发明效果
本发明结构如以上说明，具有以下效果。
将第一配线穿过相邻的第一半导体芯片之间及基片的开口部，将第一配线从第二半导体芯片引到基片的第二导电图案，因此可以最大限度地缩短配线路径的长度。因此可以抑制相邻第一配线之间的短路，同时可以抑制第一配线与半导体芯片边缘之间的短路，进而可以提高半导体装置的可信度。另外，通过最大限度地缩短配线路径的长度可以构成有利于高速化的半导体装置。
由于将连接第一配线的多个第一联结点沿开口部的延伸方向配置，所以可以将多个第一配线穿过开口部。
通过沿第二半导体芯片的中心线配置多个上述第一联结点，可以利用中心联结点式样的第二半导体芯片构成半导体装置。
通过设置将第一半导体芯片与第一导电图案电连接的第二配线，可以将第一半导体芯片与第一导电图案利用引线接合连接。
由于将连接第二配线的多个联结点设在了第一半导体芯片的周边，可以最大限度地缩短第二配线的配线路径长度。因此，可以抑制相邻第二配线之间的短路，同时可以抑制第二配线与半导体芯片边缘之间的短路，进而可以提高半导体装置的可信度。另外，最大限度地缩短配线路径的长度可以构成有利于高速化的半导体装置。另外，由于可以使第一配线与第二配线的长度相同，可以抑制在第一半导体芯片与第二半导体芯片之间产生信号的时序差。
由于在第二配线与第一导电图案之间的连接部附近设置了通孔，可以缩短从第一半导体芯片到第二导电图案的配线路径，另外，可以通过第二导电图案使第一半导体芯片的输入和输出独立。
由于在第一半导体芯片与第二半导体芯片之间设置了将两者电连接的凸粒，可以最大限度地缩短从第一半导体芯片到第二半导体芯片的配线路径的长度。
由于将与第二半导体芯片相同的芯片分割后构成了第一半导体芯片，可以利用同一晶片工艺制造第一及第二半导体芯片。因此可以大幅度地降低半导体装置的制造成本。
由于设置了一端连接在上述第一半导体芯片上，另一端连接在上述第二导电图案上的第三配线，并将第三配线穿过开口部，所以可以最大限度地缩短第三配线的配线路径的长度。
由于将连接第三配线的多个第三联结点设在了第一半导体芯片的周边，可以最大限度地缩短第三配线的配线路径。
由于在第一半导体芯片与基片的一个面之间设置了将两者电连接的凸粒，可以最大限度地缩短从第一半导体芯片到基片的配线路径的长度。
由于设置了至少连接多个联结图案中的两个的第三配线，可以提高配线的引线自由度，在基片上设置所需的配线路径。
由于利用第三配线将隔着开口部对置的联结图案之间连接，即使在基片上设置了开口部时也能在基片上设置所需的配线路径。
由于设置了至少连接多个联结图案中的至少两个的连接图案，将连接图案设在联结图案与开口部边缘之间，即使在基片的配线很难引线时，也能在基片上设置所需的配线路径。
由于在导电珠的配置区域与开口部边缘之间的区域内形成联结图案，一个或多个联结图案位于开口部的延伸方向的相邻的两个导电珠之间，即使在导电珠与开口部之间的空间小时也能配置联结图案。
由于接近导电珠部分的密封树脂的宽度比覆盖联结图案部分的宽度窄，可以在导电珠与密封树脂之间设置空间。由此可以在导电珠的周围获得成形密封树脂的模具的压料。
由于接近导电珠部分的密封树脂的宽度比覆盖联结图案部分的宽度窄0.2mm以上，可以切实地获得模具的压料。
由于在第一半导体芯片中至少一个是假芯片，在器件结构上即使在第二半导体芯片的下方不需要配置两个第一半导体芯片时也能构成半导体装置。

Claims (18)

1.一种在基片上安装多个半导体芯片的半导体装置，其特征在于包括：
第一导电图案，设在上述基片的一个面上；
第二导电图案，设在上述基片的另一个面上；
至少两个第一半导体芯片，安装在上述基片的一个面上，并连接在上述第一导电图案上；
第二半导体芯片，安装为横跨在相邻的上述第一半导体芯片上；以及
第一配线，穿过相邻的上述第一半导体芯片之间并通过设在上述基片上的开口部，其一端连接在上述第二半导体芯片的与上述基片对置的面上，另一端连接在上述第二导电图案上。
2.如权利要求1所述的半导体装置，其特征在于，具有设在上述第二半导体芯片的与上述基片对置的面上，分别与多个上述第一配线连接的多个第一联结点，上述开口部沿相邻的上述第一半导体芯片之间的缝隙延伸，多个上述第一联结点沿上述开口部的延伸方向配置。
3.如权利要求2所述的半导体装置，其特征在于，多个上述第一联结点沿上述第二半导体芯片的中心线配置。
4.如权利要求1～3中任一项所述的半导体装置，其特征在于，具有将上述第一半导体芯片与上述第一导电图案电连接的第二配线。
5.如权利要求4所述的半导体装置，其特征在于，上述第一半导体芯片的芯片表面的周边部分具有连接在多个上述第二配线上的多个联结点。
6.如权利要求4或5所述的半导体装置，其特征在于，在上述基片的上述第二配线与上述第一导电图案的连接部附近设置将上述第一导电图案与上述第二导电图案连接的通孔。
7.如权利要求1～6中任一项所述的半导体装置，其特征在于，在上述第1半导体芯片与上述基片的一个面之间具有将上述第一半导体芯片与上述第一导电图案电连接的凸粒。
8.如权利要求1～7中任一项所述的半导体装置，其特征在于，具有由上述第二导电图案构成，分别连接在多个上述第一配线上的多个联结图案，以及至少与上述多个联结图案中的两个连接的第三配线。
9.如权利要求8所述的半导体装置，其特征在于，上述第三配线至少连接在两个隔着开口部对置的上述联结图案上。
10.如权利要求1～7中任一项所述的半导体装置，其特征在于，具有由上述第二导电图案构成，分别连接在多个上述第一配线上的多个联结图案，以及由上述第二导电图案构成，至少与上述多个联结图案中的两个连接的连接图案，上述连接图案设在上述联结图案与上述开口部的边缘之间。
11.如权利要求2～10中任一项所述的半导体装置，其特征在于，
具有由上述第二导电图案构成，分别连接在多个上述第一配线上的多个联结图案，以及固定在上述第二导电图案上，沿上述开口部配置的多个导电珠，上述联结图案形成在上述多个导电珠的配置区域与上述开口部的边缘之间的区域内，一个或多个上述联结图案位于上述开口部的延伸方向上的相邻的两个上述珠之间。
12.如权利要求1～11中任一项所述的半导体装置，其特征在于，上述第一半导体芯片中的至少一个为假芯片。
13.一种在基片上安装半导体芯片的半导体装置，其特征在于，包括：导电图案，设在上述基片的一个面上；半导体芯片，安装在上述基片的另一个面上；第一配线，穿过设在上述基片上的开口部，一端连接在上述半导体芯片的与上述基片对置的面上，另一端连接在上述导电图案上；多个联结图案，由上述导电图案构成，分别连接在多个上述第一配线上；以及第二配线，至少与上述多个联结图案中的两个连接。
14.如权利要求13所述的半导体装置，其特征在于，上述第二配线至少连接在两个隔着上述开口部对置的上述联结图案上。
15.一种在基片上安装半导体芯片的半导体装置，其特征在于，包括：导电图案，设在上述基片的一个面上；半导体芯片，安装在上述基片的另一个面上；配线，穿过设在上述基片上的开口部，一端连接在上述半导体芯片的与上述基片对置的面上，另一端连接在上述导电图案上；多个联结图案，由上述导电图案构成，分别连接在多个上述配线上；以及连接图案，由上述导电图案构成，至少与上述多个联结图案中的两个连接；上述连接图案设在上述联结图案与上述开口部的边缘之间。
16.一种在基片上安装半导体芯片的半导体装置，其特征在于，包括：导电图案，设在上述基片的一个面上；半导体芯片，安装在上述基片的另一个面上；配线，穿过设在上述基片上的开口部，一端连接在上述半导体芯片的与上述基片对置的面上，另一端连接在上述导电图案上；多个联结图案，由上述导电图案构成，分别连接在多个上述配线上；以及多个导电珠，固定在上述导电图案上，沿上述开口部配置；上述联结图案形成在上述多个导电珠的配置区域与上述开口部的边缘之间的区域，一个或多个上述联结图案位于上述开口部方向上的相邻的两个上述珠之间。
17.如权利要求16所述的半导体装置，其特征在于，具有密封树脂，充填上述开口部，以宽于上述开口部的宽度形成在上述另一个面上，覆盖上述联结图案，接近上述导电珠部分的上述密封树脂的宽度比覆盖上述联结图案部分的宽度窄。
18.如权利要求17所述的半导体装置，其特征在于，接近上述导电珠部分的上述密封树脂的宽度比覆盖上述联结图案部分的宽度窄0.2mm以上。
CNA031381928A 2002-07-29 2003-05-29 半导体装置 Pending CN1472808A (zh)

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