CN1291346C - 用于提供敞口空腔低型面封装半导体包装的系统 - Google Patents

用于提供敞口空腔低型面封装半导体包装的系统 Download PDF

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CN1291346C
CN1291346C CNB031199194A CN03119919A CN1291346C CN 1291346 C CN1291346 C CN 1291346C CN B031199194 A CNB031199194 A CN B031199194A CN 03119919 A CN03119919 A CN 03119919A CN 1291346 C CN1291346 C CN 1291346C
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circuit
fingerprint sensor
sensor
contact
external
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CN1444176A (zh
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迈克尔·曼纳萨拉
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Socionext Inc
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Fujitsu Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
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Abstract

本发明涉及一种用于提供敞口空腔低型面封装半导体包装的系统，其中，本系统包括一种用于把指纹传感器电路片引线接合到外部电路的方法。指纹传感器电路片包括具有一个或多个电路片触点的传感器阵列，所述电路片触点引线接合到外部电路的一个或多个外部触点，从而传感器阵列的可用部分得到最大化。本方法包括以下步骤：在接合引线的第一端形成球；在球和外部电路上所选择的外部触点之间形成导电连接；把接合引线延伸到所选择的电路片触点，以便形成具有低线环高度的线环；在接合引线的第二端和所选的电路片触点之间形成导电针脚点焊连接；以及，重复以上步骤，直到一个或多个电路片触点引线接合到外部电路的一个或多个外部触点。

Description

用于提供敞口空腔低型面封装半导体包装的系统
技术领域
本发明涉及半导体器件，并更具体地涉及一种用于提供传感器可接近性增加的指纹传感器的系统。
背景技术
半导体器件日益用作数字系统的输入器件。例如，在鉴别和安全应用中，半导体器件用于提供用户标识信息。一个这样的器件就是半导体指纹传感器。
图1示出典型半导体指纹传感器100的一部分。一般而言，此种传感器用作集成电路(IC)。传感器100包括通过粘合剂或环氧树脂粘结剂106而附着到基板104的电路片(或晶片)102。电路片102的传感器表面108具有以110详细表示的导电栅格，导电栅格用于形成电容电路，以便当传感器表面被接触时检测人指纹的特征。此栅格耦合到在电路片表面上的多个电路片触点部件112。
称为引线接合的技术用于把电路片触点部件112耦合到位于基板材料上的基板触点114，基板材料一般由金属铅框架构成或由多层基板堆积而成。通常，引线接合包括在两个触点部件之间连接细线(金或铝)。以116表示的毛细管器件通常用于在触点之间接合引线。当接合引线时，毛细管器件首先用电子熄火(EFO)技术在引线120端部形成球118。一旦形成球，毛细管器件就用热声学工艺把球118附着到电路片触点片112上。在此工艺中，触点被加热，超声波功率用于在触点上搅动上述球，以使球弄平，从而在球和触点之间形成以122表示的金属间焊点。
在进行第一次焊接之后，毛细管器件116把引线120延伸到基板触点114上，与此触点形成焊点。为了把此引线接合到基板触点114，形成针脚点焊(stitch weld)。针脚点焊把引线接合到基板触点，同时切断引线，以便毛细管器件可在引线的后续部分上形成新球，并前进到下一电路片触点。例如，针脚点焊以124表示。
引线126表示上述引线接合工艺的结果。因为引线一般在垂直方向上从球的焊点延伸到电路片触点，所以当引线延伸向基板触点时，形成线环。线环具有超出电路片表面的高度，以128表示。对于标准引线接合工艺，此线环高度在千分之六到千分之十英寸(6-10密耳)之间。如下文所述，线环高度对指纹传感器100的操作产生影响。
一旦完成引线接合并且安装所有接合引线时，就用封装工艺保护器件，在此工艺中，诸如塑料的材料完全覆盖在接合引线上。例如，可以使用模制工艺，在此工艺中，材料环绕器件而被模制。另一可使用的工艺称作“团块-顶部(glob-top)”分配，在此工艺中，材料被分配到器件的顶部并允许环绕器件侧面和底部流动。
图2示出在完成封装工艺之后的指纹传感器100，从而接合引线被封装材料202完全保护。然而，对于指纹传感器的操作而言，由封装材料中的空腔204暴露出传感器表面108，以允许人手指接触传感器表面。
为了覆盖接合引线并依然提供对传感器表面108的接近，封装材料中的空腔包括至少与接合引线的线环一样高的空腔壁206。空腔壁形成所谓的基座，基座具有以208表示的高度。不幸地是，由于基座的高度，人的手指不能接近传感器表面108的某些部分。例如，用210和212表示的传感器表面区域对于人的手指而言就是不可触及的，因为不可能把手指挤进由传感器表面和空腔壁形成的角落。
指纹传感器一般在最大数量的栅格点被触摸时提供最佳的操作。然而，由于基座高度的影响，部分传感器栅格是不可触及的，从而降低传感器的性能。与常规指纹传感器相关的另一问题是包装尺寸。通常，指纹传感器在传感器表面的任一侧上都具有电路片触点。这导致非常大的包装，不适合便携使用。
克服以上问题的一个方法是提供更大的空腔，以充分考虑传感器表面不可触及的部分。然而，由于电路片的几何形状，不可能提供更大的空腔却不暴露电路片部分。进而，即使更大的空腔是可能的，但封装的总高也是不受欢迎的，因为通常指纹传感器的应用包括要求最小可能尺寸的便携式器件，如蜂窝电话。例如，一个常规指纹传感器的尺寸大约为22×12×.4mm，此尺寸是相对较大的包装，不适合用于便携式应用中。
从而，需要的是一种提供对指纹传感器表面最大接近的方法，同时提供最小可能的尺寸，以允许器件用于各种便携式应用中。
发明内容
本发明包括一种用于把指纹传感器电路片引线接合到外部电路的系统，以提供对指纹传感器表面的最大接近，同时提供最小可能的尺寸，以允许此器件用于各种便携式应用中。本系统降低由接合引线形成的线环高度，从而降低封装的基座高度。基座高度的降低提供对传感器表面更大的接近。因而，通过提供对指纹传感器表面的更大接近，更多的传感器栅格点用于产生传感器读出，这导致更准确的传感器操作。本系统相同地应用到静止型指纹传感器和扫描传感器中。进而，通过降低封装高度，总体器件包装在尺寸上缩小。这导致节约成本，同时允许器件集成到各种小的便携式器件中。
在本发明的一个实施例中，提供一种用于把指纹传感器电路片引线接合到外部电路的方法。指纹传感器电路片包括具有一个或多个电路片触点的传感器阵列，所述电路片触点引线接合到外部电路的一个或多个外部触点，从而传感器阵列的可用部分得到最大化。本方法包括以下步骤：在接合引线的第一端形成球；在球和外部电路上所选择的外部触点之间形成导电连接；把接合引线延伸到所选择的电路片触点，以便形成具有低线环高度的线环；在接合引线的第二端和所选的电路片触点之间形成导电针脚点焊连接；以及，重复以上步骤，直到一个或多个电路片触点引线接合到外部电路的一个或多个外部触点。
在本发明的另一实施例中，提供一种便携式指纹传感器件。本器件包括指纹传感器电路片，所述指纹传感器电路片包括具有一个或多个电路片触点的传感器阵列，所述电路片触点引线接合到外部电路的一个或多个外部触点，从而传感器阵列的可用部分得到最大化。本器件包括在电路片触点和外部触点之间耦合的接合引线，在这，所述接合引线在传感器阵列表面上形成线环高度非常低的线环。本器件用在传感器阵列周围形成空腔的封装材料封闭，以允许人们接触传感器阵列。由于线环高度低的缘故，所述空腔形成较低的基座，使得传感器阵列可被接近的量最大化。在一个或多个修改例中，所述空腔包括阶梯形的、斜坡形的、和/或倒角的空腔壁，以提供更大的传感器表面接近。
附图说明
结合以下附图并根据以下详细描述，可以更加容易地理解本发明的前述几个方面和相应优点，在附图中：
图1示出对指纹传感器电路片的典型电连接；
图2示出具有指纹传感器电路片的典型封装应用；
图3示出具有根据本发明接合的引线的指纹传感器电路片的一个
实施例；
图4示出从图3指纹传感器电路片所得到的封装；
图5a-c说明封装高度如何影响损失的传感器面积；
图6示出解释因封装基座高度而损失传感器区域的扫描型指纹传感器；
图7示出解释因封装基座高度而损失传感器区域的静止型指纹传感器；
图8示出根据本发明构造的阶梯形封装；
图9示出根据本发明构造的斜坡形封装；
图10示出具有根据本发明构造的倒角封装部分的指纹传感器；
图11示出具有根据本发明构造的倒角封装的扫描型指纹传感器；
图12a-d示出根据本发明构造的典型指纹传感器的俯视图、仰视图、侧视图和轴测图；
图13示出指纹传感器电路片的一个实施例，其中，在电路片触点上放置球形补偿器以补偿电路片偏差；
图14示出图13的指纹传感器电路片，此电路片具有根据本发明连接的接合引线；以及
图15示出具有根据本发明构造的指纹传感器的PDA和便携式移动电话。
具体实施方式
本发明包括一种用于把引线接合到指纹传感器电路片的系统，以提供对指纹传感器表面的最大接近，同时提供最小可能的尺寸。本系统降低由接合引线而形成的线环高度，从而降低封装材料的基座高度。因而，包括在本发明中的系统的各个实施例在下文中进行详细讨论。
典型实施例
图3示出根据本发明的指纹传感器电路片300的一个实施例，其中，电路片300具有在电路片触点302和基板触点304之间接合的引线。根据本发明，所示出的接合引线306、308具有非常低的线环高度310。
为了形成图3所示的引线接合，毛细管器件312在接合引线314的端部形成球，并且此球被焊接到一个基板触点304上。然后，引线314延伸到电路片触点，在这进行针脚点焊，把接合引线焊接到电路片触点上。因而，此焊接工艺与常规应用相反，但是其效果是显著的，因为与常规接合引线相比，本发明接合引线的线环高度310大大降低。此结果是有可能的，因为从球焊点垂直延伸的一部分接合引线在传感器表面316之下，从而允许引线延伸到电路片触点302，同时形成具有非常低线环高度的线环。使用此工艺，有可能使线环高度在1-2密耳的范围内，此高度比常规接合技术产生的线环高度低得多。
图4示出从图3指纹传感器电路片300所得到的封装。封装材料402覆盖接合引线，并提供允许指纹传感器被用户接近的空腔404。空腔404由封装材料的基座形成，由于接合引线的较低线环高度，因此，基座高度406非常低。从而，由于基座高度低，因此传感器316上只有非常小的区域408和410是不可接近的。
传感器表面回收
包括在本发明中的一个或多个实施例用于比常规系统增加对传感器表面部分的接近。例如，对于给定的传感器类型、传感器密度和基座高度，可以计算传感器表面的损失量以及相应的传感器栅格点。
图5a-c示出封装高度如何影响扫描型指纹传感器所损失的传感器面积。图5a示出具有传感器表面504和封装部分506的一部分扫描传感器电路片502，封装部分506覆盖连接到电路片502的接合引线。示出的用户手指508扫过传感器表面504。由于封装部分506的高度510，以512表示的一部分传感器表面不能被用户手指接触。因而，在传感器输出时，此部分512不提供与用户手指有关的信息，这导致传感器性能相应下降。
图5b和5c示出具有封装部分506的扫描传感器电路片502，封装部分506具有变化的高度并且对可接近的传感器表面区域产生相应的影响。图5b示出其高度514低于高度510的封装部分506。所获得的损失传感器表面516小于512所示的损失传感器表面。图5c示出其高度518低于高度516的封装部分506。所获得的损失传感器表面520小于516所示的损失传感器表面。因而，封装基座高度越低，可被用户接近的传感器表面面积就更大。当根据本发明连接接合引线时，可实现更低的封装高度。
图6示出根据本发明一个实施例构造的一部分扫描型指纹传感器600。当用户的手指以选定的方向扫过传感器表面时，扫描型指纹传感器获得读出。扫描型指纹传感器使其电路片触点620从传感器阵列的端部移动到与传感器阵列平行的侧边位置，从而电路片触点沿着与扫描方向正交的直线排成一列。此布置导致小得多的传感器件，然而，此布置要求封装高度非常小，否则，传感器阵列的大部分将是不可触及的。因而，需要根据本发明的引线接合来进行此种布置应用。
传感器600包括具有传感器表面604的电路片602。传感器表面604包括形成传感器阵列的行和列的栅格点或传感器象素606。对于此特定的传感器，传感器象素之间的距离称作间距尺寸，并假设为大约50微米。传感器600还包括在封装工艺过程中形成的基座部分608，基座部分608包括空腔壁610。如图所示，基座具有高出传感器表面604的高度(H)。
在操作过程中，用户手指沿着箭头612所示方向扫过传感器表面604。由于基座的高度(H)，距空腔壁610一定距离(PX)内的传感器表面部分将不被用户手指接触。此未触及的部分以614表示，并且，在此区域内的象素在手指扫描过程中不对传感器读出贡献任何信息。
对于扫描型指纹传感器600，因基座高度(H)而损失的传感器距离(PX)可表达如下：
Px＝HxSwLF
在这，SwLF是与扫描型指纹传感器有关的扫描损失系数，并且其值大约为3.2。因而，对于具有常规引线接合且基座高度300μm(大约11.8密耳)的扫描传感器，损失的传感器距离大约为960μm。对于50微米的传感器间距，此损失的传感器距离与损失大约19行传感器象素相对应。然而，在具有根据本发明接合的引线的扫描传感器中，可获得38μm(大约1.5密耳)的基座高度，这导致121μm的损失传感器距离(PX)。因而，对于50微米的传感器间距，损失大约3行的传感器象素。因而示出，根据本发明的引线接合如何有利于与扫描方向正交的电路片触点布置。
图7示出一部分静止型指纹传感器700。传感器700包括具有传感器表面704的电路片702。传感器表面704包括形成传感器阵列的行和列的栅格点或传感器象素。对于此特定的传感器，间距尺寸假设为大约50微米。传感器700还包括在封装工艺中形成的基座部分708和710。基座部分708包括空腔壁712，并且部分710包括在图7中不可见的空腔壁。如图所示，两个基座部分具有高出传感器表面704的高度(H)。
在操作中，用户把手指放到传感器表面704上。由于基座部分的高度(H)，用户手指接触不到传感器表面704上距基座壁一定距离之内的两部分。这些部分具有以714和716表示的距离。在这些区域之内的传感器象素不为传感器读出提供任何信息。
对于具有两个基座的静止型传感器700，损失的传感器距离PX可表达如下：
PX＝2x(HxSLF)
在这，SLF是静止型传感器的损失系数，并且其值大约为1.8。因而，对于基座高度300μm(大约11.8密耳)的静止型传感器，损失的传感器距离大约为1080μm。对于50微米的传感器间距，此损失的传感器距离对应于损失大约22行传感器象素。然而，在具有根据本发明接合的引线的指纹传感器中，可实现38μm(大约1.5密耳)的基座高度，这导致大约137μm的损失传感器距离(PX)。因而，对于50微米的传感器间距，损失大约3行的传感器象素。
从而，根据本发明接合引线的指纹传感器导致较低的线环高度，这意味着更低的封装基座。基座越低，使得用户可触及的传感器表面越大，从而具有以此方式接合的引线的传感器能利用更多的传感器阵列，比常规接合的指纹传感器产生更准确的读出。通过提供对更多传感器表面的接近，根据本发明的引线接合允许使用在要求小传感器的应用中，如在便携式蜂窝电话应用和其它移动便携式器件中，使用更小的指纹传感器。
节约成本
如上所述，降低封装高度导致更多可用的传感器面积。因而，通过减少损失的传感器面积，可生产具有更少材料的更小传感器。例如，需要更少的传感器和封装材料。由于大规模制造指纹传感器的潜力，可以节约巨额的成本。
其它实施例
以下描述包括在本发明中的替代实施例，以便进一步降低基座高度，从而导致更小的指纹传感器。
图8示出具有根据本发明构造的阶梯形封装部分804的静止型指纹传感器电路片802。电路片802包括根据本发明而针脚点焊到电路片触点806的接合引线808。因而，如上所述，接合引线形成具有上述较低线环高度的线环(未示出)。
传感器电路片802包括用于检测用户指纹特征(如称作小花纹的小隆起和凹陷)的传感器表面810。阶梯形封装部分804覆盖由接合引线形成的线环，以便可确定在传感器表面810上的最大封装高度812。如上所述，与常规传感器相比，此最大封装高度因本发明的引线接合技术而大大降低。然而，如以下描述的，阶梯形封装有可能甚至更大地有效降低封装的高度，以提供对传感器表面810的更大接近。
阶梯形封装804形成一种台阶结构，此结构一般与接合引线808在延伸到电路片触点806时的型面相符。最后一级结构814最靠近传感器表面，以使高出传感器表面810的台阶高度最小化，此高度用816表示。小台阶高度的效果是提供对传感器表面最大的接近。例如，由于台阶高度小，因此传感器表面上不可触及的区域(如818和820所示)最小。从而，使用阶梯形封装804有可能进一步降低基座高度，以增加用户对传感器表面的接近。
图9示出具有根据本发明构造的斜坡形封装部分904的静止型指纹传感器电路片902。电路片902包括根据本发明而针脚点焊到电路片触点906的接合引线908。因而，如上所述，接合引线形成具有上述较低线环高度的线环(未示出)。
传感器电路片902包括用于检测用户手指特征的传感器表面910。斜坡形封装904覆盖由接合引线形成的线环，以便确定在传感器表面910上的最大封装高度912。如上所述，与常规传感器相比，此最大封装高度因本发明的引线接合技术而大大降低。然而，如以下描述的，阶梯形封装有可能甚至更大地有效降低封装的高度，以提供对传感器表面910的更大接近。
斜坡形封装904倾斜得覆盖接合引线，同时提供最低的封装高度，使得有可能允许对传感器表面最大的接近。结果，不可接近的传感器表面区域914、916最小。为实现此结果，倾角(a)选择得使封装部分904覆盖接合引线和电路片触点，同时允许此封装形成环绕电路片表面910的最大可能空腔。可选择允许此封装提供所希望保护的任意所需倾角。
本文描述的阶梯形和斜坡形封装技术相同地应用于静止型和扫描型指纹传感器。从而，通过提供根据本发明的引线接合并结合上述任一种封装技术，能实现限制不可接近区域的指纹传感器，同时包括非常小的总体包装，此包装容易用于各种便携式应用中。
图10示出具有根据本发明构造的倒角形封装部分的指纹传感器1000。例如，指纹传感器1000包括形成空腔1004的封装材料1002。在空腔壁的边缘，封装材料形成以1006表示的倒角。
指纹传感器1000包括根据本发明接合的接合引线1008，此引线具有较低的线环高度，从而导致低的封装基座。此封装基座具有1010所示的高度。然而，倒角区1006用于进一步降低基座高度，从而有效的基座高度用1012表示。此降低的基座高度导致小的传感器阵列不可接近区域1014、1016，由于倒角1006的缘故，所述区域比没有倒角时更小。
提供辅助倒角区1018，以进一步减小指纹传感器包装的总尺寸。因而，倒角区和较低接合引线一起用于增加可用传感器阵列的数量并减小器件的总体包装尺寸。
图11示出具有根据本发明构造的倒角封装的扫描型指纹传感器1100。倒角部分1102导致以1104表示的有效基座高度，这转化为由1106确定的传感器不可接近区域。此区域由上述实施例确定，然而，倒角部分1102用于产生比没使用倒角1102时更小的不可接近区域。例如，没有倒角1102时，以1108表示的基座高度用于确定传感器表面上不可接近的区域，此区域比由1106确定的区域更大。因而，倒角用于增加可用传感器面积。
图12a-d示出根据本发明构造的示例性指纹传感器1200的俯视图、仰视图、侧视图和轴测图。指纹传感器1200代表细间距球栅格阵列(FBGA)传感器。
图12a示出传感器1200的俯视图，并以毫米(mm)表示尺寸。由于指纹传感器1200利用根据本发明的引线接合，因此与常规传感器相比，传感器1200的总尺寸大大减小。例如，传感器1200的宽度约为4.3mm，与此相比，常规指纹传感器的宽度为约12-13mm，是前者的四倍宽。
图12b示出指纹传感器1200的仰视图，并说明用于与传感器电接口的球栅格阵列。图12c示出传感器1200的侧视图，并说明根据本发明的引线接合如何导致较低的封装基座高度。例如，由传感器1200实现封装高度.07mm，此高度远远小于常规传感器的封装高度，后者高度约为.4mm。最后，图12d示出传感器1200的轴测图。
图13示出指纹传感器电路片1300的一个实施例，电路片1300具有设置在电路片触点上用于补偿电路片偏差的球形补偿器1302。例如，如图13所示，由于环氧树脂间界1306的变化，电路片1300在基板1304上有偏差。结果，基板上电路片的高度不均匀。例如，以1308表示的高度比以1310表示的高度更大。
为了补偿电路片高度差，在引线接合工艺之前，在每个电路片触点上放置补偿器球1302。例如，毛细管器件1312在引线1316的端部形成球1314，并把此球淀积在选择的电路片触点上。对每个电路片触点重复此工艺。然后，在引线接合工艺中使用补偿器球1302以补偿电路片高度的变化。
图14示出图13的指纹传感器电路片1300，电路片1300具有根据本发明连接的接合引线1402。接合引线通过补偿器球1302耦合到电路片1300。在把接合引线耦合到电路片触点时，补偿器球1302允许有一些变化。结果，电路片高度因环氧树脂间界1306而引起的变化得到补偿，并且，根据本发明，接合引线1402形成线环高度1404非常低的线环。因而，补偿器球1302用于补偿电路片偏差，同时仍然提供根据本发明的引线接合。
图15示出具有根据本发明构造的集成指纹传感器的个人数字助理(PDA)1502和便携式移动电话1504。由于指纹传感器的小尺寸，因此，在各种小的便携式器件中包含这些指纹传感器是有可能的，但是，包含更大的常规传感器则是不可能的。
在一个实施例中，在PDA 1502的侧部包含以1506表示的指纹传感器。在另一个实施例中，在PDA 1502的前部包含以1508表示的指纹传感器。在又一个实施例中，在电话1504的键盘部分中包含以1510表示的指纹传感器。因而，由于通过根据本发明的引线接合实现小的包装尺寸，因此有可能在各种小的便携式器件中包含指纹传感器。
本发明包括一种用于把指纹传感器电路片引线接合到外部电路的系统，以提供对指纹传感器表面的最大接近，同时提供最小可能的尺寸，以允许所述器件用于各种便携式应用中。上述实施例对于本发明是说明性的，并不用于把本发明的范围限制在所述特定实施例上。相应地，虽然已举例并描述本发明的一个或多个实施例，但可以理解，只要不偏离本发明的精神或基本特性，就可对本发明进行各种改变。相应地，本文的内容和描述是示例性的，但并不用于限制后附权利要求所述的本发明范围。

Claims (34)

1.一种用于把指纹传感器电路片引线接合到外部电路的方法，其中，指纹传感器电路片包括具有一个或多个电路片触点的传感器阵列，所述电路片触点引线接合到外部电路的一个或多个外部触点，使得传感器阵列的可用部分得到最大化，本方法包括以下步骤：
在接合引线的第一端形成球；
在球和外部电路上所选择的外部触点之间形成导电连接；
把接合引线延伸到所选择的电路片触点，以便形成具有低线环高度的线环；
在接合引线的第二端和所选的电路片触点之间形成导电针脚点焊连接；以及
重复以上步骤，直到一个或多个电路片触点被引线接合到外部电路的一个或多个外部触点。
2.如权利要求1所述的方法，其中，延伸步骤是把接合引线延伸到所选电路片触点以便形成具有低线环高度的线环的步骤，上述线环高度在1-2密耳的范围内。
3.如权利要求2所述的方法，进一步包括用封装材料封装接合引线的步骤，所述封装材料环绕至少一部分传感器阵列形成空腔，其中，所述空腔具有高出传感器阵列一个高度H的空腔壁，其中，传感器阵列的不可接近部分基本等于由3.2×H确定的区域。
4.如权利要求2所述的方法，进一步包括用封装材料封装接合引线的步骤，所述封装材料环绕至少一部分传感器阵列形成空腔，其中，所述空腔具有高出传感器阵列一个高度H的空腔壁，其中，传感器阵列的不可接近部分基本等于由1.8×H确定的区域。
5.如权利要求3所述的方法，其中，封装步骤包括形成与传感器阵列垂直的空腔壁的步骤。
6.如权利要求3所述的方法，其中，封装步骤包括形成斜坡形空腔壁的步骤。
7.如权利要求3所述的方法，其中，封装步骤包括形成阶梯形空腔壁的步骤。
8.如权利要求3所述的方法，其中，封装步骤包括形成倒角形空腔壁的步骤。
9.如权利要求3所述的方法，其中，H的值在1-2密耳范围内。
10.一种用于把指纹传感器电路片引线接合到外部电路的方法，其中，指纹传感器电路片包括顶部表面，此表面包括具有一个或多个电路片触点的传感器阵列，所述电路片触点引线接合到外部电路的一个或多个外部触点，本方法包括以下步骤：
在接合引线的第一端和所选择的外部触点之间形成导电连接；
把接合引线延伸到所选择的电路片触点，以便形成延伸出顶部表面基本为1.5密耳的线环；
在接合引线的第二端和所选的电路片触点之间形成导电针脚点焊连接；以及
重复以上步骤，直到一个或多个电路片触点电耦合到外部电路的一个或多个外部触点。
11.如权利要求10所述的方法，其中，指纹传感器是静止型指纹传感器，并且本方法进一步包括用封装材料封装接合引线的步骤，所述封装材料环绕传感器器阵列的至少两侧形成空腔，其中，所述空腔具有高出传感器阵列一个高度H的空腔壁，并且其中，传感器阵列的不可接近部分大致等于由1.8×H确定的区域。
12.如权利要求11所述的方法，其中，封装步骤包括形成与传感器阵列垂直的空腔壁的步骤。
13.如权利要求11所述的方法，其中，封装步骤包括形成斜坡形空腔壁的步骤。
14.如权利要求11所述的方法，其中，封装步骤包括形成阶梯形空腔壁的步骤。
15.如权利要求11所述的方法，其中，封装步骤包括形成倒角形空腔壁的步骤。
16.如权利要求11所述的方法，其中，H的值在1-2密耳范围内。
17.如权利要求10所述的方法，其中，指纹传感器是扫描型指纹传感器，并且本方法进一步包括用封装材料封装接合引线的步骤，所述封装材料环绕至少一部分传感器器阵列形成空腔，其中，所述空腔具有高出传感器阵列一个高度H的空腔壁，并且其中，传感器阵列的不可接近部分大致等于由3.2×H确定的区域。
18.如权利要求17所述的方法，其中，封装步骤包括形成与传感器阵列垂直的空腔壁的步骤。
19.如权利要求17所述的方法，其中，封装步骤包括形成斜坡形空腔壁的步骤。
20.如权利要求17所述的方法，其中，封装步骤包括形成阶梯形空腔壁的步骤。
21.如权利要求17所述的方法，其中，封装步骤包括形成倒角形空腔壁的步骤。
22.如权利要求17所述的方法，其中，H的值在1-2密耳范围内。
23.一种包括耦合到外部电路上的指纹传感器电路片的指纹传感器，其中，指纹传感器电路片包括具有一个或多个电路片触点的传感器阵列，并且外部电路包括一个或多个外部触点，所述指纹传感器包括：
在电路片触点和外部触点之间耦合的一根或多根接合引线，其中，接合引线形成具有低线环高度的线环，此线环延伸出传感器电路片顶部表面的高度基本在1-2密耳的范围内；以及
覆盖接合引线并环绕至少一部分传感器阵列形成空腔的封装材料，此封装材料使传感器阵列的不可接近部分最小化。
24.如权利要求23所述的指纹传感器，其中，指纹传感器是扫描型指纹传感器，所述空腔具有高出传感器阵列一个高度H的空腔壁，并且其中，传感器阵列的不可接近部分大致等于由3.2×H确定的区域。
25.如权利要求23所述的指纹传感器，其中，指纹传感器是静止型指纹传感器，所述空腔具有高出传感器阵列一个高度H的空腔壁，并且其中，传感器阵列的不可接近部分大致等于由1.8×H确定的区域。
26.如权利要求24所述的指纹传感器，其中，封装材料形成与传感器阵列垂直的空腔壁。
27.如权利要求24所述的指纹传感器，其中，封装材料形成斜坡形空腔壁。
28.如权利要求24所述的指纹传感器，其中，封装材料形成阶梯形空腔壁。
29.如权利要求24所述的指纹传感器，其中，封装材料形成倒角形空腔壁。
30.如权利要求24所述的指纹传感器，其中，H的值在1-2密耳范围内。
31.一种用于把指纹传感器电路片引线接合到外部电路的方法，其中，指纹传感器电路片包括具有一个或多个电路片触点的传感器阵列，所述电路片触点引线接合到外部电路的一个或多个外部触点，从而传感器阵列的可用部分得到最大化，本方法包括以下步骤：
将表面上具有电路片触点的指纹传感器电路片定位到表面上具有外部触点的外部电路上，使得指纹传感器电路片的表面定位在高于外部电路表面的位置上；
在接合引线和外部电路的所选外部触点之间形成导电连接；
把接合引线从外部电路的所选外部触点延伸出外部电路的外部触点表面；
通过把接合引线延伸向指纹传感器电路片表面上的所选电路片触点而形成高度较低的接合引线线环；以及
在接合引线的第二端和所选电路片触点之间形成导电针脚点焊连接。
32.一种指纹传感器，包括：
表面上具有电路片触点的指纹传感器电路片；
表面上具有外部触点的外部电路，外部电路的表面定位在低于指纹传感器电路片表面的位置上；以及
在电路片触点和外部触点之间耦合的一根或多根接合引线，
其中，接合引线的一端通过在接合引线的所述一端上形成的球而连接到外部电路的所选外部触点，并且接合引线的另一端连接到所选择的电路片触点。
33.如权利要求32所述的指纹传感器，其中，接合引线的另一端通过位于各个所选电路片触点上的球而连接到所选电路片触点。
34.一种指纹传感器，包括：
表面上具有电路片触点的指纹传感器电路片；
表面上具有外部触点的外部电路，外部电路的表面定位在低于指纹传感器电路片表面的位置上；以及
在电路片触点和外部触点之间耦合的一根或多根接合引线，
其中，接合引线从外部电路的所选外部触点沿着与外部电路表面垂直的方向延伸，然后，从垂直延伸的接合引线以环路延伸向指纹传感器电路片的所选电路片触点。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102017112B (zh) * 2008-05-09 2013-06-19 罗伯特·博世有限公司 电气压焊连接装置
CN104851813A (zh) * 2015-05-19 2015-08-19 苏州晶方半导体科技股份有限公司 指纹识别芯片的封装结构及封装方法

Families Citing this family (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6653723B2 (en) * 2002-03-09 2003-11-25 Fujitsu Limited System for providing an open-cavity low profile encapsulated semiconductor package
FR2839570B1 (fr) * 2002-05-07 2004-09-17 Atmel Grenoble Sa Procede de fabrication de capteur d'empreinte digitale et capteur correspondant
US6924496B2 (en) * 2002-05-31 2005-08-02 Fujitsu Limited Fingerprint sensor and interconnect
US7146029B2 (en) * 2003-02-28 2006-12-05 Fujitsu Limited Chip carrier for fingerprint sensor
TWI311353B (en) * 2003-04-18 2009-06-21 Advanced Semiconductor Eng Stacked chip package structure
TWI225623B (en) * 2003-05-29 2004-12-21 Lightuning Tech Inc Card device with a sweep-type fingerprint sensor
US7494042B2 (en) * 2003-10-02 2009-02-24 Asm Technology Singapore Pte. Ltd. Method of forming low wire loops and wire loops formed using the method
KR101313391B1 (ko) 2004-11-03 2013-10-01 테세라, 인코포레이티드 적층형 패키징
KR100626618B1 (ko) * 2004-12-10 2006-09-25 삼성전자주식회사 반도체 칩 적층 패키지 및 제조 방법
WO2006088270A1 (en) * 2005-02-15 2006-08-24 Unisemicon Co., Ltd. Stacked package and method of fabricating the same
US7961914B1 (en) * 2005-07-12 2011-06-14 Smith Robert J D Portable storage apparatus with integral biometric-based access control system
DE102005054177B4 (de) * 2005-11-14 2011-12-22 Infineon Technologies Ag Verfahren zum Herstellen einer Vielzahl von gehäusten Sensormodulen
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US7714453B2 (en) * 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US8581381B2 (en) * 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
JP2008034567A (ja) * 2006-07-27 2008-02-14 Fujitsu Ltd 半導体装置及びその製造方法
JP4833031B2 (ja) * 2006-11-06 2011-12-07 富士通セミコンダクター株式会社 表面形状センサとその製造方法
US8536692B2 (en) * 2007-12-12 2013-09-17 Stats Chippac Ltd. Mountable integrated circuit package system with mountable integrated circuit die
US7985628B2 (en) * 2007-12-12 2011-07-26 Stats Chippac Ltd. Integrated circuit package system with interconnect lock
US8084849B2 (en) * 2007-12-12 2011-12-27 Stats Chippac Ltd. Integrated circuit package system with offset stacking
US7781261B2 (en) * 2007-12-12 2010-08-24 Stats Chippac Ltd. Integrated circuit package system with offset stacking and anti-flash structure
JPWO2009113262A1 (ja) * 2008-03-11 2011-07-21 パナソニック株式会社 半導体デバイスおよび半導体デバイスの製造方法
US20090243069A1 (en) * 2008-03-26 2009-10-01 Zigmund Ramirez Camacho Integrated circuit package system with redistribution
TW200950017A (en) * 2008-05-19 2009-12-01 Lightuning Tech Inc Sensing apparatus with packaging material as sensing protection layer and method of manufacturing the same
TWI380413B (en) * 2008-06-19 2012-12-21 Unimicron Technology Corp Pressure sensing device package and manufacturing method thereof
US9293385B2 (en) * 2008-07-30 2016-03-22 Stats Chippac Ltd. RDL patterning with package on package system
CN101782953B (zh) * 2009-01-16 2012-11-21 深圳富泰宏精密工业有限公司 具有指纹识别功能的便携式电子装置
JP5157964B2 (ja) * 2009-02-27 2013-03-06 オムロン株式会社 光伝送モジュール、電子機器、及び光伝送モジュールの製造方法
WO2010113712A1 (ja) * 2009-03-31 2010-10-07 アルプス電気株式会社 容量型湿度センサ及びその製造方法
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8836478B2 (en) * 2011-09-25 2014-09-16 Authentec, Inc. Electronic device including finger sensor and related methods
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
JP5634380B2 (ja) * 2011-10-31 2014-12-03 アオイ電子株式会社 受光装置およびその製造方法
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
KR101352605B1 (ko) * 2012-11-14 2014-01-22 앰코 테크놀로지 코리아 주식회사 지문 인식용 반도체 패키지 및 그 제조 방법
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
WO2014166547A1 (en) * 2013-04-12 2014-10-16 Osram Opto Semiconductors Gmbh Electronic device and method for producing an electronic device
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US9448130B2 (en) * 2013-08-31 2016-09-20 Infineon Technologies Ag Sensor arrangement
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US20160257117A1 (en) 2013-10-28 2016-09-08 Hewlett-Packard Development Company, L.P. Encapsulating a Bonded Wire with Low Profile Encapsulation
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
TWI485821B (zh) * 2014-02-24 2015-05-21 Dynacard Co Ltd 指紋辨識晶片封裝模組及其製造方法
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
CN104051367A (zh) 2014-07-01 2014-09-17 苏州晶方半导体科技股份有限公司 指纹识别芯片封装结构和封装方法
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9576177B2 (en) * 2014-12-11 2017-02-21 Fingerprint Cards Ab Fingerprint sensing device
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
CN104966707A (zh) * 2015-04-30 2015-10-07 深圳莱宝高科技股份有限公司 指纹采集封装结构及其封装方法
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9663357B2 (en) 2015-07-15 2017-05-30 Texas Instruments Incorporated Open cavity package using chip-embedding technology
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10508935B2 (en) * 2015-10-15 2019-12-17 Advanced Semiconductor Engineering, Inc. Optical module and manufacturing process thereof
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
TWI604389B (zh) * 2017-01-06 2017-11-01 致伸科技股份有限公司 指紋辨識模組
CN107078122B (zh) 2017-01-22 2020-04-03 深圳市汇顶科技股份有限公司 一种指纹芯片封装及加工方法
TWI644601B (zh) * 2017-03-03 2018-12-11 致伸科技股份有限公司 指紋辨識模組的治具及指紋辨識模組的製造方法
CN110077657B (zh) * 2018-01-26 2021-03-09 致伸科技股份有限公司 指纹辨识模块包装方法
WO2020248215A1 (zh) 2019-06-14 2020-12-17 深圳市汇顶科技股份有限公司 芯片封装结构和电子设备

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3235650A1 (de) * 1982-09-27 1984-03-29 Philips Patentverwaltung Gmbh, 2000 Hamburg Informationskarte und verfahren zu ihrer herstellung
US5907627A (en) * 1995-11-06 1999-05-25 Dew Engineering And Development Limited Contact imaging device
US5956415A (en) * 1996-01-26 1999-09-21 Harris Corporation Enhanced security fingerprint sensor package and related methods
US5963679A (en) * 1996-01-26 1999-10-05 Harris Corporation Electric field fingerprint sensor apparatus and related methods
US6028773A (en) * 1997-11-14 2000-02-22 Stmicroelectronics, Inc. Packaging for silicon sensors
KR100260997B1 (ko) * 1998-04-08 2000-07-01 마이클 디. 오브라이언 반도체패키지
US6014066A (en) * 1998-08-17 2000-01-11 Trw Inc. Tented diode shunt RF switch
US20030165743A1 (en) * 1998-10-19 2003-09-04 Tomonari Horikiri Gel electrolyte, cell and electrochromic element
US6307258B1 (en) * 1998-12-22 2001-10-23 Silicon Bandwidth, Inc. Open-cavity semiconductor die package
US6686546B2 (en) * 1998-12-30 2004-02-03 Stmicroelectronics, Inc. Static charge dissipation for an active circuit surface
US6291884B1 (en) * 1999-11-09 2001-09-18 Amkor Technology, Inc. Chip-size semiconductor packages
JP2001141411A (ja) * 1999-11-12 2001-05-25 Sony Corp 指紋認識用半導体装置
US6401545B1 (en) * 2000-01-25 2002-06-11 Motorola, Inc. Micro electro-mechanical system sensor with selective encapsulation and method therefor
WO2002015209A2 (en) * 2000-08-17 2002-02-21 Authentec Inc. Methods and apparatus for making integrated circuit package including opening exposing portion of the ic
US6340846B1 (en) * 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
US6672174B2 (en) * 2001-07-23 2004-01-06 Fidelica Microsystems, Inc. Fingerprint image capture device with a passive sensor array
US6655854B1 (en) * 2001-08-03 2003-12-02 National Semiconductor Corporation Optoelectronic package with dam structure to provide fiber standoff
JP4702586B2 (ja) * 2001-09-10 2011-06-15 日本電気株式会社 指紋センサ及び指紋センサ実装構造並びに該指紋センサを備えた指紋検出器
JP3766034B2 (ja) * 2002-02-20 2006-04-12 富士通株式会社 指紋センサ装置及びその製造方法
US6653723B2 (en) * 2002-03-09 2003-11-25 Fujitsu Limited System for providing an open-cavity low profile encapsulated semiconductor package
JP2003282791A (ja) * 2002-03-20 2003-10-03 Fujitsu Ltd 接触型センサ内蔵半導体装置及びその製造方法
US6998721B2 (en) * 2002-11-08 2006-02-14 Stmicroelectronics, Inc. Stacking and encapsulation of multiple interconnected integrated circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102017112B (zh) * 2008-05-09 2013-06-19 罗伯特·博世有限公司 电气压焊连接装置
CN104851813A (zh) * 2015-05-19 2015-08-19 苏州晶方半导体科技股份有限公司 指纹识别芯片的封装结构及封装方法

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