TWI524438B - 具有導線架的積體電路封裝系統及其製造方法 - Google Patents

具有導線架的積體電路封裝系統及其製造方法 Download PDF

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TWI524438B
TWI524438B TW100117531A TW100117531A TWI524438B TW I524438 B TWI524438 B TW I524438B TW 100117531 A TW100117531 A TW 100117531A TW 100117531 A TW100117531 A TW 100117531A TW I524438 B TWI524438 B TW I524438B
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flat surface
retracted
degrees
crystal pad
integrated circuit
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TW201209940A (en
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沈國強
李在學
姚峰
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星科金朋有限公司
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Description

具有導線架的積體電路封裝系統及其製造方法
本發明涉及積體電路封裝系統，尤其涉及具有導線架的積體電路封裝系統。
積體電路使用於許多攜帶型電子産品中(如手機、攜帶型電腦、答錄機等)以及使用於許多較大型電子系統中(如汽車、飛機、工業控制系統等)。綜觀來說，幾乎所有的應用都不斷要求縮小設備尺寸並提高設備性能。而已經相當普遍的攜帶型電子産品對於上述性能的要求尤為強烈。
隨著電子設備不斷變小變薄，用於積體電路晶片保護和互連的封裝件，尤其是電源積體電路的封裝件，也具有相同的趨勢。
設計和製造半導體設備的目標是使設備更小、更複雜、密度更高，並使其包括額外的特徵。一種改進半導體設備的特徵和密度的方法是縮小半導體設備的製造過程中平版印刷製程步驟的線尺寸(line size)。舉例而言，半導體設備中電路的線寬度每縮小一半，同樣尺寸設備的晶片密度即增加四倍。
遺憾的是，由於物理限制以及縮小半導體設備尺寸的成本因素，簡單地通過改進平版印刷技術所能夠增加的密度非常有限。因此，業界在增加半導體設備密度方面作了許多嘗試。其中一種替代方法是堆疊多個半導體設備。
因此，仍然需要一種積體電路封裝系統，以在不犧牲可靠性、良率和大批量半導體程式的情況下增加密度。鑒於對於增加積體電路密度的需求不斷增加，尤其是攜帶型電子産品，解決上述問題變得極為關鍵。鑒於日益加劇的商業競爭壓力以及不斷增長的消費者預期和市場上產品差異化的日漸縮小，解決上述問題變得更為關鍵。此外，對於降低成本、提高效率和性能、以及面對競爭壓力的需求更進一步增加了解決上述問題的關鍵性與必要性。
長期以來人們一直在試圖解決上述問題，但現有發展均未能給出任何教導或啟示，因此，上述問題一直持續困擾著熟悉相關領域的人士。
本發明提供一種積體電路封裝系統的製造方法，包含：形成晶墊(paddle)，其具有與向外延伸的平坦表面相交成約135度加25度或減5度的角度的縮入平坦表面；在該晶墊上方安裝積體電路；以及在該積體電路上方以及該延伸部下方形成無空洞(void free)的密封體(encapsulation)。
本發明還提供一種積體電路封裝系統，包括：晶墊，其具有與向外延伸的平坦表面相交成約135度加25度或減5度的角度的縮入平坦表面；位在該晶墊上方的積體電路；以及位在該積體電路上方以及該延伸部下方的無空洞的密封體。
本發明的某些實施例具有除了上述步驟或元件或元件以外的其他步驟或元件，或者替代上述步驟或元件的其他步驟或元件。本領域的技術人員藉由參照附圖而閱讀下列詳細說明，將清楚瞭解所述的步驟或元件。
以下詳細描述實施例以使本領域的技術人員能夠製造和使用本發明。基於本發明所揭露的內容可使其他實施例顯而易見，並且可對於系統、流程或機械進行變化而不背離本發明的範圍。
於以下的描述中給出諸多特定細節以利於充分理解本發明。不過，將瞭解到本發明可在不具有這些特定細節的情況下實施。為避免模糊本發明，對一些已知的電路、系統架構和流程步驟均不作詳細揭露。
顯示系統實施例的附圖均是半示意圖，並且未按比例繪製。更詳細地說，為清楚起見，圖中對一些尺寸進行誇大比例顯示。同樣，儘管為描述方便，附圖部分的視圖通常都顯示類似的定向，但圖中的此類描述大多是隨意的。一般而言，可在任意定向下執行本發明。
為了清楚、簡化和便於理解起見，對於所揭露具有一些共同特徵的多個實施例，彼此類似的特徵通常採用類似的元件符號。將實施例編號為第一實施例、第二實施例等僅是為了描述方便起見，並不具有其他意義或意圖限制本發明。
為了說明起見，本文中將術語“水平”定義為在不考慮定向的情況下，與積體電路的平面或表面平行的平面。術語“垂直”指與所定義的水平的方向垂直。如“上方”、“下方”、“底部”、“頂部”、“側面”(如同於“側壁”中)、“高於”、“低於”、“上側”、“在上方”、“在下方”等術語都是相對於所述的水平所定義，如附圖所示。
本文中所用的術語“上面”指元件間直接接觸。術語“直接在上面”指一個元件和另一元件間直接接觸而沒有干預元件。
本文中所用的術語“主動側”是指晶粒、模組、封裝或電子結構中具有主動電路的一側，或者是具有用於連接該晶粒、模組、封裝或電子結構內的主動電路的元件的一側。本文中所用的術語“處理(processing)”包括形成所描述結構所需的材料或光阻材料的沈積、圖案化、曝光、顯影、蝕刻、清洗和/或所述材料或光阻材料的移除等步驟。
現在參照第1圖，顯示本發明一實施例中的積體電路封裝系統100的頂視圖。舉例而言，該積體電路封裝系統100可應用於具有外露焊墊(pad)的四方扁平封裝(Quad Flat Package;QFP)。
該積體電路封裝系統100可包含位元在密封體104(如包括封裝膠體、環氧樹脂成型材料(Epoxy Molding Compound；EMC)或成型材料的覆蓋物)周圍的引線指(lead finger)102，其中該引線指102(如引線(lead)或終端(terminal))。舉例而言，可利用尺寸約在1微米至75微米範圍內的EMC填充物形成密封體104。
現在參照第2圖，顯示積體電路封裝系統100沿第1圖的剖切線2-2的剖視圖。該積體電路封裝系統100可包括晶墊202，例如晶粒附接晶墊(die-attach paddle；DAP)，晶粒附接墊或晶粒墊。
該晶墊202可鄰近該引線指102。該引線指102可圍繞該晶墊202。該晶墊202和該引線指102可為導線架(未圖示)的一部分。
黏著劑204(如膜、環氧樹脂或導電膠)可貼附於晶墊202和積體電路206(如積體電路晶粒、打線積體電路(wirebond integrated circuit)或晶片)。該黏著劑204可將來自該積體電路206的熱量傳導至該晶墊202。
該積體電路206可附接於晶墊202的上方。互連(interconnect)208，(如焊線(bond wire)、條帶焊線(ribbon bond wire)或導線)可連接至該引線指102和該積體電路206。
密封體104可形成於引線指102、晶墊202、黏著劑204、積體電路206以及互連208的上方。密封體104可局部覆蓋該引線指102和該晶墊202。
引線指102的一部分可外露於密封體104的非水平面側，以提供積體電路206和外部系統(未圖示)間的連接。晶墊202可局部外露於密封體104。
現在參照第3圖，顯示部分晶墊202的較詳細視圖。該晶墊202可具有底部側302以及與底部側302相對的頂部側304。底部側302可大致平行於頂部側304。
該晶墊202可包括延伸自該底部側302上方的頂部側304的延伸部306。延伸部306可水平延伸超出底部側302。
延伸部306可形成於晶墊202的周邊。延伸部306可具有由縮入平坦表面308、向外延伸的平坦表面310和非縮入平坦表面312所形成的形狀或結構。
縮入平坦表面308可接續該底部側302。向外延伸的平坦表面310可接續該縮入平坦表面308。非縮入平坦表面312可接續該向外延伸的平坦表面310，並位在該向外延伸的平坦表面310與該頂部側304間。
該向外延伸的平坦表面310位在該縮入平坦表面308與該非縮入平坦表面312間。該縮入平坦表面308可大致平行於該非縮入平坦表面312。
延伸部306可延伸於縮入平坦表面308與非縮入平坦表面312間。向外延伸的平坦表面310可為延伸部306的平坦下表面。延伸部306的平坦上表面可位在該頂部側304。
縮入平坦表面308可為與底部側302垂直的垂直平坦表面。縮入平坦表面308可與向外延伸的平坦表面310相交。
縮入平坦表面308可與向外延伸的平坦表面310形成角度314。該角度314定義為取自或測量自延伸部306的外面並且介於縮入平坦表面308與向外延伸的平坦表面310間的角度。
較佳地，角度314大約為135加25度或減5度。舉例而言，角度314約在130度至145度的範圍內。又舉例而言，角度314約在130度至140度的範圍內。
向外延伸的平坦表面310可為不與縮入平坦表面308和非縮入平坦表面312垂直的非垂直平坦表面。向外延伸的平坦表面310可與非縮入平坦表面312相交。
非縮入平坦表面312可與頂部側304相交。儘管非縮入平坦表面312可為不與頂部側304垂直的非垂直平坦表面，但為描述起見，圖中所示的非縮入平坦表面312是與頂部側304垂直的垂直平坦表面。
舉例而言，基於約為135度加25度或減5度的角度314，晶墊202的向外延伸平坦表面310與縮入平坦表面308的長度比約在0.3至2.7的範圍內。又舉例而言，基於約為135度加25度或減5度的角度314，晶墊202的向外延伸平坦表面310與非縮入平坦表面312的長度比約在0.3至8.5的範圍內。
向外延伸的平坦表面310可自該縮入平坦表面308延伸一水平距離316並與非縮入平坦表面312相交。水平距離316定義為縮入平坦表面308與非縮入平坦表面312間的延伸部306的長度。
水平距離316可隨著角度314的增加而減少。舉例而言，基於約為135度加25度或減5度的角度314，水平距離316與縮入平坦表面308的長度比約在0.3至2.4的範圍內。
為了描述起見，儘管角度314顯示為130度，但並不限於此。舉例而言，角度314可為135度或160度，如虛線所示。
晶墊202可藉由衝壓(stamping)或其他機械製程形成。舉例而言，可藉由衝壓晶墊202形成延伸部306，以使縮入平坦表面308與向外延伸的平坦表面310間形成角度314。
晶墊202可局部外露於第1圖的密封體104。底部側302可外露於密封體104。底部側302可與密封體104共面。
底部側302可安裝於外部系統(未圖示)的上方。舉例而言，底部側302可附接至外部印刷電路板上。又舉例而言，底部側302可藉由連接至接地端、外部接地電位、或第1圖的積體電路封裝系統100外部的電性參考點而接地。
儘管別的晶墊具有看起來類似的角度，但業界一直未能發現或意識到本發明人所發現的問題。只有徹底研究該些問題才能意識到角度314對於解決該些問題而言至關重要。
本發明人發現到，縮入平坦表面308與向外延伸的平坦表面310相交形成角度314有助於提升可靠性。基於故障分析，細微脫層(tiny delamination)發生於導線架設計的經衝壓區域或經半蝕刻區域下方的間隙中，並且由於大的EMC填充物堵塞該些間隙而進一步增加了細微脫層的發生機率。藉由角度314，向外延伸的平坦表面310下方的間隙提供了充足的空間供填充密封膠體(encapsulant)，使可成型性(moldability)得以提升。與使用相同密封膠體的傳統設計相比，可成型性的提升避免了可引起脫層的空洞和多孔表面，藉此滿足顧客所提出在任何區域都不允許有脫層的要求。
本發明人也發現到，具有角度314的晶墊202不僅使密封體104無空洞，而且使密封體104具有鎖模特征(mold lock feature)，從而將晶墊202牢牢地固定於密封體104中。角度314具有大致範圍。該大致範圍的一端是根據容置密封體104所需而設定，另一端是根據能夠將具有大約1-75微米尺寸的填充物的密封體104填充於晶墊202下側(例如：在向外延伸的平坦表面310下)所需而設定。如果角度314小於130度，則空洞會增加。如果角度314大於160度，則延伸部306的水平距離316對於晶墊202來說太小，以至不足以充分鎖在密封體104中。較佳的情況是角度314是135度，可達成無空洞的密封體104和鎖模特征間的平衡。因此，角度314大約為135度加25度或減5度極為關鍵。
本發明人進一步發現到，具有角度314的晶墊202允許積體電路封裝系統100的面積更為緊密。基於角度314的緣故，晶墊202的水平距離316與縮入平坦表面308的長度比例約在0.3至2.4的範圍內。當角度314增加至約160度時，不但使晶墊202充分鎖在密封體104中，而且水平距離316縮小，從而使得面積更為緊密。
現在參照第4圖，顯示本發明另一實施例中積體電路封裝系統100的製造方法400的流程圖。請參照第4圖，方法400包括：在方塊402中，形成晶墊，該晶墊具有與向外延伸的平坦表面相交成約135度加25度或減5度的角度的縮入平坦表面；在方塊404中，在該晶墊上方安裝積體電路；以及在方塊406中，在該積體電路上方以及該延伸部下方形成無空洞的密封體。
所述方法、製程、裝置、設備、產品和/或系統直接明瞭、具成本效益、簡單、靈活多變、精確、靈敏而且有效，可適應現有元件而實現簡易、有效、經濟的製造、應用和利用。
本發明的另一個重要態樣是其符合降低成本、簡化系統、提高性能的長遠發展趨勢。
因此，本發明的上述以及其他態樣將技術水平進一步提升至更高的層次。
儘管本發明已結合特定實施例進行描述，但應當理解的是，本領域技術人員可根據上述說明進行各種替換、更改和變化。因此，欲強調的是，所有此類替換、變更和變化均落入申請專利範圍。上述內容或附圖所示內容均為描述性質，而非限制本發明。
100．．．積體電路封裝系統
102．．．引線指
104．．．密封體
202．．．晶墊
204．．．黏著劑
206．．．積體電路
208．．．互連
302．．．底部側
304．．．頂部側
306．．．延伸部
308．．．縮入平坦表面
310．．．向外延伸的平坦表面
312．．．非縮入平坦表面
314．．．角度
316．．．水平距離
400．．．方法
402、404、406．．．方塊
第1圖顯示本發明一實施例中的積體電路封裝系統的頂視圖。
第2圖顯示該積體電路封裝系統沿第1圖的剖切線2-2的剖視圖。
第3圖顯示部分晶墊的較詳細視圖。
第4圖顯示本發明另一實施例中該積體電路封裝系統的製造方法的流程圖。
100．．．積體電路封裝系統
102．．．引線指
104．．．密封體
202．．．晶墊
204．．．黏著劑
206．．．積體電路
208．．．互連

Claims (10)

  1. 一種積體電路封裝系統的製造方法，包括：形成晶墊，其具有延伸部、縮入平坦表面以及向外延伸的平坦表面，該延伸部由該縮入平坦表面水平延伸，該縮入平坦表面與該向外延伸的平坦表面相交成約135度加25度或減5度的角度，該角度係測量自該延伸部外側並且介於該縮入平坦表面與該向外延伸的平坦表面；在該晶墊上方安裝積體電路；以及在該積體電路上方以及該延伸部下方形成無空洞的密封體。
  2. 如申請專利範圍第1項所述之方法，其中，形成該晶墊包含形成具有約在130度至145度的範圍內的該角度的該晶墊。
  3. 如申請專利範圍第1項所述之方法，其中，形成該晶墊包含形成具有約在130度至140度的範圍內的該角度的該晶墊。
  4. 如申請專利範圍第1項所述之方法，其中，形成該晶墊包含形成具有與該向外延伸的平坦表面相交的非縮入平坦表面的該晶墊，該非縮入平坦表面不與該向外延伸的平坦表面垂直。
  5. 如申請專利範圍第1項所述之方法，其中，形成該晶墊包含形成具有頂部側以及與該頂部側相交的非縮入平坦表面的該晶墊，該非縮入平坦表面與該頂部側垂直。
  6. 一種積體電路封裝系統，包括：晶墊，其具有延伸部、縮入平坦表面以及向外延伸的平坦表面，該延伸部由該縮入平坦表面水平延伸，該縮入平坦表面與該向外延伸的平坦表面相交成約135度加25度或減5度的角度，該角度係測量自該延伸部外側並且介於該縮入平坦表面與該向外延伸的平坦表面；位在該晶墊上方的積體電路；以及位在該積體電路上方以及該延伸部下方的無空洞的密封體。
  7. 如申請專利範圍第6項所述之系統，其中，該晶墊包含具有約在130度至145度的範圍內的該角度的該晶墊。
  8. 如申請專利範圍第6項所述之系統，其中，該晶墊包含具有約在130度至140度的範圍內的該角度的該晶墊。
  9. 如申請專利範圍第6項所述之系統，其中，該晶墊包含具有與該向外延伸的平坦表面相交的非縮入平坦表面的該晶墊，該非縮入平坦表面不與該向外延伸的平坦表面垂直。
  10. 如申請專利範圍第6項所述之系統，其中，該晶墊包含具有頂部側以及與該頂部側相交的非縮入平坦表面的該晶墊，該非縮入平坦表面與該頂部側垂直。
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