CN102290393B - 具有导线架的集成电路封装系统及其制造方法 - Google Patents

具有导线架的集成电路封装系统及其制造方法 Download PDF

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CN102290393B
CN102290393B CN201110139223.2A CN201110139223A CN102290393B CN 102290393 B CN102290393 B CN 102290393B CN 201110139223 A CN201110139223 A CN 201110139223A CN 102290393 B CN102290393 B CN 102290393B
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integrated circuit
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CN102290393A (zh
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沈国强
李在学
姚峰
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Stats Chippac Shanghai Co Ltd
Stats Chippac Pte Ltd
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Abstract

一种集成电路封装系统的制造方法包括：形成晶垫，其具有与向外延伸的平坦表面相交成约135度加25度或减5度的角度的缩入平坦表面；在该晶垫上方安装集成电路；以及在该集成电路上方以及该延伸部下方形成无空洞的密封体。

Description

具有导线架的集成电路封装系统及其制造方法
技术领域
本发明涉及集成电路封装系统，尤其涉及具有导线架的集成电路封装系统。
背景技术
集成电路使用于许多携带型电子产品中(如手机、携带型电脑、答录机等)以及使用于许多较大型电子系统中(如汽车、飞机、工业控制系统等)。综观来说，几乎所有的应用都不断要求缩小设备尺寸并提高设备性能。而已经相当普遍的携带型电子产品对于上述性能的要求尤为强烈。
随着电子设备不断变小变薄，用于集成电路芯片保护和互连的封装件，尤其是电源集成电路的封装件，也具有相同的趋势。
设计和制造半导体设备的目标是使设备更小、更复杂、密度更高，并使其包括额外的特征。一种改进半导体设备的特征和密度的方法是缩小半导体设备的制造过程中光刻程序步骤的线尺寸。举例而言，半导体设备中电路的线宽度每缩小一半，同样尺寸设备的芯片密度即增加四倍。
遗憾的是，由于物理限制以及缩小半导体设备尺寸的成本因素，简单地通过改进光刻技术所能够增加的密度非常有限。因此，业界在增加半导体设备密度方面作了许多尝试。其中一种替代方法是堆叠多个半导体设备。
因此，仍然需要一种集成电路封装系统，以在不牺牲可靠性、良率和大批量半导体程序的情况下增加密度。鉴于对于增加集成电路密度的需求不断增加，尤其是携带型电子产品，解决上述问题变得极为关键。鉴于日益加剧的商业竞争压力以及不断增长的消费者预期和市场上产品差异化的日渐缩小，解决上述问题变得更为关键。此外，对于降低成本、提高效率和性能、以及面对竞争压力的需求更进一步增加了解决上述问题的关键性与必要性。
长期以来人们一直在试图解决上述问题，但现有发展均未能给出任何教导或启示，因此，上述问题一直持续困扰着熟悉相关领域的人士。
发明内容
本发明提供一种集成电路封装系统的制造方法，包含：形成晶垫(paddle)，其具有与向外延伸的平坦表面相交成约135度加25度或减5度的角度的缩入平坦表面；在该晶垫上方安装集成电路；以及在该集成电路上方以及该延伸部下方形成无空洞(voidfree)的密封体(encapsulation)。
本发明还提供一种集成电路封装系统，包括：晶垫，其具有与向外延伸的平坦表面相交成约135度加25度或减5度的角度的缩入平坦表面；位在该晶垫上方的集成电路；以及位在该集成电路上方以及该延伸部下方的无空洞的密封体。
本发明的某些实施例具有除了上述步骤或元件或元件以外的其他步骤或元件，或者替代上述步骤或元件的其他步骤或元件。本领域的技术人员藉由参照附图而阅读下列详细说明，将清楚了解所述的步骤或元件。
附图说明
图1显示本发明一实施例中的集成电路封装系统的顶视图。
图2显示该集成电路封装系统沿图1的剖切线2-2的剖视图。
图3显示部分晶垫的较详细视图。
图4显示本发明另一实施例中该集成电路封装系统的制造方法的流程图。
具体实施方式
以下详细描述实施例以使本领域的技术人员能够制造和使用本发明。基于本发明所揭露的内容可使其他实施例显而易见，并且可对于系统、流程或机械进行变化而不背离本发明的范围。
于以下的描述中给出诸多特定细节以利于充分理解本发明。不过，将了解到本发明可在不具有这些特定细节的情况下实施。为避免模糊本发明，对一些已知的电路、系统架构和流程步骤均不作详细揭露。
显示系统实施例的附图均是半示意图，并且未按比例绘制。更详细地说，为清楚起见，图中对一些尺寸进行夸大比例显示。同样，尽管为描述方便，附图部分的视图通常都显示类似的定向，但图中的此类描述大多是随意的。一般而言，可在任意定向下执行本发明。
为了清楚、简化和便于理解起见，对于所揭露具有一些共同特征的多个实施例，彼此类似的特征通常采用类似的参考标记。将实施例编号为第一实施例、第二实施例等仅是为了描述方便起见，并不具有其他意义或意图限制本发明。
为了说明起见，本文中将术语“水平”定义为在不考虑定向的情况下，与集成电路的平面或表面平行的平面。术语“垂直”指与所定义的水平的方向垂直。如“上方”、“下方”、“底部”、“顶部”、“侧面”(如同于“侧壁”中)、“高于”、“低于”、“上侧”、“在上方”、“在下方”等术语都是相对于所述的水平所定义，如附图所示。
本文中所用的术语“上面”指元件间直接接触。术语“直接在上面”指一个元件和另一元件间直接接触而没有干预元件。
本文中所用的术语“主动侧”是指晶粒、模组、封装或电子结构中具有主动电路的一侧，或者是具有用于连接该晶粒、模组、封装或电子结构内的主动电路的元件的一侧。本文中所用的术语“处理(processing)”包括形成所描述结构所需的材料或光阻材料的沉积、图案化、曝光、显影、蚀刻、清洗和/或所述材料或光阻材料的移除等步骤。
现在参照图1，显示本发明一实施例中的集成电路封装系统100的顶视图。举例而言，该集成电路封装系统100可应用于具有外露焊垫(pad)的四方扁平封装(QuadFlatPackage；QFP)。
该集成电路封装系统100可包含位在密封体104(如包括封装胶体、环氧树脂成型材料(EpoxyMoldingCompound；EMC)或成型材料的覆盖物)周围的引线指102，其中该引线指102(如引线(lead)或终端(terminal))。举例而言，可利用尺寸约在1微米至75微米范围内的EMC填充物形成密封体104。
现在参照图2，显示集成电路封装系统100沿图1的剖切线2-2的剖视图。该集成电路封装系统100可包括晶垫202，例如晶粒附接晶垫(die-attachpaddle；DAP)，晶粒附接垫或晶粒垫。
该晶垫202可邻近该引线指102。该引线指102可围绕该晶垫202。该晶垫202和该引线指102可为导线架(未图示)的一部分。
黏着剂204(如膜、环氧树脂或导电胶)可贴附于晶垫202和集成电路206(如集成电路晶粒、打线集成电路或芯片)。该黏着剂204可将来自该集成电路206的热量传导至该晶垫202。
该集成电路206可附接于晶垫202的上方。互连208，(如焊线(bondwire)、条带焊线(ribbonbondwire)或导线)可连接至该引线指102和该集成电路206。
密封体104可形成于引线指102、晶垫202、黏着剂204、集成电路206以及互连208的上方。密封体104可局部覆盖该引线指102和该晶垫202。
引线指102的一部分可外露于密封体104的非水平面侧，以提供集成电路206和外部系统(未图示)间的连接。晶垫202可局部外露于密封体104。
现在参照图3，显示部分晶垫202的较详细视图。该晶垫202可具有底部侧302以及与底部侧302相对的顶部侧304。底部侧302可大致平行于顶部侧304。
该晶垫202可包括延伸自该底部侧302上方的顶部侧304的延伸部306。延伸部306可水平延伸超出底部侧302。
延伸部306可形成于晶垫202的周边。延伸部306可具有由缩入平坦表面308、向外延伸的平坦表面310和非缩入平坦表面312所形成的形状或结构。
缩入平坦表面308可接续该底部侧302。向外延伸的平坦表面310可接续该缩入平坦表面308。非缩入平坦表面312可接续该向外延伸的平坦表面310，并位在该向外延伸的平坦表面310与该顶部侧304间。
该向外延伸的平坦表面310位在该缩入平坦表面308与该非缩入平坦表面312间。该缩入平坦表面308可大致平行于该非缩入平坦表面312。
延伸部306可延伸于缩入平坦表面308与非缩入平坦表面312间。延伸部306从缩入平坦表面308水平延伸。向外延伸的平坦表面310可为延伸部306的平坦下表面。延伸部306的平坦上表面可位在该顶部侧304。
缩入平坦表面308可为与底部侧302垂直的垂直平坦表面。缩入平坦表面308可与向外延伸的平坦表面310相交。
缩入平坦表面308可与向外延伸的平坦表面310形成角度314。该角度314定义为取自或测量自延伸部306的外面并且介于缩入平坦表面308与向外延伸的平坦表面310间的角度。
较佳地，角度314大约为135加25度或减5度。举例而言，角度314约在130度至145度的范围内。又举例而言，角度314约在130度至140度的范围内。
向外延伸的平坦表面310可为不与缩入平坦表面308和非缩入平坦表面312垂直的非垂直平坦表面。向外延伸的平坦表面310可与非缩入平坦表面312相交。
非缩入平坦表面312可与顶部侧304相交。尽管非缩入平坦表面312可为不与顶部侧304垂直的非垂直平坦表面，但为描述起见，图中所示的非缩入平坦表面312是与顶部侧304垂直的垂直平坦表面。
举例而言，基于约为135度加25度或减5度的角度314，晶垫202的向外延伸平坦表面310与缩入平坦表面308的长度比约在0.3至2.7的范围内。又举例而言，基于约为135度加25度或减5度的角度314，晶垫202的向外延伸平坦表面310与非缩入平坦表面312的长度比约在0.3至8.5的范围内。
向外延伸的平坦表面310可自该缩入平坦表面308延伸一水平距离316并与非缩入平坦表面312相交。水平距离316定义为缩入平坦表面308与非缩入平坦表面312间的延伸部306的长度。
水平距离316可随着角度314的增加而减少。举例而言，基于约为135度加25度或减5度的角度314，水平距离316与缩入平坦表面308的长度比约在0.3至2.4的范围内。
为了描述起见，尽管角度314显示为130度，但并不限于此。举例而言，角度314可为135度或160度，如虚线所示。
晶垫202可藉由冲压或其他机械程序形成。举例而言，可藉由冲压晶垫202形成延伸部306，以使缩入平坦表面308与向外延伸的平坦表面310间形成角度314。
晶垫202可局部外露于图1的密封体104。底部侧302可外露于密封体104。底部侧302可与密封体104共面。
底部侧302可安装于外部系统(未图示)的上方。举例而言，底部侧302可附接至外部印刷电路板上。又举例而言，底部侧302可藉由连接至接地端、外部接地电位、或图1的集成电路封装系统100外部的电性参考点而接地。
尽管别的晶垫具有看起来类似的角度，但业界一直未能发现或意识到本发明人所发现的问题。只有彻底研究该些问题才能意识到角度314对于解决该些问题而言至关重要。
本发明人发现到，缩入平坦表面308与向外延伸的平坦表面310相交形成角度314有助于提升可靠性。基于故障分析，细微脱层(tinydelamination)发生于导线架设计的经冲压区域或经半蚀刻区域下方的间隙中，并且由于大的EMC填充物堵塞该些间隙而进一步增加了细微脱层的发生机率。藉由角度314，向外延伸的平坦表面310下方的间隙提供了充足的空间供填充密封胶体(encapsulant)，使可成型性(moldability)得以提升。与使用相同密封胶体的传统设计相比，可成型性的提升避免了可引起脱层的空洞和多孔表面，藉此满足顾客所提出在任何区域都不允许有脱层的要求。
本发明人也发现到，具有角度314的晶垫202不仅使密封体104无空洞，而且使密封体104具有锁模特征(moldlockfeature)，从而将晶垫202牢牢地固定于密封体104中。角度314具有大致范围。该大致范围的一端是根据容置密封体104所需而设定，另一端是根据能够将具有大约1-75微米尺寸的填充物的密封体104填充于晶垫202下侧(例如：在向外延伸的平坦表面310下)所需而设定。如果角度314小于130度，则空洞会增加。如果角度314大于160度，则延伸部306的水平距离316对于晶垫202来说太小，以至不足以充分锁在密封体104中。较佳的情况是角度314是135度，可达成无空洞的密封体104和锁模特征间的平衡。因此，角度314大约为135度加25度或减5度极为关键。
本发明人进一步发现到，具有角度314的晶垫202允许集成电路封装系统100的面积更为紧密。基于角度314的缘故，晶垫202的水平距离316与缩入平坦表面308的长度比例约在0.3至2.4的范围内。当角度314增加至约160度时，不但使晶垫202充分锁在密封体104中，而且水平距离316缩小，从而使得面积更为紧密。
现在参照图4，显示本发明另一实施例中集成电路封装系统100的制造方法400的流程图。请参照图4，方法400包括：在方块402中，形成晶垫，该晶垫具有与向外延伸的平坦表面相交成约135度加25度或减5度的角度的缩入平坦表面；在方块404中，在该晶垫上方安装集成电路；以及在方块406中，在该集成电路上方以及该延伸部下方形成无空洞的密封体。
所述方法、程序、装置、设备、产品和/或系统直接明了、具成本效益、简单、灵活多变、精确、灵敏而且有效，可适应现有元件而实现简易、有效、经济的制造、应用和利用。
本发明的另一个重要态样是其符合降低成本、简化系统、提高性能的长远发展趋势。
因此，本发明的上述以及其他态样将技术水平进一步提升至更高的层次。
尽管本发明已结合特定实施例进行描述，但应当理解的是，本领域技术人员可根据上述说明进行各种替换、更改和变化。因此，欲强调的是，所有此类替换、变更和变化均落入权利要求范围。上述内容或附图所示内容均为描述性质，而非限制本发明。

Claims (10)

1.一种集成电路封装系统的制造方法，包括：
形成具有延伸部、缩入平坦表面、及向外延伸的平坦表面的晶垫，该延伸部从该缩入平坦表面水平延伸，该缩入平坦表面与该向外延伸的平坦表面相交成130度至160度的角度范围内，该角度从该延伸部的外面并且介于该缩入平坦表面与该向外延伸的平坦表面间测量；
在该晶垫上方安装集成电路；以及
在该集成电路上方以及该延伸部下方形成无空洞的密封体。
2.如权利要求1所述的方法，其中，形成该晶垫包含形成具有在130度至145度的范围内的该角度的该晶垫。
3.如权利要求1所述的方法，其中，形成该晶垫包含形成具有在130度至140度的范围内的该角度的该晶垫。
4.如权利要求1所述的方法，其中，形成该晶垫包含形成具有与该向外延伸的平坦表面相交的非缩入平坦表面的该晶垫，该非缩入平坦表面不与该向外延伸的平坦表面垂直。
5.如权利要求1所述的方法，其中，形成该晶垫包含形成具有顶部侧以及与该顶部侧相交的非缩入平坦表面的该晶垫，该非缩入平坦表面与该顶部侧垂直。
6.一种集成电路封装系统，包括：
具有延伸部、缩入平坦表面、及向外延伸的平坦表面的晶垫，该延伸部从该缩入平坦表面水平延伸，该缩入平坦表面与该向外延伸的平坦表面相交成130度至160度的角度范围内，该角度从该延伸部的外面并且介于该缩入平坦表面与该向外延伸的平坦表面间测量；
位在该晶垫上方的集成电路；以及
位在该集成电路上方以及该延伸部下方的无空洞的密封体。
7.如权利要求6所述的系统，其中，该晶垫包含具有在130度至145度的范围内的该角度的该晶垫。
8.如权利要求6所述的系统，其中，该晶垫包含具有在130度至140度的范围内的该角度的该晶垫。
9.如权利要求6所述的系统，其中，该晶垫包含具有与该向外延伸的平坦表面相交的非缩入平坦表面的该晶垫，该非缩入平坦表面不与该向外延伸的平坦表面垂直。
10.如权利要求6所述的系统，其中，该晶垫包含具有顶部侧以及与该顶部侧相交的非缩入平坦表面的该晶垫，该非缩入平坦表面与该顶部侧垂直。
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