SG139690A1 - Method for manufacturing bonded soi wafer and bonded soi wafer manufactured thereby - Google Patents

Method for manufacturing bonded soi wafer and bonded soi wafer manufactured thereby

Info

Publication number
SG139690A1
SG139690A1 SG200705417-4A SG2007054174A SG139690A1 SG 139690 A1 SG139690 A1 SG 139690A1 SG 2007054174 A SG2007054174 A SG 2007054174A SG 139690 A1 SG139690 A1 SG 139690A1
Authority
SG
Singapore
Prior art keywords
wafer
soi wafer
bonded soi
manufacturing
manufactured
Prior art date
Application number
SG200705417-4A
Other languages
English (en)
Inventor
Yasunobu Ikeda
Shinichi Tomita
Hiroyuki Miyahara
Original Assignee
Sumco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Corp filed Critical Sumco Corp
Publication of SG139690A1 publication Critical patent/SG139690A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
SG200705417-4A 2006-07-24 2007-07-24 Method for manufacturing bonded soi wafer and bonded soi wafer manufactured thereby SG139690A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006200958A JP5315596B2 (ja) 2006-07-24 2006-07-24 貼合せｓｏｉウェーハの製造方法

Publications (1)

Publication Number Publication Date
SG139690A1 true SG139690A1 (en) 2008-02-29

Family

ID=38691873

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200705417-4A SG139690A1 (en) 2006-07-24 2007-07-24 Method for manufacturing bonded soi wafer and bonded soi wafer manufactured thereby

Country Status (6)

Country Link
US (1) US7528049B2 (ja)
EP (1) EP1883104B1 (ja)
JP (1) JP5315596B2 (ja)
CN (1) CN101114574B (ja)
SG (1) SG139690A1 (ja)
TW (1) TW200822179A (ja)

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* Cited by examiner, † Cited by third party
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JP5315596B2 (ja) * 2006-07-24 2013-10-16 株式会社Ｓｕｍｃｏ 貼合せｓｏｉウェーハの製造方法
FR2919427B1 (fr) * 2007-07-26 2010-12-03 Soitec Silicon On Insulator Structure a reservoir de charges.
JP2009283533A (ja) * 2008-05-20 2009-12-03 Sumco Corp 裏面照射型固体撮像素子用ウェーハ、その製造方法及び裏面照射型固体撮像素子
US20090242939A1 (en) * 2008-03-25 2009-10-01 Sumco Corporation Wafer for backside illumination type solid imaging device, production method thereof and backside illumination solid imaging device
JP5696349B2 (ja) * 2008-09-05 2015-04-08 株式会社Sumco 裏面照射型固体撮像素子用ウェーハの製造方法
JP5728902B2 (ja) * 2010-11-25 2015-06-03 株式会社Sumco Ｓｏｉウェーハの製造方法並びにウェーハ貼り合わせシステム
CN102130037B (zh) * 2010-12-27 2013-03-13 上海新傲科技股份有限公司 采用吸杂工艺制备带有绝缘埋层的半导体衬底的方法
CN102130039B (zh) * 2010-12-27 2013-04-10 上海新傲科技股份有限公司 采用吸杂工艺制备带有绝缘埋层的半导体衬底的方法
WO2012088710A1 (zh) 2010-12-27 2012-07-05 上海新傲科技股份有限公司 采用吸杂工艺制备带有绝缘埋层的半导体衬底的方法
JP2013229356A (ja) * 2012-04-24 2013-11-07 Mitsubishi Electric Corp Ｓｏｉウェハおよびその製造方法、並びにｍｅｍｓデバイス
JP5867291B2 (ja) * 2012-05-24 2016-02-24 株式会社Sumco Ｓｏｉウェーハの製造方法
JP6303321B2 (ja) * 2013-08-08 2018-04-04 株式会社Sumco 貼り合わせウェーハの製造方法および貼り合わせウェーハ
CN105448668B (zh) * 2015-12-30 2018-09-14 西安立芯光电科技有限公司 一种改善SiNx在GaAs晶圆上粘附性的方法
US20170339100A1 (en) * 2016-05-18 2017-11-23 Empire Technology Development Llc Device address update based on event occurrences
TWI727515B (zh) * 2018-11-30 2021-05-11 台灣積體電路製造股份有限公司 形成soi結構的方法
US11289330B2 (en) 2019-09-30 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator (SOI) substrate and method for forming
TWI796599B (zh) * 2019-09-30 2023-03-21 台灣積體電路製造股份有限公司 絕緣層上半導體（soi）基底、形成絕緣層上半導體基底的方法以及積體電路

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JPH06112451A (ja) * 1992-09-29 1994-04-22 Nagano Denshi Kogyo Kk Ｓｏｉ基板の製造方法
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JP5315596B2 (ja) * 2006-07-24 2013-10-16 株式会社Ｓｕｍｃｏ 貼合せｓｏｉウェーハの製造方法
JP5459899B2 (ja) * 2007-06-01 2014-04-02 株式会社半導体エネルギー研究所 半導体装置の作製方法
WO2008156040A1 (en) * 2007-06-20 2008-12-24 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
US7795111B2 (en) * 2007-06-27 2010-09-14 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate and manufacturing method of semiconductor device

Also Published As

Publication number Publication date
CN101114574A (zh) 2008-01-30
US20080020541A1 (en) 2008-01-24
TWI364059B (ja) 2012-05-11
EP1883104B1 (en) 2015-09-30
TW200822179A (en) 2008-05-16
US7528049B2 (en) 2009-05-05
CN101114574B (zh) 2011-07-27
JP5315596B2 (ja) 2013-10-16
EP1883104A1 (en) 2008-01-30
JP2008028244A (ja) 2008-02-07

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