SG139623A1 - Method for the simultaneous double-side grinding of a plurality of semiconductor wafers, and semiconductor wafer having outstanding flatness - Google Patents

Method for the simultaneous double-side grinding of a plurality of semiconductor wafers, and semiconductor wafer having outstanding flatness

Info

Publication number
SG139623A1
SG139623A1 SG200703837-5A SG2007038375A SG139623A1 SG 139623 A1 SG139623 A1 SG 139623A1 SG 2007038375 A SG2007038375 A SG 2007038375A SG 139623 A1 SG139623 A1 SG 139623A1
Authority
SG
Singapore
Prior art keywords
semiconductor wafers
side grinding
simultaneous double
semiconductor wafer
semiconductor
Prior art date
Application number
SG200703837-5A
Other languages
English (en)
Inventor
Georg Pietsch
Michael Kerstan
Original Assignee
Siltronic Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siltronic Ag filed Critical Siltronic Ag
Publication of SG139623A1 publication Critical patent/SG139623A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
    • B24B37/08—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Grinding Of Cylindrical And Plane Surfaces (AREA)
  • Constituent Portions Of Griding Lathes, Driving, Sensing And Control (AREA)
SG200703837-5A 2006-07-13 2007-05-29 Method for the simultaneous double-side grinding of a plurality of semiconductor wafers, and semiconductor wafer having outstanding flatness SG139623A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102006032455A DE102006032455A1 (de) 2006-07-13 2006-07-13 Verfahren zum gleichzeitigen beidseitigen Schleifen mehrerer Halbleiterscheiben sowie Halbleierscheibe mit hervorragender Ebenheit

Publications (1)

Publication Number Publication Date
SG139623A1 true SG139623A1 (en) 2008-02-29

Family

ID=38949832

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200703837-5A SG139623A1 (en) 2006-07-13 2007-05-29 Method for the simultaneous double-side grinding of a plurality of semiconductor wafers, and semiconductor wafer having outstanding flatness

Country Status (7)

Country Link
US (1) US7815489B2 (de)
JP (1) JP4730844B2 (de)
KR (1) KR100914540B1 (de)
CN (1) CN101106082B (de)
DE (1) DE102006032455A1 (de)
SG (1) SG139623A1 (de)
TW (1) TWI373071B (de)

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DE102011003006B4 (de) * 2011-01-21 2013-02-07 Siltronic Ag Verfahren zur Bereitstellung jeweils einer ebenen Arbeitsschicht auf jeder der zwei Arbeitsscheiben einer Doppelseiten-Bearbeitungsvorrichtung
JP5479390B2 (ja) * 2011-03-07 2014-04-23 信越半導体株式会社 シリコンウェーハの製造方法
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DE102012201516A1 (de) 2012-02-02 2013-08-08 Siltronic Ag Verfahren zum Polieren einer Halbleiterscheibe
WO2013146133A1 (ja) * 2012-03-30 2013-10-03 コニカミノルタ株式会社 情報記録媒体用ガラス基板の製造方法および情報記録媒体
DE102012206398A1 (de) 2012-04-18 2012-06-21 Siltronic Ag Verfahren zur beidseitigen Bearbeitung einer Scheibe aus Halbleitermaterial
DE102012214998B4 (de) 2012-08-23 2014-07-24 Siltronic Ag Verfahren zum beidseitigen Bearbeiten einer Halbleiterscheibe
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Also Published As

Publication number Publication date
CN101106082B (zh) 2011-07-06
JP2008018528A (ja) 2008-01-31
DE102006032455A1 (de) 2008-04-10
TW200805478A (en) 2008-01-16
JP4730844B2 (ja) 2011-07-20
KR100914540B1 (ko) 2009-09-02
US20080014839A1 (en) 2008-01-17
CN101106082A (zh) 2008-01-16
KR20080007165A (ko) 2008-01-17
TWI373071B (en) 2012-09-21
US7815489B2 (en) 2010-10-19

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