SG11201907932UA - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
SG11201907932UA
SG11201907932UA SG11201907932UA SG11201907932UA SG11201907932UA SG 11201907932U A SG11201907932U A SG 11201907932UA SG 11201907932U A SG11201907932U A SG 11201907932UA SG 11201907932U A SG11201907932U A SG 11201907932UA SG 11201907932U A SG11201907932U A SG 11201907932UA
Authority
SG
Singapore
Prior art keywords
memory device
semiconductor memory
substrates
element layers
vias
Prior art date
Application number
SG11201907932UA
Other languages
English (en)
Inventor
Masaru Koyanagi
Original Assignee
Toshiba Memory Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Memory Corp filed Critical Toshiba Memory Corp
Publication of SG11201907932UA publication Critical patent/SG11201907932UA/en

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    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/145—Read-only memory [ROM]
    • H01L2924/1451—EPROM
    • H01L2924/14511—EEPROM

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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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PCT/JP2018/001639 WO2018168198A1 (fr) 2017-03-15 2018-01-19 Dispositif de stockage à semiconducteur

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JP6800788B2 (ja) 2020-12-16
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CN110447102B (zh) 2024-03-05
TW201836125A (zh) 2018-10-01
TWI807342B (zh) 2023-07-01
EP3598493A4 (fr) 2021-01-20
TWI667772B (zh) 2019-08-01
WO2018168198A1 (fr) 2018-09-20
JP2018156968A (ja) 2018-10-04
CN110447102A (zh) 2019-11-12
US20190385984A1 (en) 2019-12-19
US11594523B2 (en) 2023-02-28
EP3598493A1 (fr) 2020-01-22
TW202207424A (zh) 2022-02-16
US20220005789A1 (en) 2022-01-06

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