SG11201906510PA - Method and device for bonding chips - Google Patents

Method and device for bonding chips

Info

Publication number
SG11201906510PA
SG11201906510PA SG11201906510PA SG11201906510PA SG11201906510PA SG 11201906510P A SG11201906510P A SG 11201906510PA SG 11201906510P A SG11201906510P A SG 11201906510PA SG 11201906510P A SG11201906510P A SG 11201906510PA SG 11201906510P A SG11201906510P A SG 11201906510PA
Authority
SG
Singapore
Prior art keywords
chips
bonding chips
bonding
onto
substrate
Prior art date
Application number
SG11201906510PA
Other languages
English (en)
Inventor
Markus Wimplinger
Original Assignee
Ev Group E Thallner Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ev Group E Thallner Gmbh filed Critical Ev Group E Thallner Gmbh
Publication of SG11201906510PA publication Critical patent/SG11201906510PA/en

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/9512—Aligning the plurality of semiconductor or solid-state bodies
    • H01L2224/95136—Aligning the plurality of semiconductor or solid-state bodies involving guiding structures, e.g. shape matching, spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/9512—Aligning the plurality of semiconductor or solid-state bodies
    • H01L2224/95143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H01L2224/95146—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium by surface tension
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Wire Bonding (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Dicing (AREA)
SG11201906510PA 2017-03-02 2017-03-02 Method and device for bonding chips SG11201906510PA (en)

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TW201842630A (zh) 2018-12-01
TWI797492B (zh) 2023-04-01
CN118737997A (zh) 2024-10-01
EP3590130A1 (fr) 2020-01-08
JP7453299B2 (ja) 2024-03-19
JP2020509578A (ja) 2020-03-26
US11764198B2 (en) 2023-09-19
JP2022169798A (ja) 2022-11-09
CN110214369A (zh) 2019-09-06
KR102624841B1 (ko) 2024-01-15
US20240170474A1 (en) 2024-05-23
JP2024060010A (ja) 2024-05-01
KR20190119031A (ko) 2019-10-21
TWI713159B (zh) 2020-12-11
US11990463B2 (en) 2024-05-21
CN118737999A (zh) 2024-10-01
KR20230042124A (ko) 2023-03-27
JP7137571B2 (ja) 2022-09-14
TW202324548A (zh) 2023-06-16
KR20240010753A (ko) 2024-01-24
TW202401595A (zh) 2024-01-01
CN118737998A (zh) 2024-10-01
US20200176437A1 (en) 2020-06-04
WO2018157937A1 (fr) 2018-09-07
US20210134782A1 (en) 2021-05-06
TWI842412B (zh) 2024-05-11

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