WO2015107290A3 - Procédé de placement et de collage de puces sur un substrat récepteur en utilisant un plot a l'aide d'une force d'attraction magnétique, électrostatique ou électromagnétique. - Google Patents

Procédé de placement et de collage de puces sur un substrat récepteur en utilisant un plot a l'aide d'une force d'attraction magnétique, électrostatique ou électromagnétique. Download PDF

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Publication number
WO2015107290A3
WO2015107290A3 PCT/FR2015/050052 FR2015050052W WO2015107290A3 WO 2015107290 A3 WO2015107290 A3 WO 2015107290A3 FR 2015050052 W FR2015050052 W FR 2015050052W WO 2015107290 A3 WO2015107290 A3 WO 2015107290A3
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WO
WIPO (PCT)
Prior art keywords
bonding
receiving
chips
zone
pad
Prior art date
Application number
PCT/FR2015/050052
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English (en)
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WO2015107290A2 (fr
Inventor
Chrystel Deguet
Frank Fournel
Hubert Moriceau
Loic Sanchez
Original Assignee
Commissariat à l'énergie atomique et aux énergies alternatives
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Application filed by Commissariat à l'énergie atomique et aux énergies alternatives filed Critical Commissariat à l'énergie atomique et aux énergies alternatives
Publication of WO2015107290A2 publication Critical patent/WO2015107290A2/fr
Publication of WO2015107290A3 publication Critical patent/WO2015107290A3/fr

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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/9512—Aligning the plurality of semiconductor or solid-state bodies
    • H01L2224/95136—Aligning the plurality of semiconductor or solid-state bodies involving guiding structures, e.g. shape matching, spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view

Abstract

Un procédé de placement et de collage de puces (4) sur un substrat récepteur (6), ce procédé comportant : a) la fourniture (44, 98) de plusieurs puces (4), chaque puce (4) comportant une face de collage et une couche de transfert (36), b) le placement (70, 100, 126) des puces (4) à des emplacements prédéfinis en attirant la couche de transfert (36) à l'aide d'un plot (58), la force d'attraction entre la couche de transfert (36) et le plot (58) étant une force choisie dans le groupe composé d'une force magnétique, d'une force électrostatique et d'une force électromagnétique, c) le collage (74, 100, 126) des faces de collage des puces (4) ainsi placées sur des zones de réception respectives d'une face active (10) du substrat récepteur (6), chaque zone de réception ayant la même surface que la face de collage collée sur cette zone de réception et chaque zone de réception étant lisse et directement bordée par une zone périphérique lisse et au même niveau pour prolonger cette zone de réception dans un même plan ou par une zone périphérique en retrait à l'intérieur du substrat (6), dans lequel : - les faces de collage et les zones de réception sont préparées pour permettre un collage sans apport de matière adhésive entre les faces de collage et les zones de réception correspondantes, puis - lors de l'étape c), chaque face de collage est mise en contact direct avec sa zone de réception respective pour obtenir ainsi un collage sans apport de matière adhésive (un collage direct) des puces (4) sur le substrat récepteur (6).
PCT/FR2015/050052 2014-01-14 2015-01-09 Procédé de placement et de collage de puces sur un substrat récepteur WO2015107290A2 (fr)

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FR1450293 2014-01-14
FR1450293A FR3016474A1 (fr) 2014-01-14 2014-01-14 Procede de placement et de collage de puces sur un substrat recepteur

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JP7137571B2 (ja) 2017-03-02 2022-09-14 エーファウ・グループ・エー・タルナー・ゲーエムベーハー チップを接合する方法および装置
FR3102771B1 (fr) * 2019-10-31 2021-10-08 Commissariat Energie Atomique Procédé de collage de deux surfaces hydrophiles
CN112992878B (zh) * 2021-02-05 2023-01-13 惠州市聚飞光电有限公司 一种芯片转移方法及显示装置
CN113053793B (zh) * 2021-03-19 2023-02-03 江西乾照光电有限公司 一种Micro LED阵列器件巨量转移装置及转移方法
CN114335260A (zh) * 2021-12-27 2022-04-12 深圳市思坦科技有限公司 一种led芯片转移方法、转移基板制备方法及显示器件

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EP1209735A2 (fr) * 2000-10-24 2002-05-29 Shinko Electric Industries Co. Ltd. Dispositif semi-conducteur et son procédé de fabrication
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EP1209735A2 (fr) * 2000-10-24 2002-05-29 Shinko Electric Industries Co. Ltd. Dispositif semi-conducteur et son procédé de fabrication
US20080121724A1 (en) * 2005-05-12 2008-05-29 Infineon Technologies Ag Semiconductor Chips for TAG Applications, Devices for Mounting the Same, and Mounting Method
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