SG11201810919UA - Engineered substrate structure for power and rf applications - Google Patents

Engineered substrate structure for power and rf applications

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Publication number
SG11201810919UA
SG11201810919UA SG11201810919UA SG11201810919UA SG11201810919UA SG 11201810919U A SG11201810919U A SG 11201810919UA SG 11201810919U A SG11201810919U A SG 11201810919UA SG 11201810919U A SG11201810919U A SG 11201810919UA SG 11201810919U A SG11201810919U A SG 11201810919UA
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SG
Singapore
Prior art keywords
international
layer coupled
quora
santa clara
california
Prior art date
Application number
SG11201810919UA
Other languages
English (en)
Inventor
Vladimir Odnoblyudov
Cem Basceri
Shari Farrens
Original Assignee
Qromis Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qromis Inc filed Critical Qromis Inc
Publication of SG11201810919UA publication Critical patent/SG11201810919UA/en

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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
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    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • C30B25/14Feed and outlet means for the gases; Modifying the flow of the reactive gases
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    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • C30B25/18Epitaxial-layer growth characterised by the substrate
    • C30B25/183Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10Inorganic compounds or compositions
    • C30B29/40AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
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    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
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    • H01L21/02367Substrates
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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    • H01L33/0066Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Peptides Or Proteins (AREA)
SG11201810919UA 2016-06-14 2017-06-13 Engineered substrate structure for power and rf applications SG11201810919UA (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662350077P 2016-06-14 2016-06-14
US201662350084P 2016-06-14 2016-06-14
PCT/US2017/037252 WO2017218536A1 (en) 2016-06-14 2017-06-13 Engineered substrate structure for power and rf applications

Publications (1)

Publication Number Publication Date
SG11201810919UA true SG11201810919UA (en) 2019-01-30

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SG11201810919UA SG11201810919UA (en) 2016-06-14 2017-06-13 Engineered substrate structure for power and rf applications

Country Status (7)

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EP (1) EP3469119A4 (ja)
JP (4) JP6626607B2 (ja)
KR (1) KR102361057B1 (ja)
CN (2) CN114256068A (ja)
SG (1) SG11201810919UA (ja)
TW (2) TWI793755B (ja)
WO (1) WO2017218536A1 (ja)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017218536A1 (en) * 2016-06-14 2017-12-21 Quora Technology, Inc. Engineered substrate structure for power and rf applications
US10297445B2 (en) 2016-06-14 2019-05-21 QROMIS, Inc. Engineered substrate structure for power and RF applications
US10622468B2 (en) * 2017-02-21 2020-04-14 QROMIS, Inc. RF device integrated on an engineered substrate
US10734303B2 (en) * 2017-11-06 2020-08-04 QROMIS, Inc. Power and RF devices implemented using an engineered substrate structure
US10586844B2 (en) * 2018-01-23 2020-03-10 Texas Instruments Incorporated Integrated trench capacitor formed in an epitaxial layer
TWI692869B (zh) * 2019-05-03 2020-05-01 世界先進積體電路股份有限公司 基底及其製造方法
CN111987140A (zh) * 2019-05-21 2020-11-24 世界先进积体电路股份有限公司 基底及其制造方法
JP7319227B2 (ja) 2020-05-11 2023-08-01 信越化学工業株式会社 Iii-v族化合物結晶用ベース基板及びその製造方法
KR20230020968A (ko) 2020-06-09 2023-02-13 신에쓰 가가꾸 고교 가부시끼가이샤 Iii족 질화물계 에피택셜 성장용 기판과 그 제조 방법
JP2022012558A (ja) 2020-07-01 2022-01-17 信越化学工業株式会社 大口径iii族窒化物系エピタキシャル成長用基板とその製造方法
KR102446604B1 (ko) * 2021-01-04 2022-09-26 한국과학기술원 스트레인드 채널 성장 구조, 및 그를 이용한 스트레인드 채널 및 소자 제조 방법
WO2022168572A1 (ja) 2021-02-05 2022-08-11 信越半導体株式会社 窒化物半導体基板及びその製造方法
JP2022131086A (ja) 2021-02-26 2022-09-07 信越半導体株式会社 窒化物半導体基板およびその製造方法
WO2022191079A1 (ja) * 2021-03-10 2022-09-15 信越化学工業株式会社 エピタキシャル成長用種基板およびその製造方法、ならびに半導体基板およびその製造方法
JP7334869B2 (ja) * 2021-06-08 2023-08-29 信越半導体株式会社 窒化物半導体基板及びその製造方法
JP2023025432A (ja) * 2021-08-10 2023-02-22 信越半導体株式会社 窒化物半導体基板及びその製造方法
WO2023047864A1 (ja) * 2021-09-21 2023-03-30 信越半導体株式会社 窒化物半導体基板及びその製造方法
JPWO2023063278A1 (ja) * 2021-10-15 2023-04-20
JPWO2023063046A1 (ja) * 2021-10-15 2023-04-20
JP2023065227A (ja) 2021-10-27 2023-05-12 信越化学工業株式会社 エピタキシャル成長用種基板およびその製造方法、ならびに半導体基板およびその製造方法
WO2023119916A1 (ja) 2021-12-21 2023-06-29 信越半導体株式会社 窒化物半導体基板および窒化物半導体基板の製造方法
JP2023098137A (ja) * 2021-12-28 2023-07-10 信越化学工業株式会社 高特性エピタキシャル成長用基板とその製造方法
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