SG11201810054RA - Standard cell architecture for diffusion based on fin count - Google Patents

Standard cell architecture for diffusion based on fin count

Info

Publication number
SG11201810054RA
SG11201810054RA SG11201810054RA SG11201810054RA SG11201810054RA SG 11201810054R A SG11201810054R A SG 11201810054RA SG 11201810054R A SG11201810054R A SG 11201810054RA SG 11201810054R A SG11201810054R A SG 11201810054RA SG 11201810054R A SG11201810054R A SG 11201810054RA
Authority
SG
Singapore
Prior art keywords
international
logic
cells
drive
diffusion regions
Prior art date
Application number
SG11201810054RA
Other languages
English (en)
Inventor
Jr Anthony Correale
Benjamin Bowers
ROVA Tracey DELLA
Iii William Goodall
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of SG11201810054RA publication Critical patent/SG11201810054RA/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Architecture (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Peptides Or Proteins (AREA)
  • Error Detection And Correction (AREA)
SG11201810054RA 2016-06-22 2017-06-22 Standard cell architecture for diffusion based on fin count SG11201810054RA (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662353536P 2016-06-22 2016-06-22
US15/629,728 US10366196B2 (en) 2016-06-22 2017-06-21 Standard cell architecture for diffusion based on fin count
PCT/US2017/038730 WO2018013315A1 (en) 2016-06-22 2017-06-22 Standard cell architecture for diffusion based on fin count

Publications (1)

Publication Number Publication Date
SG11201810054RA true SG11201810054RA (en) 2019-01-30

Family

ID=60675625

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201810054RA SG11201810054RA (en) 2016-06-22 2017-06-22 Standard cell architecture for diffusion based on fin count

Country Status (8)

Country Link
US (2) US10366196B2 (zh)
EP (2) EP3475983A1 (zh)
JP (2) JP6972031B2 (zh)
KR (2) KR102528329B1 (zh)
CN (2) CN109314109B (zh)
CA (1) CA3024332C (zh)
SG (1) SG11201810054RA (zh)
WO (2) WO2017223295A1 (zh)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10366196B2 (en) 2016-06-22 2019-07-30 Qualcomm Incorporated Standard cell architecture for diffusion based on fin count
US11211330B2 (en) * 2017-05-01 2021-12-28 Advanced Micro Devices, Inc. Standard cell layout architectures and drawing styles for 5nm and beyond
US11347925B2 (en) 2017-05-01 2022-05-31 Advanced Micro Devices, Inc. Power grid architecture and optimization with EUV lithography
US11011545B2 (en) * 2017-11-14 2021-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including standard cells
KR102465964B1 (ko) 2018-05-18 2022-11-10 삼성전자주식회사 다중 높이 셀을 포함하는 집적 회로 및 이를 제조하기 위한 방법
KR102560368B1 (ko) 2018-06-20 2023-07-27 삼성전자주식회사 확산 방지 영역을 구비하는 반도체 소자
US10522542B1 (en) 2018-06-28 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Double rule integrated circuit layouts for a dual transmission gate
US10797078B2 (en) * 2018-08-14 2020-10-06 Taiwan Semiconductor Manufacturing Company Limited Hybrid fin field-effect transistor cell structures and related methods
KR102599048B1 (ko) 2018-08-16 2023-11-06 삼성전자주식회사 표준 셀을 포함하는 집적 회로 및 이를 제조하기 위한 방법
US10783313B2 (en) 2018-08-30 2020-09-22 Taiwan Semiconductor Manufacturing Company Ltd. Method for improved cut metal patterning
US10977418B2 (en) * 2018-09-28 2021-04-13 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device with cell region, method of generating layout diagram and system for same
US10700065B2 (en) 2018-10-10 2020-06-30 Apple Inc. Leakage current reduction in electrical isolation gate structures
KR102539066B1 (ko) * 2018-11-09 2023-06-01 삼성전자주식회사 서로 다른 타입의 셀들을 포함하는 집적 회로, 그 설계 방법 및 설계 시스템
US11030381B2 (en) * 2019-01-16 2021-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Leakage analysis on semiconductor device
KR102556811B1 (ko) 2019-01-25 2023-07-18 삼성전자주식회사 반도체 장치
KR102635671B1 (ko) * 2019-03-21 2024-02-14 에스케이하이닉스 주식회사 반도체 장치
CN112018112A (zh) * 2019-05-29 2020-12-01 中芯国际集成电路制造(上海)有限公司 半导体单元结构及其形成方法
US11387229B2 (en) 2019-06-14 2022-07-12 Samsung Electronics Co., Ltd. Semiconductor device
US11862637B2 (en) * 2019-06-19 2024-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Tie off device
KR20210009503A (ko) 2019-07-17 2021-01-27 삼성전자주식회사 반도체 장치 및 그 제조 방법
US11488947B2 (en) 2019-07-29 2022-11-01 Tokyo Electron Limited Highly regular logic design for efficient 3D integration
US10796061B1 (en) 2019-08-29 2020-10-06 Advanced Micro Devices, Inc. Standard cell and power grid architectures with EUV lithography
KR20210028306A (ko) 2019-09-03 2021-03-12 삼성전자주식회사 반도체 장치의 레이아웃 설계 방법
CN110690215A (zh) * 2019-11-13 2020-01-14 上海华力微电子有限公司 基于FinFET小面积标准单元的版图结构
KR20210077189A (ko) 2019-12-17 2021-06-25 삼성전자주식회사 반도체 집적 회로
KR20210128661A (ko) 2020-04-17 2021-10-27 삼성전자주식회사 반도체 장치
TWI790619B (zh) * 2020-05-26 2023-01-21 台灣積體電路製造股份有限公司 積體電路結構
US11424250B2 (en) * 2020-08-27 2022-08-23 Qualcomm Incorporated Memory
US11552085B2 (en) 2020-09-28 2023-01-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including memory cell and fin arrangements
US11817392B2 (en) 2020-09-28 2023-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit
EP4060738A4 (en) * 2021-02-05 2022-11-30 Changxin Memory Technologies, Inc. STANDARD CELL TEMPLATE AND SEMICONDUCTOR STRUCTURE
US11955369B2 (en) 2021-06-08 2024-04-09 International Business Machines Corporation Recessed local interconnect formed over self-aligned double diffusion break

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060190893A1 (en) 2005-02-24 2006-08-24 Icera Inc. Logic cell layout architecture with shared boundary
US7266787B2 (en) 2005-02-24 2007-09-04 Icera, Inc. Method for optimising transistor performance in integrated circuits
JPWO2007063990A1 (ja) * 2005-12-02 2009-05-07 日本電気株式会社 半導体装置およびその製造方法
US9009641B2 (en) * 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US9563733B2 (en) * 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US7763534B2 (en) * 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
JP4791868B2 (ja) * 2006-03-28 2011-10-12 株式会社東芝 Ｆｉｎ−ＮＡＮＤ型フラッシュメモリ
US7838948B2 (en) 2007-01-30 2010-11-23 Infineon Technologies Ag Fin interconnects for multigate FET circuit blocks
JP4461154B2 (ja) * 2007-05-15 2010-05-12 株式会社東芝 半導体装置
JP2009016418A (ja) * 2007-07-02 2009-01-22 Nec Electronics Corp 半導体装置
US8141016B2 (en) 2008-08-29 2012-03-20 International Business Machines Corporation Integrated design for manufacturing for 1×N VLSI design
JP2010098081A (ja) * 2008-09-16 2010-04-30 Hitachi Ltd 半導体装置
US8258577B2 (en) * 2009-06-04 2012-09-04 International Business Machines Corporation CMOS inverter device with fin structures
US8258572B2 (en) * 2009-12-07 2012-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM structure with FinFETs having multiple fins
US10192859B2 (en) * 2011-05-11 2019-01-29 Texas Instruments Incorporated Integrated circuits and processes for protection of standard cell performance from context effects
US8595661B2 (en) 2011-07-29 2013-11-26 Synopsys, Inc. N-channel and p-channel finFET cell architecture
CN104303263B (zh) * 2012-01-13 2016-12-14 特拉创新公司 具有线形翅片场效应结构的电路
US9252021B2 (en) * 2012-02-09 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for patterning a plurality of features for Fin-like field-effect transistor (FinFET) devices
US8901615B2 (en) * 2012-06-13 2014-12-02 Synopsys, Inc. N-channel and P-channel end-to-end finfet cell architecture
US8723268B2 (en) 2012-06-13 2014-05-13 Synopsys, Inc. N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch
US9123565B2 (en) 2012-12-31 2015-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. Masks formed based on integrated circuit layout design having standard cell that includes extended active region
US8943455B2 (en) 2013-03-12 2015-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for layout verification for polysilicon cell edge structures in FinFET standard cells
US9158877B2 (en) * 2013-05-02 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell metal structure directly over polysilicon structure
JP6281571B2 (ja) 2013-08-28 2018-02-21 株式会社ソシオネクスト 半導体集積回路装置
JP6281572B2 (ja) * 2013-09-04 2018-02-21 株式会社ソシオネクスト 半導体装置
JP2016029690A (ja) * 2014-07-25 2016-03-03 マイクロン テクノロジー， インク． 半導体装置及びその製造方法
JP6449082B2 (ja) * 2014-08-18 2019-01-09 ルネサスエレクトロニクス株式会社 半導体装置
JP6373686B2 (ja) * 2014-08-22 2018-08-15 ルネサスエレクトロニクス株式会社 半導体装置
US20160111421A1 (en) * 2014-10-21 2016-04-21 Mark S. Rodder Multiple cpp for increased source/drain area for fets including in a critical speed path
FI20150334A (fi) * 2015-01-14 2016-07-15 Artto Mikael Aurola Paranneltu puolijohdekokoonpano
US9337099B1 (en) 2015-01-30 2016-05-10 Globalfoundries Inc. Special constructs for continuous non-uniform active region FinFET standard cells
US10366196B2 (en) 2016-06-22 2019-07-30 Qualcomm Incorporated Standard cell architecture for diffusion based on fin count

Also Published As

Publication number Publication date
EP3475984A1 (en) 2019-05-01
WO2017223295A1 (en) 2017-12-28
JP2019519114A (ja) 2019-07-04
EP3475983A1 (en) 2019-05-01
US10236302B2 (en) 2019-03-19
BR112018075720A2 (pt) 2019-03-26
US10366196B2 (en) 2019-07-30
JP6972031B2 (ja) 2021-11-24
CN109314109B (zh) 2023-08-11
US20170371995A1 (en) 2017-12-28
KR20190019952A (ko) 2019-02-27
WO2018013315A1 (en) 2018-01-18
CN109314109A (zh) 2019-02-05
JP6752905B2 (ja) 2020-09-09
US20170373090A1 (en) 2017-12-28
CN109314110A (zh) 2019-02-05
CA3024332C (en) 2021-09-14
BR112018075596A2 (pt) 2019-03-26
CN109314110B (zh) 2023-06-13
KR102083190B1 (ko) 2020-03-02
CA3024332A1 (en) 2017-12-28
KR102528329B1 (ko) 2023-05-02
KR20190020682A (ko) 2019-03-04
JP2019519110A (ja) 2019-07-04

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