SG10201909185PA - Memory device including charge pump circuit - Google Patents

Memory device including charge pump circuit

Info

Publication number
SG10201909185PA
SG10201909185PA SG10201909185PA SG10201909185PA SG10201909185PA SG 10201909185P A SG10201909185P A SG 10201909185PA SG 10201909185P A SG10201909185P A SG 10201909185PA SG 10201909185P A SG10201909185P A SG 10201909185PA SG 10201909185P A SG10201909185P A SG 10201909185PA
Authority
SG
Singapore
Prior art keywords
memory device
device including
charge pump
pump circuit
including charge
Prior art date
Application number
SG10201909185PA
Other languages
English (en)
Inventor
Baek Se-Heon
Byeon Dae-Seok
Jang Ki-chang
Min Young-Sun
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201909185PA publication Critical patent/SG10201909185PA/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/30Power supply circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/32Timing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222Clock generating, synchronizing or distributing circuits within memory device
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073Charge pumps of the Schenkel-type
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22Control and timing of internal memory operations
    • G11C2207/2254Calibration
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073Charge pumps of the Schenkel-type
    • H02M3/077Charge pumps of the Schenkel-type with parallel connected charge pump stages

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Dc-Dc Converters (AREA)
  • Read Only Memory (AREA)
SG10201909185PA 2018-10-05 2019-10-01 Memory device including charge pump circuit SG10201909185PA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020180119304A KR102545174B1 (ko) 2018-10-05 2018-10-05 차지 펌프 회로를 포함하는 메모리 장치

Publications (1)

Publication Number Publication Date
SG10201909185PA true SG10201909185PA (en) 2020-05-28

Family

ID=70051246

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201909185PA SG10201909185PA (en) 2018-10-05 2019-10-01 Memory device including charge pump circuit

Country Status (4)

Country Link
US (1) US10867639B2 (ko)
KR (1) KR102545174B1 (ko)
CN (1) CN111009267A (ko)
SG (1) SG10201909185PA (ko)

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KR20220049653A (ko) * 2020-10-14 2022-04-22 삼성전자주식회사 비휘발성 메모리 장치
US11908528B2 (en) * 2020-11-20 2024-02-20 Stmicroelectronics International N.V. Selectively configurable charge pump
EP4033661B1 (en) * 2020-11-25 2024-01-24 Changxin Memory Technologies, Inc. Control circuit and delay circuit
KR20220118174A (ko) * 2021-02-18 2022-08-25 에스케이하이닉스 주식회사 충전펌프회로와 그 동작방법 및 충전펌프회로를 포함하는 반도체 장치
CN113409849A (zh) * 2021-05-21 2021-09-17 芯天下技术股份有限公司 一种降低编程功耗的方法、装置、存储介质和终端
IT202200006488A1 (it) * 2022-04-01 2023-10-01 St Microelectronics Srl Dispositivo regolatore di tensione, corrispondenti procedimento e sistema di archiviazione dati

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Also Published As

Publication number Publication date
US20200111513A1 (en) 2020-04-09
CN111009267A (zh) 2020-04-14
KR102545174B1 (ko) 2023-06-19
US10867639B2 (en) 2020-12-15
KR20200039403A (ko) 2020-04-16

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