NL8600848A - Geheugen met gelijktijdig adresseerbare geheugenelementen. - Google Patents

Geheugen met gelijktijdig adresseerbare geheugenelementen. Download PDF

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Publication number
NL8600848A
NL8600848A NL8600848A NL8600848A NL8600848A NL 8600848 A NL8600848 A NL 8600848A NL 8600848 A NL8600848 A NL 8600848A NL 8600848 A NL8600848 A NL 8600848A NL 8600848 A NL8600848 A NL 8600848A
Authority
NL
Netherlands
Prior art keywords
tree structure
memory
memory elements
selection
addressing
Prior art date
Application number
NL8600848A
Other languages
English (en)
Dutch (nl)
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Priority to NL8600848A priority Critical patent/NL8600848A/nl
Priority to EP87200564A priority patent/EP0241078B1/en
Priority to DE8787200564T priority patent/DE3771252D1/de
Priority to US07/033,126 priority patent/US4845678A/en
Priority to JP62081298A priority patent/JPH07104815B2/ja
Publication of NL8600848A publication Critical patent/NL8600848A/nl

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/14—Conversion to or from non-weighted codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Image Input (AREA)
  • Memory System (AREA)
NL8600848A 1986-04-03 1986-04-03 Geheugen met gelijktijdig adresseerbare geheugenelementen. NL8600848A (nl)

Priority Applications (5)

Application Number Priority Date Filing Date Title
NL8600848A NL8600848A (nl) 1986-04-03 1986-04-03 Geheugen met gelijktijdig adresseerbare geheugenelementen.
EP87200564A EP0241078B1 (en) 1986-04-03 1987-03-24 Memory comprising simultaneously addressable memory elements
DE8787200564T DE3771252D1 (de) 1986-04-03 1987-03-24 Speicher mit gleichzeitig adressierbaren speicherelementen.
US07/033,126 US4845678A (en) 1986-04-03 1987-03-31 Memory comprising simultaneously addressable memory elements
JP62081298A JPH07104815B2 (ja) 1986-04-03 1987-04-03 メモリ

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8600848A NL8600848A (nl) 1986-04-03 1986-04-03 Geheugen met gelijktijdig adresseerbare geheugenelementen.
NL8600848 1986-04-03

Publications (1)

Publication Number Publication Date
NL8600848A true NL8600848A (nl) 1987-11-02

Family

ID=19847818

Family Applications (1)

Application Number Title Priority Date Filing Date
NL8600848A NL8600848A (nl) 1986-04-03 1986-04-03 Geheugen met gelijktijdig adresseerbare geheugenelementen.

Country Status (5)

Country Link
US (1) US4845678A (ja)
EP (1) EP0241078B1 (ja)
JP (1) JPH07104815B2 (ja)
DE (1) DE3771252D1 (ja)
NL (1) NL8600848A (ja)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2514365B2 (ja) * 1987-06-16 1996-07-10 三菱電機株式会社 機能ブロックのアドレスデコ−ド装置
US5247634A (en) * 1990-03-20 1993-09-21 Hewlett-Packard Company Method of managing memory allocation by association of memory blocks with a tree structure
JPH04147493A (ja) * 1990-10-09 1992-05-20 Mitsubishi Electric Corp 半導体メモリ
JPH04258876A (ja) * 1991-02-12 1992-09-14 Mitsubishi Electric Corp 半導体メモリ装置およびメモリアクセスシステム
US5235545A (en) * 1991-03-29 1993-08-10 Micron Technology, Inc. Memory array write addressing circuit for simultaneously addressing selected adjacent memory cells
JPH0628861A (ja) * 1992-07-07 1994-02-04 Oki Electric Ind Co Ltd 半導体記憶装置
US5363337A (en) * 1992-07-15 1994-11-08 Micron Technology, Inc. Integrated circuit memory with variable addressing of memory cells
US5313433A (en) * 1992-09-11 1994-05-17 Micron Technology, Inc. Windowed flash write circuit
US6167499A (en) * 1997-05-20 2000-12-26 Vlsi Technology, Inc. Memory space compression technique for a sequentially accessible memory
DE19738712C2 (de) * 1997-09-04 2001-09-20 Siemens Ag Nichtflüchtiger Speicher mit zu Subblöcken zusammengefaßten Speicherzellen
JP2000122919A (ja) * 1998-10-13 2000-04-28 Mitsubishi Electric Corp プロセッサ及びメモリ制御方法
GB2383145B (en) 2001-10-31 2005-09-07 Alphamosaic Ltd Data access in a processor
GB2382677B (en) * 2001-10-31 2005-09-07 Alphamosaic Ltd Data access in a processor
GB2382676B (en) * 2001-10-31 2005-09-07 Alphamosaic Ltd Data access in a processor
US7928764B2 (en) * 2006-08-31 2011-04-19 Agate Logic (Beijing), Inc. Programmable interconnect network for logic array

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3895360A (en) * 1974-01-29 1975-07-15 Westinghouse Electric Corp Block oriented random access memory
US4087811A (en) * 1976-02-25 1978-05-02 International Business Machines Corporation Threshold decoder
US4106109A (en) * 1977-02-01 1978-08-08 Ncr Corporation Random access memory system providing high-speed digital data output
JPS55143652A (en) * 1979-04-25 1980-11-10 Hitachi Ltd Series-parallel signal converter
SU826418A1 (ru) * 1979-08-17 1981-04-30 Кировский Политехнический Институт Запоминающее устройство
JPS5634179A (en) * 1979-08-24 1981-04-06 Mitsubishi Electric Corp Control circuit for memory unit
JPS5798173A (en) * 1980-12-09 1982-06-18 Panafacom Ltd Module selecting system of storage device
US4434502A (en) * 1981-04-03 1984-02-28 Nippon Electric Co., Ltd. Memory system handling a plurality of bits as a unit to be processed
DE3341982A1 (de) * 1983-11-21 1985-05-30 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zur zaehlung von 1-belegungen in (0,1)- vektoren
FR2566938B1 (fr) * 1984-06-29 1989-08-18 Texas Instruments France Memoire permettant de transformer un flot de mots de donnees en un autre flot de mots de donnees
JPH069116B2 (ja) * 1985-05-24 1994-02-02 日立超エル・エス・アイエンジニアリング株式会社 半導体集積回路装置
GB8515482D0 (en) * 1985-06-19 1985-07-24 Int Computers Ltd Search apparatus
JPH0629855A (ja) * 1992-07-11 1994-02-04 Hitachi Ltd Ｄ／ａ変換器
JPH0654055A (ja) * 1992-07-28 1994-02-25 Nec Corp 加入者線によるケーブル芯線電圧制御接続方式

Also Published As

Publication number Publication date
US4845678A (en) 1989-07-04
JPH07104815B2 (ja) 1995-11-13
EP0241078B1 (en) 1991-07-10
JPS62237542A (ja) 1987-10-17
DE3771252D1 (de) 1991-08-14
EP0241078A1 (en) 1987-10-14

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Legal Events

Date Code Title Description
A1B A search report has been drawn up
BV The patent application has lapsed