JPS5798173A - Module selecting system of storage device - Google Patents
Module selecting system of storage deviceInfo
- Publication number
- JPS5798173A JPS5798173A JP17360280A JP17360280A JPS5798173A JP S5798173 A JPS5798173 A JP S5798173A JP 17360280 A JP17360280 A JP 17360280A JP 17360280 A JP17360280 A JP 17360280A JP S5798173 A JPS5798173 A JP S5798173A
- Authority
- JP
- Japan
- Prior art keywords
- memory array
- address
- comparing circuit
- array card
- address information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
- G06F12/0669—Configuration or reconfiguration with decentralised address assignment
- G06F12/0676—Configuration or reconfiguration with decentralised address assignment the address being position dependent
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To easily extend the capacity of a memory without requiring a complicated setting operation, by providing each specific adding means, lower limit address comparing circuit and upper limit address comparing circuit on each memory array card. CONSTITUTION:Each memory array card 3-1-3-n is provided with an adding means 31 for adding the capacity portion of a memory array 10 placed in its own memory array card, to address information inputted from the memory array card of the following side, and outputting it to the memory array card of the preceding side, or a control part 2. Also, said memory array card is provided with a lower limit address comparing circuit 32 for comparing an inputted address information with an access address information sent out from an access request origin 1, and an upper limit address address comparing circuit 33 for comparing an output of the adding means 31 with the access address information. In this way, in accordance with outputs of the lower limit address comparing circuit 32 and the upper limit address comparing circuit 33, it is discriminated that the access address information is in an address area of the relevant memory array card 3, and a relevant memory array selecting signal is generated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17360280A JPS5798173A (en) | 1980-12-09 | 1980-12-09 | Module selecting system of storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17360280A JPS5798173A (en) | 1980-12-09 | 1980-12-09 | Module selecting system of storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5798173A true JPS5798173A (en) | 1982-06-18 |
Family
ID=15963639
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17360280A Pending JPS5798173A (en) | 1980-12-09 | 1980-12-09 | Module selecting system of storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5798173A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4845678A (en) * | 1986-04-03 | 1989-07-04 | U.S. Philips Corporation | Memory comprising simultaneously addressable memory elements |
-
1980
- 1980-12-09 JP JP17360280A patent/JPS5798173A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4845678A (en) * | 1986-04-03 | 1989-07-04 | U.S. Philips Corporation | Memory comprising simultaneously addressable memory elements |
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