JPS5725053A - Memory device - Google Patents

Memory device

Info

Publication number
JPS5725053A
JPS5725053A JP9929180A JP9929180A JPS5725053A JP S5725053 A JPS5725053 A JP S5725053A JP 9929180 A JP9929180 A JP 9929180A JP 9929180 A JP9929180 A JP 9929180A JP S5725053 A JPS5725053 A JP S5725053A
Authority
JP
Japan
Prior art keywords
read
common bus
memory device
data
central processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9929180A
Other languages
Japanese (ja)
Inventor
Susumu Yoshino
Koji Kunida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9929180A priority Critical patent/JPS5725053A/en
Publication of JPS5725053A publication Critical patent/JPS5725053A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0669—Configuration or reconfiguration with decentralised address assignment

Abstract

PURPOSE:To realize a memory device which is inexpensive and high in mounting efficiency, by not inputting a discriminating information which has been received from a common bus, to a control system in a device, but sending it out to the common bus, in a data processing system using an asynchronous two-way common bus. CONSTITUTION:When a central processing equipment 14 which requests to read out a data from a memory device 13 transfers a read-out address, a read-out instruction signal, and a discrimination number of the central processing equipment 14, to the memory device 13, read-out is started, and when a read-out data is obtained, the read-out data information and the discrimination number are transferred to a common bus 10. An equipment which has coincided with the discrimination number of the own device, that is to say, the central processing equipment 14 only inputs a read-out data on the common bus.
JP9929180A 1980-07-22 1980-07-22 Memory device Pending JPS5725053A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9929180A JPS5725053A (en) 1980-07-22 1980-07-22 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9929180A JPS5725053A (en) 1980-07-22 1980-07-22 Memory device

Publications (1)

Publication Number Publication Date
JPS5725053A true JPS5725053A (en) 1982-02-09

Family

ID=14243532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9929180A Pending JPS5725053A (en) 1980-07-22 1980-07-22 Memory device

Country Status (1)

Country Link
JP (1) JPS5725053A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992005490A1 (en) * 1990-09-18 1992-04-02 Fujitsu Limited Exclusive control method for shared memory
WO1992005489A1 (en) * 1990-09-18 1992-04-02 Fujitsu Limited Method of nonsynchronous access to shared memory
US6108755A (en) * 1990-09-18 2000-08-22 Fujitsu Limited Asynchronous access system to a shared storage

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992005490A1 (en) * 1990-09-18 1992-04-02 Fujitsu Limited Exclusive control method for shared memory
WO1992005489A1 (en) * 1990-09-18 1992-04-02 Fujitsu Limited Method of nonsynchronous access to shared memory
US5377324A (en) * 1990-09-18 1994-12-27 Fujitsu Limited Exclusive shared storage control system in computer system
US6108755A (en) * 1990-09-18 2000-08-22 Fujitsu Limited Asynchronous access system to a shared storage

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