NL1007898C2 - Werkwijze voor het vervaardigen van een halfgeleider-inrichting. - Google Patents

Werkwijze voor het vervaardigen van een halfgeleider-inrichting. Download PDF

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Publication number
NL1007898C2
NL1007898C2 NL1007898A NL1007898A NL1007898C2 NL 1007898 C2 NL1007898 C2 NL 1007898C2 NL 1007898 A NL1007898 A NL 1007898A NL 1007898 A NL1007898 A NL 1007898A NL 1007898 C2 NL1007898 C2 NL 1007898C2
Authority
NL
Netherlands
Prior art keywords
base layer
bipolar transistor
layer
forming
insulating film
Prior art date
Application number
NL1007898A
Other languages
English (en)
Dutch (nl)
Other versions
NL1007898A1 (nl
Inventor
Takayuki Gomi
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of NL1007898A1 publication Critical patent/NL1007898A1/xx
Application granted granted Critical
Publication of NL1007898C2 publication Critical patent/NL1007898C2/nl

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/01Bipolar transistors-ion implantation
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/011Bipolar transistors
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/933Germanium or silicon or Ge-Si on III-V

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
NL1007898A 1996-12-26 1997-12-24 Werkwijze voor het vervaardigen van een halfgeleider-inrichting. NL1007898C2 (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP34691796A JP3409618B2 (ja) 1996-12-26 1996-12-26 半導体装置の製造方法
JP34691796 1996-12-26

Publications (2)

Publication Number Publication Date
NL1007898A1 NL1007898A1 (nl) 1998-06-29
NL1007898C2 true NL1007898C2 (nl) 2001-06-07

Family

ID=18386692

Family Applications (1)

Application Number Title Priority Date Filing Date
NL1007898A NL1007898C2 (nl) 1996-12-26 1997-12-24 Werkwijze voor het vervaardigen van een halfgeleider-inrichting.

Country Status (5)

Country Link
US (1) US5915186A (ko)
JP (1) JP3409618B2 (ko)
KR (1) KR19980064697A (ko)
DE (1) DE19757685A1 (ko)
NL (1) NL1007898C2 (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1298516B1 (it) * 1998-01-30 2000-01-12 Sgs Thomson Microelectronics Dispositivo elettronico di potenza integrato su un materiale semiconduttore e relativo processo di fabricazione
US6323538B1 (en) * 1999-01-12 2001-11-27 Matsushita Electric Industrial Co., Ltd. Bipolar transistor and method for fabricating the same
US7521733B2 (en) * 2002-05-14 2009-04-21 Infineon Technologies Ag Method for manufacturing an integrated circuit and integrated circuit with a bipolar transistor and a hetero bipolar transistor
DE10221416A1 (de) * 2002-05-14 2003-11-27 Infineon Technologies Ag Verfahren zum Herstellen einer integrierten Schaltung und integrierte Schaltung mit einem Bipolartransistor und einem Heterobipolartransistor
JP4784595B2 (ja) * 2007-12-21 2011-10-05 株式会社デンソー バイポーラ型の半導体装置の製造方法
US9761608B1 (en) 2016-08-15 2017-09-12 International Business Machines Corporation Lateral bipolar junction transistor with multiple base lengths

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5739567A (en) * 1980-07-18 1982-03-04 Nec Corp Manufacture of semiconductor device
EP0342695A2 (en) * 1988-05-20 1989-11-23 Fujitsu Limited Semiconductor device
US5137840A (en) * 1990-10-24 1992-08-11 International Business Machines Corporation Vertical bipolar transistor with recessed epitaxially grown intrinsic base region
US5494836A (en) * 1993-04-05 1996-02-27 Nec Corporation Process of producing heterojunction bipolar transistor with silicon-germanium base
US5523606A (en) * 1993-10-07 1996-06-04 Nec Corporation BiCMOS semiconductor device having SiGe heterojunction and Si homo-junction transistors
JPH09162296A (ja) * 1995-12-12 1997-06-20 Sony Corp 半導体装置およびその製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4133701A (en) * 1977-06-29 1979-01-09 General Motors Corporation Selective enhancement of phosphorus diffusion by implanting halogen ions
JPS564263A (en) * 1979-06-25 1981-01-17 Hitachi Ltd Semiconductor memory
JPS5676560A (en) * 1979-11-28 1981-06-24 Hitachi Ltd Semiconductor device
JPS56115525A (en) * 1980-02-18 1981-09-10 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
KR900001062B1 (ko) * 1987-09-15 1990-02-26 강진구 반도체 바이 씨 모오스 장치의 제조방법
US5273915A (en) * 1992-10-05 1993-12-28 Motorola, Inc. Method for fabricating bipolar junction and MOS transistors on SOI
US5541124A (en) * 1993-02-28 1996-07-30 Sony Corporation Method for making bipolar transistor having double polysilicon structure
CN1052341C (zh) * 1993-03-26 2000-05-10 松下电器产业株式会社 半导体器件及其制造方法
JP2630237B2 (ja) * 1993-12-22 1997-07-16 日本電気株式会社 半導体装置及びその製造方法
JP2606141B2 (ja) * 1994-06-16 1997-04-30 日本電気株式会社 半導体装置およびその製造方法
JP3551489B2 (ja) * 1994-08-29 2004-08-04 ソニー株式会社 半導体装置の製造方法
US5670394A (en) * 1994-10-03 1997-09-23 United Technologies Corporation Method of making bipolar transistor having amorphous silicon contact as emitter diffusion source
US5593905A (en) * 1995-02-23 1997-01-14 Texas Instruments Incorporated Method of forming stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link
JP2914213B2 (ja) * 1995-03-28 1999-06-28 日本電気株式会社 半導体装置及びその製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5739567A (en) * 1980-07-18 1982-03-04 Nec Corp Manufacture of semiconductor device
EP0342695A2 (en) * 1988-05-20 1989-11-23 Fujitsu Limited Semiconductor device
US5137840A (en) * 1990-10-24 1992-08-11 International Business Machines Corporation Vertical bipolar transistor with recessed epitaxially grown intrinsic base region
US5494836A (en) * 1993-04-05 1996-02-27 Nec Corporation Process of producing heterojunction bipolar transistor with silicon-germanium base
US5523606A (en) * 1993-10-07 1996-06-04 Nec Corporation BiCMOS semiconductor device having SiGe heterojunction and Si homo-junction transistors
JPH09162296A (ja) * 1995-12-12 1997-06-20 Sony Corp 半導体装置およびその製造方法
US5976940A (en) * 1995-12-12 1999-11-02 Sony Corporation Method of making plurality of bipolar transistors

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 006, no. 107 (E - 113) 17 June 1982 (1982-06-17) *
PATENT ABSTRACTS OF JAPAN vol. 1997, no. 10 31 October 1997 (1997-10-31) *

Also Published As

Publication number Publication date
NL1007898A1 (nl) 1998-06-29
KR19980064697A (ko) 1998-10-07
DE19757685A1 (de) 1998-07-02
JPH10189754A (ja) 1998-07-21
JP3409618B2 (ja) 2003-05-26
US5915186A (en) 1999-06-22

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